1/* $NetBSD: intmmu.S,v 1.7 2005/05/21 11:46:56 rearnsha Exp $ */ 2 3/* 4 * Copyright (c) 2001 ARM Ltd 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the company may not be used to endorse or promote 16 * products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#include "assym.h" 33#include <machine/asm.h> 34#include <arm/armreg.h> 35#include <arm/arm32/pte.h> 36 37 .section .start,"ax",%progbits 38 39ASENTRY_NP(integrator_start) 40 mov r6, #0x16000000 /* UART0 Physical base*/ 41#ifdef VERBOSE_INIT_ARM 42 mov r3, #'A' 43 str r3, [r6] /* Let the world know we are alive */ 44#endif 45/* 46 * Check that the processor has a CP15. Some core modules do not. 47 * We can tell by reading CM_PROC. If it is zero, then we're OK, otherwise 48 * let the user know why we've died. 49 */ 50 mov r7, #0x10000000 51 ldr r3, [r7, #4] 52 cmp r3, #0 53 bne Lno_cp15 54/* 55 * Now read CP15 and check what sort of core we have. We need to know 56 * if it has an MMU. There's no simple test for this, but the following 57 * hack should be sufficient for all currently supported CM boards. 58 * 1) Check that the architecture is less than v6 (V6 has feature registers) 59 * 2) Check that the product code has a '2' in bits 8-11 60 */ 61 mrc p15, 0, r3, c0, c0, 0 62 and r0, r3, #0x000f0000 63 cmp r0, #0x00060000 64 bhs Lno_v6 65 and r0, r3, #0x00000f00 66 teq r0, #0x00000200 67 bne Lno_mmu 68 69/* 70 * At this time the MMU is off. 71 * We build up an initial memory map at 0x8000 that we can use to get 72 * the kernel running from the top of memory. All mappings in this table 73 * use L1 section maps. 74 */ 75 76/* 77 * Set Virtual == Physical 78 */ 79 mov r3, #(L1_S_AP(AP_KRW)) 80 add r3, r3, #(L1_TYPE_S) 81 mov r2, #0x100000 /* advance by 1MB */ 82 mov r1, #0x8000 /* page table start */ 83 mov r0, #0x1000 /* page table size */ 84 85Lflat: 86 str r3, [r1], #0x0004 87 add r3, r3, r2 88 subs r0, r0, #1 89 bgt Lflat 90 91/* 92 * Map VA 0xc0000000->0xc03fffff to PA 0x00000000->0x003fffff 93 */ 94 mov r3, #(L1_S_AP(AP_KRW)) 95 add r3, r3, #(L1_TYPE_S) 96 mov r1, #0x8000 /* page table start */ 97 add r1, r1, #(0xc00 * 4) /* offset to 0xc00xxxxx */ 98# add r1, r1, #(0x001 * 4) /* offset to 0xc01xxxxx */ 99 mov r0, #63 100Lkern: 101 str r3, [r1], #0x0004 /* 0xc000000-0xc03fffff */ 102 add r3, r3, r2 103 subs r0, r0, #1 104 bgt Lkern 105/* 106 * Mapping the peripheral register region (0x10000000->0x1fffffff) linearly 107 * would require 256MB of virtual memory (as much space as the entire kernel 108 * virtual space). So we map the first 1M of each 16MB sub-space into the 109 * region VA 0xfd000000->0xfdffffff; this should map enough of the peripheral 110 * space to at least get us up and running. 111 */ 112 mov r3, #(L1_S_AP(AP_KRW)) 113 add r3, r3, #L1_TYPE_S 114 add r3, r3, #0x10000000 /* Peripherals base */ 115 mov r1, #0x8000 /* page table start */ 116 add r1, r1, #(0xfd0 * 4) 117 mov r2, #0x01000000 /* 16MB increment. */ 118 mov r0, #16 119Lperiph: 120 str r3, [r1], #4 /* 0xfd000000-0xfdffffff */ 121 add r3, r3, r2 122 subs r0, r0, #1 123 bgt Lperiph 124 125/* 126 * We now have our page table ready, so load it up and light the blue 127 * touch paper. 128 */ 129 130 /* set the location of the L1 page table */ 131 mov r1, #0x8000 132 mcr p15, 0, r1, c2, c0, 0 133 134 /* Flush the old TLBs (just in case) */ 135 mcr p15, 0, r1, c8, c7, 0 136#ifdef VERBOSE_INIT_ARM 137 mov r2, #'B' 138 strb r2, [r6] 139#endif 140 141 /* Set the Domain Access register. Very important! */ 142 mov r1, #1 143 mcr p15, 0, r1, c3, c0, 0 144 145 /* 146 * set mmu bit (don't set anything else for now, we don't know 147 * what sort of CPU we have yet. 148 */ 149 mov r1, #CPU_CONTROL_MMU_ENABLE 150 151/* 152 * This is where it might all start to go wrong if the CPU fitted to your 153 * integrator does not have an MMU. 154 */ 155 /* fetch current control state */ 156 mrc p15, 0, r2, c1, c0, 0 157 orr r2, r2, r1 158 159 /* set new control state */ 160 mcr p15, 0, r2, c1, c0, 0 161 162 mov r0, r0 163 mov r0, r0 164 mov r0, r0 165 166#ifdef VERBOSE_INIT_ARM 167 /* emit a char. Uart is now at 0xfd600000 */ 168 mov r6, #0xfd000000 169 add r6, r6, #0x00600000 170 mov r2, #'C' 171 strb r2, [r6] 172#endif 173 174 /* jump to kernel space */ 175 mov r0, #0x0200 176 177 /* Switch to kernel VM and really set the ball rolling. */ 178 ldr pc, Lstart 179 180Lstart: .long start 181 182Lmsg: 183 ldrb r2, [r0], #1 184 cmp r2, #0 185 strneb r2, [r6] 186Lwait: 187 ldrb r3, [r6, #0x18] 188 tst r3, #0x80 189 beq Lwait 190 cmp r2, #0 191 bne Lmsg 192 /* We're toast! */ 193 b . 194 195Lno_cp15: 196 adr r0, Lcp15msg 197 b Lmsg 198Lno_v6: 199 adr r0, Lv6msg 200 b Lmsg 201Lno_mmu: 202 adr r0, Lmmumsg 203 b Lmsg 204 205Lcp15msg: 206 .ascii "Core has no cp15\r\n\0" 207Lv6msg: 208 .ascii "Architecture v6 not yet supported\r\n\0" 209Lmmumsg: 210 .ascii "Core has no MMU\r\n\0" 211