1*beecddb6Sthorpej /* $NetBSD: zs_sbdio.c,v 1.14 2021/08/07 16:18:53 thorpej Exp $ */
204faabf0Stsutsui
304faabf0Stsutsui /*-
404faabf0Stsutsui * Copyright (c) 1996, 2005 The NetBSD Foundation, Inc.
504faabf0Stsutsui * All rights reserved.
604faabf0Stsutsui *
704faabf0Stsutsui * This code is derived from software contributed to The NetBSD Foundation
804faabf0Stsutsui * by Gordon W. Ross.
904faabf0Stsutsui *
1004faabf0Stsutsui * Redistribution and use in source and binary forms, with or without
1104faabf0Stsutsui * modification, are permitted provided that the following conditions
1204faabf0Stsutsui * are met:
1304faabf0Stsutsui * 1. Redistributions of source code must retain the above copyright
1404faabf0Stsutsui * notice, this list of conditions and the following disclaimer.
1504faabf0Stsutsui * 2. Redistributions in binary form must reproduce the above copyright
1604faabf0Stsutsui * notice, this list of conditions and the following disclaimer in the
1704faabf0Stsutsui * documentation and/or other materials provided with the distribution.
1804faabf0Stsutsui *
1904faabf0Stsutsui * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
2004faabf0Stsutsui * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
2104faabf0Stsutsui * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
2204faabf0Stsutsui * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
2304faabf0Stsutsui * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2404faabf0Stsutsui * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2504faabf0Stsutsui * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2604faabf0Stsutsui * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2704faabf0Stsutsui * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2804faabf0Stsutsui * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2904faabf0Stsutsui * POSSIBILITY OF SUCH DAMAGE.
3004faabf0Stsutsui */
3104faabf0Stsutsui
3204faabf0Stsutsui /*
3304faabf0Stsutsui * Zilog Z8530 Dual UART driver (machine-dependent part)
3404faabf0Stsutsui *
3504faabf0Stsutsui * Runs two serial lines per chip using slave drivers.
3604faabf0Stsutsui * Plain tty/async lines use the zs_async slave.
3704faabf0Stsutsui */
3804faabf0Stsutsui
3904faabf0Stsutsui #include <sys/cdefs.h>
40*beecddb6Sthorpej __KERNEL_RCSID(0, "$NetBSD: zs_sbdio.c,v 1.14 2021/08/07 16:18:53 thorpej Exp $");
4104faabf0Stsutsui
4204faabf0Stsutsui #include <sys/param.h>
4304faabf0Stsutsui #include <sys/systm.h>
4404faabf0Stsutsui #include <sys/device.h>
4504faabf0Stsutsui #include <sys/tty.h>
4604faabf0Stsutsui #include <sys/conf.h>
4734db2867Sad #include <sys/intr.h>
4804faabf0Stsutsui
4904faabf0Stsutsui #include <dev/cons.h>
5004faabf0Stsutsui #include <dev/ic/z8530reg.h>
5104faabf0Stsutsui
5298ed9c25Smatt #include <mips/locore.h>
5398ed9c25Smatt
5404faabf0Stsutsui #include <machine/sbdiovar.h>
5504faabf0Stsutsui #include <machine/z8530var.h>
5604faabf0Stsutsui
5704faabf0Stsutsui #define ZS_DEFSPEED 9600
5804faabf0Stsutsui #define PCLK (9600 * 512) /* 4.915200MHz */
5904faabf0Stsutsui
6004faabf0Stsutsui /* The layout of this is hardware-dependent (padding, order). */
6104faabf0Stsutsui struct zschan {
6204faabf0Stsutsui volatile uint8_t zc_csr; /* ctrl, status, and indirect access */
6304faabf0Stsutsui uint8_t padding1[3];
6404faabf0Stsutsui volatile uint8_t zc_data; /* data */
6504faabf0Stsutsui uint8_t padding2[3];
6604faabf0Stsutsui } __attribute__((__packed__));
6704faabf0Stsutsui
6804faabf0Stsutsui struct zsdevice {
6904faabf0Stsutsui /* Yes, they are backwards. */
7004faabf0Stsutsui struct zschan zs_chan_b;
7104faabf0Stsutsui struct zschan zs_chan_a;
7204faabf0Stsutsui } __attribute__((__packed__));
7304faabf0Stsutsui
7404faabf0Stsutsui static uint8_t zs_init_reg[16] = {
7504faabf0Stsutsui 0, /* 0: CMD (reset, etc.) */
7604faabf0Stsutsui 0, /* 1: No interrupts yet. */
7704faabf0Stsutsui 0, /* 2: IVECT EWS-UX don't set this. */
7804faabf0Stsutsui ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
7904faabf0Stsutsui ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
8004faabf0Stsutsui ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
8104faabf0Stsutsui 0, /* 6: TXSYNC/SYNCLO */
8204faabf0Stsutsui 0, /* 7: RXSYNC/SYNCHI */
8304faabf0Stsutsui 0, /* 8: alias for data port */
8404faabf0Stsutsui ZSWR9_MASTER_IE,
8504faabf0Stsutsui 0, /* 10: Misc. TX/RX control bits */
8604faabf0Stsutsui ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
8704faabf0Stsutsui BPS_TO_TCONST((PCLK/16), ZS_DEFSPEED), /* 12: BAUDLO (default=9600) */
8804faabf0Stsutsui 0, /*13: BAUDHI (default=9600) */
8904faabf0Stsutsui ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
9004faabf0Stsutsui ZSWR15_BREAK_IE,
9104faabf0Stsutsui };
9204faabf0Stsutsui
937b2990daStsutsui static int zs_sbdio_match(device_t, cfdata_t, void *);
947b2990daStsutsui static void zs_sbdio_attach(device_t, device_t, void *);
9504faabf0Stsutsui
9602cb47caStsutsui CFATTACH_DECL_NEW(zsc_sbdio, sizeof(struct zsc_softc),
9704faabf0Stsutsui zs_sbdio_match, zs_sbdio_attach, NULL, NULL);
9804faabf0Stsutsui
9904faabf0Stsutsui int
zs_sbdio_match(device_t parent,cfdata_t cf,void * aux)1007b2990daStsutsui zs_sbdio_match(device_t parent, cfdata_t cf, void *aux)
10104faabf0Stsutsui {
10204faabf0Stsutsui struct sbdio_attach_args *sa = aux;
10304faabf0Stsutsui
10404faabf0Stsutsui return strcmp(sa->sa_name, "zsc") ? 0 : 1;
10504faabf0Stsutsui }
10604faabf0Stsutsui
10704faabf0Stsutsui void
zs_sbdio_attach(device_t parent,device_t self,void * aux)1087b2990daStsutsui zs_sbdio_attach(device_t parent, device_t self, void *aux)
10904faabf0Stsutsui {
11002cb47caStsutsui struct zsc_softc *zsc = device_private(self);
1117b2990daStsutsui struct sbdio_attach_args *sa = aux;
11204faabf0Stsutsui struct zsc_attach_args zsc_args;
11304faabf0Stsutsui struct zschan *zc;
11404faabf0Stsutsui struct zs_chanstate *cs;
11504faabf0Stsutsui struct zsdevice *zs_addr;
11667b37d93Schristos int s, channel;
11704faabf0Stsutsui
11802cb47caStsutsui zsc->zsc_dev = self;
1197b2990daStsutsui aprint_normal("\n");
12004faabf0Stsutsui
12104faabf0Stsutsui zs_addr = (void *)MIPS_PHYS_TO_KSEG1(sa->sa_addr1);
12204faabf0Stsutsui zsc->zsc_flags = sa->sa_flags;
12304faabf0Stsutsui
12404faabf0Stsutsui /*
12504faabf0Stsutsui * Initialize software state for each channel.
12604faabf0Stsutsui */
12704faabf0Stsutsui for (channel = 0; channel < 2; channel++) {
12804faabf0Stsutsui zsc_args.channel = channel;
12904faabf0Stsutsui zsc_args.hwflags = 0;
13004faabf0Stsutsui cs = &zsc->zsc_cs_store[channel];
13104faabf0Stsutsui zsc->zsc_cs[channel] = cs;
13204faabf0Stsutsui
13304faabf0Stsutsui cs->cs_channel = channel;
13404faabf0Stsutsui cs->cs_private = NULL;
13504faabf0Stsutsui cs->cs_ops = &zsops_null;
13604faabf0Stsutsui
13704faabf0Stsutsui if (channel == 0)
13804faabf0Stsutsui zc = &zs_addr->zs_chan_a;
13904faabf0Stsutsui else
14004faabf0Stsutsui zc = &zs_addr->zs_chan_b;
14104faabf0Stsutsui
14204faabf0Stsutsui if (zc == zs_consaddr) {
14304faabf0Stsutsui memcpy(cs, zs_conscs, sizeof(struct zs_chanstate));
14404faabf0Stsutsui zs_conscs = cs;
14504faabf0Stsutsui zsc_args.hwflags = ZS_HWFLAG_CONSOLE;
14604faabf0Stsutsui } else {
14704faabf0Stsutsui cs->cs_reg_csr = &zc->zc_csr;
14804faabf0Stsutsui cs->cs_reg_data = &zc->zc_data;
14904faabf0Stsutsui memcpy(cs->cs_creg, zs_init_reg, 16);
15004faabf0Stsutsui memcpy(cs->cs_preg, zs_init_reg, 16);
15104faabf0Stsutsui cs->cs_defspeed = ZS_DEFSPEED;
15204faabf0Stsutsui zsc_args.hwflags = 0;
15304faabf0Stsutsui }
15404faabf0Stsutsui
155f2c57d85Sad zs_lock_init(cs);
15604faabf0Stsutsui cs->cs_brg_clk = PCLK / 16;
15704faabf0Stsutsui cs->cs_defcflag = zs_def_cflag;
15804faabf0Stsutsui
15904faabf0Stsutsui /* Make these correspond to cs_defcflag (-crtscts) */
16004faabf0Stsutsui cs->cs_rr0_dcd = ZSRR0_DCD;
16104faabf0Stsutsui cs->cs_rr0_cts = 0;
16204faabf0Stsutsui cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
16304faabf0Stsutsui cs->cs_wr5_rts = 0;
16404faabf0Stsutsui
16504faabf0Stsutsui /*
16604faabf0Stsutsui * Clear the master interrupt enable.
16704faabf0Stsutsui * The INTENA is common to both channels,
16804faabf0Stsutsui * so just do it on the A channel.
16904faabf0Stsutsui */
17004faabf0Stsutsui if (channel == 0) {
17104faabf0Stsutsui zs_write_reg(cs, 9, 0);
17204faabf0Stsutsui }
17304faabf0Stsutsui
17404faabf0Stsutsui /*
17504faabf0Stsutsui * Look for a child driver for this channel.
17604faabf0Stsutsui * The child attach will setup the hardware.
17704faabf0Stsutsui */
1783bee0c11Sthorpej if (!config_found(self, (void *)&zsc_args, zs_print,
179*beecddb6Sthorpej CFARGS_NONE)) {
18004faabf0Stsutsui /* No sub-driver. Just reset it. */
18104faabf0Stsutsui uint8_t reset = (channel == 0) ?
18204faabf0Stsutsui ZSWR9_A_RESET : ZSWR9_B_RESET;
18304faabf0Stsutsui s = splhigh();
18404faabf0Stsutsui zs_write_reg(cs, 9, reset);
18504faabf0Stsutsui splx(s);
18604faabf0Stsutsui }
18704faabf0Stsutsui }
18804faabf0Stsutsui
18934db2867Sad zsc->zsc_si = softint_establish(SOFTINT_SERIAL,
19057a0051fStsutsui (void (*)(void *))zsc_intr_soft, zsc);
19157a0051fStsutsui intr_establish(sa->sa_irq, zshard, zsc);
19204faabf0Stsutsui
19304faabf0Stsutsui /*
19404faabf0Stsutsui * Set the master interrupt enable and interrupt vector.
19504faabf0Stsutsui * (common to both channels, do it on A)
19604faabf0Stsutsui */
19704faabf0Stsutsui cs = zsc->zsc_cs[0];
19804faabf0Stsutsui s = splhigh();
19904faabf0Stsutsui /* interrupt vector */
20004faabf0Stsutsui zs_write_reg(cs, 2, zs_init_reg[2]);
20104faabf0Stsutsui /* master interrupt control (enable) */
20204faabf0Stsutsui zs_write_reg(cs, 9, zs_init_reg[9]);
20304faabf0Stsutsui splx(s);
20404faabf0Stsutsui }
20504faabf0Stsutsui
20604faabf0Stsutsui /*
20704faabf0Stsutsui * console stuff
20804faabf0Stsutsui */
20904faabf0Stsutsui
21004faabf0Stsutsui static void zs_sbdio_cnprobe(struct consdev *);
21104faabf0Stsutsui static void zs_sbdio_cninit(struct consdev *);
21204faabf0Stsutsui
21304faabf0Stsutsui struct consdev consdev_zs_sbdio = {
21404faabf0Stsutsui zs_sbdio_cnprobe,
21504faabf0Stsutsui zs_sbdio_cninit,
21604faabf0Stsutsui zscngetc,
21704faabf0Stsutsui zscnputc,
21804faabf0Stsutsui nullcnpollc,
21904faabf0Stsutsui NULL,
22004faabf0Stsutsui NULL,
22104faabf0Stsutsui NULL,
22204faabf0Stsutsui NODEV,
22304faabf0Stsutsui CN_DEAD
22404faabf0Stsutsui };
22504faabf0Stsutsui
22604faabf0Stsutsui static void
zs_sbdio_cnprobe(struct consdev * cn)22704faabf0Stsutsui zs_sbdio_cnprobe(struct consdev *cn)
22804faabf0Stsutsui {
22904faabf0Stsutsui
23004faabf0Stsutsui /* not used */
23104faabf0Stsutsui }
23204faabf0Stsutsui
23304faabf0Stsutsui static void
zs_sbdio_cninit(struct consdev * cn)23404faabf0Stsutsui zs_sbdio_cninit(struct consdev *cn)
23504faabf0Stsutsui {
23604faabf0Stsutsui struct zs_chanstate *cs;
23704faabf0Stsutsui struct zschan *zc;
23804faabf0Stsutsui
23904faabf0Stsutsui zc = zs_consaddr;
24004faabf0Stsutsui cs = zs_conscs;
24104faabf0Stsutsui
24204faabf0Stsutsui /* Setup temporary chanstate. */
24304faabf0Stsutsui cs->cs_reg_csr = &zc->zc_csr;
24404faabf0Stsutsui cs->cs_reg_data = &zc->zc_data;
24504faabf0Stsutsui
24604faabf0Stsutsui /* Initialize the pending registers. */
24704faabf0Stsutsui memcpy(cs->cs_preg, zs_init_reg, 16);
24804faabf0Stsutsui cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
24904faabf0Stsutsui
25004faabf0Stsutsui cs->cs_brg_clk = PCLK / 16;
25104faabf0Stsutsui cs->cs_defspeed = ZS_DEFSPEED;
25204faabf0Stsutsui zs_set_speed(cs, ZS_DEFSPEED);
25304faabf0Stsutsui
25404faabf0Stsutsui /* Clear the master interrupt enable. */
25504faabf0Stsutsui zs_write_reg(cs, 9, 0);
25604faabf0Stsutsui
25704faabf0Stsutsui /* Reset the whole SCC chip. */
25804faabf0Stsutsui zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
25904faabf0Stsutsui
26004faabf0Stsutsui /* Copy "pending" to "current" and H/W */
26104faabf0Stsutsui zs_loadchannelregs(cs);
26204faabf0Stsutsui }
263