1*825088edSmatt /* $NetBSD: irqhandler.h,v 1.5 2008/04/27 18:58:47 matt Exp $ */ 280675955Sthorpej 380675955Sthorpej /* 480675955Sthorpej * Copyright (c) 1994-1996 Mark Brinicombe. 580675955Sthorpej * Copyright (c) 1994 Brini. 680675955Sthorpej * All rights reserved. 780675955Sthorpej * 880675955Sthorpej * This code is derived from software written for Brini by Mark Brinicombe 980675955Sthorpej * 1080675955Sthorpej * Redistribution and use in source and binary forms, with or without 1180675955Sthorpej * modification, are permitted provided that the following conditions 1280675955Sthorpej * are met: 1380675955Sthorpej * 1. Redistributions of source code must retain the above copyright 1480675955Sthorpej * notice, this list of conditions and the following disclaimer. 1580675955Sthorpej * 2. Redistributions in binary form must reproduce the above copyright 1680675955Sthorpej * notice, this list of conditions and the following disclaimer in the 1780675955Sthorpej * documentation and/or other materials provided with the distribution. 1880675955Sthorpej * 3. All advertising materials mentioning features or use of this software 1980675955Sthorpej * must display the following acknowledgement: 2080675955Sthorpej * This product includes software developed by Mark Brinicombe 2180675955Sthorpej * for the NetBSD Project. 2280675955Sthorpej * 4. The name of the company nor the name of the author may be used to 2380675955Sthorpej * endorse or promote products derived from this software without specific 2480675955Sthorpej * prior written permission. 2580675955Sthorpej * 2680675955Sthorpej * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 2780675955Sthorpej * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 2880675955Sthorpej * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2980675955Sthorpej * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 3080675955Sthorpej * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 3180675955Sthorpej * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 3280675955Sthorpej * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 3380675955Sthorpej * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3480675955Sthorpej * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3580675955Sthorpej * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3680675955Sthorpej * SUCH DAMAGE. 3780675955Sthorpej * 3880675955Sthorpej * IRQ related stuff (defines + structures) 3980675955Sthorpej * 4080675955Sthorpej * Created : 30/09/94 4180675955Sthorpej */ 4280675955Sthorpej 4380675955Sthorpej #ifndef _ARM32_IRQHANDLER_H_ 4480675955Sthorpej #define _ARM32_IRQHANDLER_H_ 4580675955Sthorpej 4680675955Sthorpej #ifndef _LOCORE 4780675955Sthorpej #include <sys/types.h> 482c6d199dSmatt #include <sys/evcnt.h> 4980675955Sthorpej #endif /* _LOCORE */ 5080675955Sthorpej 5180675955Sthorpej /* Define the IRQ bits */ 5280675955Sthorpej 5380675955Sthorpej /* 5480675955Sthorpej * XXX this is really getting rather horrible. 5580675955Sthorpej * Shortly to be replaced with system specific interrupt tables and handling 5680675955Sthorpej */ 5780675955Sthorpej 5880675955Sthorpej #ifdef OFWGENCFG 5980675955Sthorpej /* These are just made up for now! -JJK */ 6080675955Sthorpej #define IRQ_TIMER0 0 6180675955Sthorpej #endif 6280675955Sthorpej 6380675955Sthorpej #ifdef SHARK 6480675955Sthorpej /* 6580675955Sthorpej * shark hardware requirements for IRQ's: 6680675955Sthorpej * IDE: 14 (hardwired) 6780675955Sthorpej * PCI: 5, 9, 10, 11, 15(mapped to UMIPCI inta, intb, intc, intd) 6880675955Sthorpej * UMIISA: 10, 11, 12 6980675955Sthorpej * SuperIO: 1, 3..12, 14, 15(all may be remapped. defaults as follows.) 7080675955Sthorpej * KBC: 1 7180675955Sthorpej * USI: 3 (UART with Slow Infrared support) 7280675955Sthorpej * UART: 4 7380675955Sthorpej * FLOPPY: 6 (not currently used on shark) 7480675955Sthorpej * PARALLEL: 7 7580675955Sthorpej * RTC: 8 (not used on shark: RTC in sequoia used) 7680675955Sthorpej * MOUSE: 12 7780675955Sthorpej * Sequoia: 8 (internal RTC hardwired to irq 8) 7880675955Sthorpej * Codec: 5, 7, 9, 10, 15 (irqe, connected to 15, has special status.) 7980675955Sthorpej * CS8900: 5, 10, 11, 12 (P.14 of datasheet sez only 1 used/time) 8080675955Sthorpej * FERR#: 13 (unconnected floating point error) 8180675955Sthorpej * 8280675955Sthorpej * total of 15 irqs: 8380675955Sthorpej * timer, ide, 2 umi = isa/pci, ethernet, 2 codec, kb, usi, uart, floppy, 8480675955Sthorpej * parallel, rtc, mouse, ferr (irq 13) 8580675955Sthorpej * 8680675955Sthorpej * eventually, need to read the OFW dev info tree, and allocate IRQs. 8780675955Sthorpej * hardcoded for now. 8880675955Sthorpej */ 8980675955Sthorpej #define IRQ_TIMER0 0x00 /* hardwired to 8254 counter 0 in sequoia */ 9080675955Sthorpej #define IRQ_KEYBOARD 0x01 9180675955Sthorpej #define IRQ_CASCADE 0x02 /* hardwired IRQ for second 8259 = IRQ_SLAVE */ 9280675955Sthorpej #define IRQ_USI 0x03 9380675955Sthorpej #define IRQ_UART 0x04 9480675955Sthorpej #define IRQ_ETHERNET 0x05 9580675955Sthorpej #define IRQ_FLOPPY 0x06 9680675955Sthorpej #define IRQ_PARALLEL 0x07 97d471ccf3Smatt #endif 9880675955Sthorpej 99d471ccf3Smatt #if defined(SHARK) || defined(OFWGENCFG) 10080675955Sthorpej #define IRQ_RTC 0x08 /* hardwired to the sequoia RTC */ 101d471ccf3Smatt #endif 102d471ccf3Smatt #ifdef SHARK 10380675955Sthorpej #define IRQ_CODEC1 0x09 10480675955Sthorpej #define IRQ_UMI1 0x0A /* isa or pci */ 10580675955Sthorpej #define IRQ_UMI2 0x0B /* isa or pci */ 10680675955Sthorpej 10780675955Sthorpej #define IRQ_MOUSE 0x0C 10880675955Sthorpej #define IRQ_FERR 0x0D /* FERR# pin on sequoia needs to be connected */ 10980675955Sthorpej #define IRQ_IDE 0x0E /* hardwired to the IDE connector */ 11080675955Sthorpej #define IRQ_CODEC2 0x0F /* special interrupt on codec */ 11180675955Sthorpej #endif /* SHARK */ 11280675955Sthorpej 11380675955Sthorpej #define IRQ_VSYNC IRQ_FLYBACK /* Aliased */ 11480675955Sthorpej #define IRQ_NETSLOT IRQ_EXTENDED 11580675955Sthorpej 11680675955Sthorpej #define IRQ_INSTRUCT -1 11780675955Sthorpej #define NIRQS 0x20 11880675955Sthorpej 11980675955Sthorpej #include <machine/intr.h> 12080675955Sthorpej 12180675955Sthorpej #ifndef _LOCORE 12280675955Sthorpej typedef struct irqhandler { 123d471ccf3Smatt int (*ih_func)(void *arg); /* handler function */ 12480675955Sthorpej void *ih_arg; /* Argument to handler */ 12580675955Sthorpej int ih_level; /* Interrupt level */ 12680675955Sthorpej int ih_num; /* Interrupt number (for accounting) */ 12780675955Sthorpej u_int ih_flags; /* Interrupt flags */ 12880675955Sthorpej u_int ih_maskaddr; /* mask address for expansion cards */ 12980675955Sthorpej u_int ih_maskbits; /* interrupt bit for expansion cards */ 13080675955Sthorpej struct irqhandler *ih_next; /* next handler */ 1312c6d199dSmatt struct evcnt ih_ev; /* evcnt structure */ 132503fb648Sad int (*ih_realfunc)(void *arg); /* XXX real handler function */ 133503fb648Sad void *ih_realarg; 13480675955Sthorpej } irqhandler_t; 13580675955Sthorpej 13680675955Sthorpej #ifdef _KERNEL 137*825088edSmatt extern u_int irqmasks[NIPL]; 13880675955Sthorpej extern irqhandler_t *irqhandlers[NIRQS]; 13980675955Sthorpej 140d471ccf3Smatt void irq_init(void); 141d471ccf3Smatt int irq_claim(int, irqhandler_t *, const char *group, const char *name); 142d471ccf3Smatt int irq_release(int, irqhandler_t *); 143d471ccf3Smatt void *intr_claim(int irq, int level, int (*func)(void *), void *arg, 144d471ccf3Smatt const char *group, const char *name); 145d471ccf3Smatt int intr_release(void *ih); 146d471ccf3Smatt void irq_setmasks(void); 147d471ccf3Smatt void disable_irq(int); 148d471ccf3Smatt void enable_irq(int); 14980675955Sthorpej #endif /* _KERNEL */ 15080675955Sthorpej #endif /* _LOCORE */ 15180675955Sthorpej 15280675955Sthorpej #define IRQ_FLAG_ACTIVE 0x00000001 /* This is the active handler in list */ 15380675955Sthorpej 15480675955Sthorpej #endif /* _ARM32_IRQHANDLER_H_ */ 15580675955Sthorpej 15680675955Sthorpej /* End of irqhandler.h */ 157