1 /* $NetBSD: fpu_subr.c,v 1.6 2005/12/11 12:19:05 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)fpu_subr.c 8.1 (Berkeley) 6/11/93 41 */ 42 43 /* 44 * FPU subroutines. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: fpu_subr.c,v 1.6 2005/12/11 12:19:05 christos Exp $"); 49 50 #include <sys/types.h> 51 #ifdef DIAGNOSTIC 52 #include <sys/systm.h> 53 #endif 54 55 #include <machine/reg.h> 56 #include <machine/instr.h> 57 58 #include <sparc/fpu/fpu_arith.h> 59 #include <sparc/fpu/fpu_emu.h> 60 #include <sparc/fpu/fpu_extern.h> 61 62 /* 63 * Shift the given number right rsh bits. Any bits that `fall off' will get 64 * shoved into the sticky field; we return the resulting sticky. Note that 65 * shifting NaNs is legal (this will never shift all bits out); a NaN's 66 * sticky field is ignored anyway. 67 */ 68 int 69 fpu_shr(register struct fpn *fp, register int rsh) 70 { 71 register u_int m0, m1, m2, m3, s; 72 register int lsh; 73 74 #ifdef DIAGNOSTIC 75 if (rsh <= 0 || (fp->fp_class != FPC_NUM && !ISNAN(fp))) 76 panic("fpu_rightshift 1"); 77 #endif 78 79 m0 = fp->fp_mant[0]; 80 m1 = fp->fp_mant[1]; 81 m2 = fp->fp_mant[2]; 82 m3 = fp->fp_mant[3]; 83 84 /* If shifting all the bits out, take a shortcut. */ 85 if (rsh >= FP_NMANT) { 86 #ifdef DIAGNOSTIC 87 if ((m0 | m1 | m2 | m3) == 0) 88 panic("fpu_rightshift 2"); 89 #endif 90 fp->fp_mant[0] = 0; 91 fp->fp_mant[1] = 0; 92 fp->fp_mant[2] = 0; 93 fp->fp_mant[3] = 0; 94 #ifdef notdef 95 if ((m0 | m1 | m2 | m3) == 0) 96 fp->fp_class = FPC_ZERO; 97 else 98 #endif 99 fp->fp_sticky = 1; 100 return (1); 101 } 102 103 /* Squish out full words. */ 104 s = fp->fp_sticky; 105 if (rsh >= 32 * 3) { 106 s |= m3 | m2 | m1; 107 m3 = m0, m2 = 0, m1 = 0, m0 = 0; 108 } else if (rsh >= 32 * 2) { 109 s |= m3 | m2; 110 m3 = m1, m2 = m0, m1 = 0, m0 = 0; 111 } else if (rsh >= 32) { 112 s |= m3; 113 m3 = m2, m2 = m1, m1 = m0, m0 = 0; 114 } 115 116 /* Handle any remaining partial word. */ 117 if ((rsh &= 31) != 0) { 118 lsh = 32 - rsh; 119 s |= m3 << lsh; 120 m3 = (m3 >> rsh) | (m2 << lsh); 121 m2 = (m2 >> rsh) | (m1 << lsh); 122 m1 = (m1 >> rsh) | (m0 << lsh); 123 m0 >>= rsh; 124 } 125 fp->fp_mant[0] = m0; 126 fp->fp_mant[1] = m1; 127 fp->fp_mant[2] = m2; 128 fp->fp_mant[3] = m3; 129 fp->fp_sticky = s; 130 return (s); 131 } 132 133 /* 134 * Force a number to be normal, i.e., make its fraction have all zero 135 * bits before FP_1, then FP_1, then all 1 bits. This is used for denorms 136 * and (sometimes) for intermediate results. 137 * 138 * Internally, this may use a `supernormal' -- a number whose fp_mant 139 * is greater than or equal to 2.0 -- so as a side effect you can hand it 140 * a supernormal and it will fix it (provided fp->fp_mant[3] == 0). 141 */ 142 void 143 fpu_norm(register struct fpn *fp) 144 { 145 register u_int m0, m1, m2, m3, top, sup, nrm; 146 register int lsh, rsh, exp; 147 148 exp = fp->fp_exp; 149 m0 = fp->fp_mant[0]; 150 m1 = fp->fp_mant[1]; 151 m2 = fp->fp_mant[2]; 152 m3 = fp->fp_mant[3]; 153 154 /* Handle severe subnormals with 32-bit moves. */ 155 if (m0 == 0) { 156 if (m1) 157 m0 = m1, m1 = m2, m2 = m3, m3 = 0, exp -= 32; 158 else if (m2) 159 m0 = m2, m1 = m3, m2 = 0, m3 = 0, exp -= 2 * 32; 160 else if (m3) 161 m0 = m3, m1 = 0, m2 = 0, m3 = 0, exp -= 3 * 32; 162 else { 163 fp->fp_class = FPC_ZERO; 164 return; 165 } 166 } 167 168 /* Now fix any supernormal or remaining subnormal. */ 169 nrm = FP_1; 170 sup = nrm << 1; 171 if (m0 >= sup) { 172 /* 173 * We have a supernormal number. We need to shift it right. 174 * We may assume m3==0. 175 */ 176 for (rsh = 1, top = m0 >> 1; top >= sup; rsh++) /* XXX slow */ 177 top >>= 1; 178 exp += rsh; 179 lsh = 32 - rsh; 180 m3 = m2 << lsh; 181 m2 = (m2 >> rsh) | (m1 << lsh); 182 m1 = (m1 >> rsh) | (m0 << lsh); 183 m0 = top; 184 } else if (m0 < nrm) { 185 /* 186 * We have a regular denorm (a subnormal number), and need 187 * to shift it left. 188 */ 189 for (lsh = 1, top = m0 << 1; top < nrm; lsh++) /* XXX slow */ 190 top <<= 1; 191 exp -= lsh; 192 rsh = 32 - lsh; 193 m0 = top | (m1 >> rsh); 194 m1 = (m1 << lsh) | (m2 >> rsh); 195 m2 = (m2 << lsh) | (m3 >> rsh); 196 m3 <<= lsh; 197 } 198 199 fp->fp_exp = exp; 200 fp->fp_mant[0] = m0; 201 fp->fp_mant[1] = m1; 202 fp->fp_mant[2] = m2; 203 fp->fp_mant[3] = m3; 204 } 205 206 /* 207 * Concoct a `fresh' Quiet NaN per Appendix N. 208 * As a side effect, we set NV (invalid) for the current exceptions. 209 */ 210 struct fpn * 211 fpu_newnan(register struct fpemu *fe) 212 { 213 register struct fpn *fp; 214 215 fe->fe_cx = FSR_NV; 216 fp = &fe->fe_f3; 217 fp->fp_class = FPC_QNAN; 218 fp->fp_sign = 0; 219 fp->fp_mant[0] = FP_1 - 1; 220 fp->fp_mant[1] = fp->fp_mant[2] = fp->fp_mant[3] = ~0; 221 return (fp); 222 } 223