1*8a06b90dSskrll /* $NetBSD: bus_defs.h,v 1.2 2019/09/23 16:17:57 skrll Exp $ */ 2e57d534eSdyoung 3e57d534eSdyoung /*- 4e57d534eSdyoung * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 5e57d534eSdyoung * All rights reserved. 6e57d534eSdyoung * 7e57d534eSdyoung * This code is derived from software contributed to The NetBSD Foundation 8e57d534eSdyoung * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9e57d534eSdyoung * NASA Ames Research Center. 10e57d534eSdyoung * 11e57d534eSdyoung * Redistribution and use in source and binary forms, with or without 12e57d534eSdyoung * modification, are permitted provided that the following conditions 13e57d534eSdyoung * are met: 14e57d534eSdyoung * 1. Redistributions of source code must retain the above copyright 15e57d534eSdyoung * notice, this list of conditions and the following disclaimer. 16e57d534eSdyoung * 2. Redistributions in binary form must reproduce the above copyright 17e57d534eSdyoung * notice, this list of conditions and the following disclaimer in the 18e57d534eSdyoung * documentation and/or other materials provided with the distribution. 19e57d534eSdyoung * 20e57d534eSdyoung * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21e57d534eSdyoung * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22e57d534eSdyoung * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23e57d534eSdyoung * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24e57d534eSdyoung * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25e57d534eSdyoung * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26e57d534eSdyoung * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27e57d534eSdyoung * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28e57d534eSdyoung * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29e57d534eSdyoung * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30e57d534eSdyoung * POSSIBILITY OF SUCH DAMAGE. 31e57d534eSdyoung */ 32e57d534eSdyoung 33e57d534eSdyoung /* 34e57d534eSdyoung * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 35e57d534eSdyoung * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36e57d534eSdyoung * 37e57d534eSdyoung * Redistribution and use in source and binary forms, with or without 38e57d534eSdyoung * modification, are permitted provided that the following conditions 39e57d534eSdyoung * are met: 40e57d534eSdyoung * 1. Redistributions of source code must retain the above copyright 41e57d534eSdyoung * notice, this list of conditions and the following disclaimer. 42e57d534eSdyoung * 2. Redistributions in binary form must reproduce the above copyright 43e57d534eSdyoung * notice, this list of conditions and the following disclaimer in the 44e57d534eSdyoung * documentation and/or other materials provided with the distribution. 45e57d534eSdyoung * 3. All advertising materials mentioning features or use of this software 46e57d534eSdyoung * must display the following acknowledgement: 47e57d534eSdyoung * This product includes software developed by Christopher G. Demetriou 48e57d534eSdyoung * for the NetBSD Project. 49e57d534eSdyoung * 4. The name of the author may not be used to endorse or promote products 50e57d534eSdyoung * derived from this software without specific prior written permission 51e57d534eSdyoung * 52e57d534eSdyoung * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53e57d534eSdyoung * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54e57d534eSdyoung * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55e57d534eSdyoung * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56e57d534eSdyoung * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57e57d534eSdyoung * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58e57d534eSdyoung * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59e57d534eSdyoung * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60e57d534eSdyoung * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61e57d534eSdyoung * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62e57d534eSdyoung */ 63e57d534eSdyoung 64e57d534eSdyoung #ifndef _SPARC_BUS_DEFS_H_ 65e57d534eSdyoung #define _SPARC_BUS_DEFS_H_ 66e57d534eSdyoung 67e57d534eSdyoung /* 68e57d534eSdyoung * Bus address and size types 69e57d534eSdyoung */ 70e57d534eSdyoung typedef u_long bus_space_handle_t; 71*8a06b90dSskrll 72*8a06b90dSskrll #define PRIxBSH "lx" 73*8a06b90dSskrll 74e57d534eSdyoung typedef uint64_t bus_addr_t; 75e57d534eSdyoung typedef u_long bus_size_t; 76e57d534eSdyoung 77*8a06b90dSskrll #define PRIxBUSADDR PRIx64 78*8a06b90dSskrll #define PRIxBUSSIZE "lx" 79*8a06b90dSskrll #define PRIuBUSSIZE "lu" 80*8a06b90dSskrll 81e57d534eSdyoung #define SPARC_BUS_SPACE 0 82e57d534eSdyoung 83e57d534eSdyoung /* bus_addr_t is extended to 64-bits and has the iospace encoded in it */ 84e57d534eSdyoung #define BUS_ADDR_IOSPACE(x) ((x)>>32) 85e57d534eSdyoung #define BUS_ADDR_PADDR(x) ((x)&0xffffffff) 86e57d534eSdyoung #define BUS_ADDR(io, pa) \ 87e57d534eSdyoung ((((uint64_t)(uint32_t)(io))<<32) | (uint32_t)(pa)) 88e57d534eSdyoung 89e57d534eSdyoung #define __BUS_SPACE_HAS_STREAM_METHODS 1 90e57d534eSdyoung 91e57d534eSdyoung /* 92e57d534eSdyoung * Access methods for bus resources and address space. 93e57d534eSdyoung */ 94e57d534eSdyoung typedef struct sparc_bus_space_tag *bus_space_tag_t; 95e57d534eSdyoung 96e57d534eSdyoung struct sparc_bus_space_tag { 97e57d534eSdyoung void *cookie; 98e57d534eSdyoung bus_space_tag_t parent; 99e57d534eSdyoung 100e57d534eSdyoung /* 101e57d534eSdyoung * Windows onto the parent bus that this tag maps. If ranges 102e57d534eSdyoung * is non-NULL, the address will be translated, and recursively 103e57d534eSdyoung * mapped via the parent tag. 104e57d534eSdyoung */ 105e57d534eSdyoung struct openprom_range *ranges; 106e57d534eSdyoung int nranges; 107e57d534eSdyoung 108e57d534eSdyoung int (*sparc_bus_map)( 109e57d534eSdyoung bus_space_tag_t, 110e57d534eSdyoung bus_addr_t, 111e57d534eSdyoung bus_size_t, 112e57d534eSdyoung int, /*flags*/ 113e57d534eSdyoung vaddr_t, /*preferred vaddr*/ 114e57d534eSdyoung bus_space_handle_t *); 115e57d534eSdyoung int (*sparc_bus_unmap)( 116e57d534eSdyoung bus_space_tag_t, 117e57d534eSdyoung bus_space_handle_t, 118e57d534eSdyoung bus_size_t); 119e57d534eSdyoung int (*sparc_bus_subregion)( 120e57d534eSdyoung bus_space_tag_t, 121e57d534eSdyoung bus_space_handle_t, 122e57d534eSdyoung bus_size_t, /*offset*/ 123e57d534eSdyoung bus_size_t, /*size*/ 124e57d534eSdyoung bus_space_handle_t *); 125e57d534eSdyoung 126e57d534eSdyoung void (*sparc_bus_barrier)( 127e57d534eSdyoung bus_space_tag_t, 128e57d534eSdyoung bus_space_handle_t, 129e57d534eSdyoung bus_size_t, /*offset*/ 130e57d534eSdyoung bus_size_t, /*size*/ 131e57d534eSdyoung int); /*flags*/ 132e57d534eSdyoung 133e57d534eSdyoung paddr_t (*sparc_bus_mmap)( 134e57d534eSdyoung bus_space_tag_t, 135e57d534eSdyoung bus_addr_t, 136e57d534eSdyoung off_t, 137e57d534eSdyoung int, /*prot*/ 138e57d534eSdyoung int); /*flags*/ 139e57d534eSdyoung 140e57d534eSdyoung void *(*sparc_intr_establish)( 141e57d534eSdyoung bus_space_tag_t, 142e57d534eSdyoung int, /*bus-specific intr*/ 143e57d534eSdyoung int, /*device class level, 144e57d534eSdyoung see machine/intr.h*/ 145e57d534eSdyoung int (*)(void *), /*handler*/ 146e57d534eSdyoung void *, /*handler arg*/ 147e57d534eSdyoung void (*)(void)); /*optional fast vector*/ 148e57d534eSdyoung 149e57d534eSdyoung uint8_t (*sparc_read_1)( 150e57d534eSdyoung bus_space_tag_t space, 151e57d534eSdyoung bus_space_handle_t handle, 152e57d534eSdyoung bus_size_t offset); 153e57d534eSdyoung 154e57d534eSdyoung uint16_t (*sparc_read_2)( 155e57d534eSdyoung bus_space_tag_t space, 156e57d534eSdyoung bus_space_handle_t handle, 157e57d534eSdyoung bus_size_t offset); 158e57d534eSdyoung 159e57d534eSdyoung uint32_t (*sparc_read_4)( 160e57d534eSdyoung bus_space_tag_t space, 161e57d534eSdyoung bus_space_handle_t handle, 162e57d534eSdyoung bus_size_t offset); 163e57d534eSdyoung 164e57d534eSdyoung uint64_t (*sparc_read_8)( 165e57d534eSdyoung bus_space_tag_t space, 166e57d534eSdyoung bus_space_handle_t handle, 167e57d534eSdyoung bus_size_t offset); 168e57d534eSdyoung 169e57d534eSdyoung void (*sparc_write_1)( 170e57d534eSdyoung bus_space_tag_t space, 171e57d534eSdyoung bus_space_handle_t handle, 172e57d534eSdyoung bus_size_t offset, 173e57d534eSdyoung uint8_t value); 174e57d534eSdyoung 175e57d534eSdyoung void (*sparc_write_2)( 176e57d534eSdyoung bus_space_tag_t space, 177e57d534eSdyoung bus_space_handle_t handle, 178e57d534eSdyoung bus_size_t offset, 179e57d534eSdyoung uint16_t value); 180e57d534eSdyoung 181e57d534eSdyoung void (*sparc_write_4)( 182e57d534eSdyoung bus_space_tag_t space, 183e57d534eSdyoung bus_space_handle_t handle, 184e57d534eSdyoung bus_size_t offset, 185e57d534eSdyoung uint32_t value); 186e57d534eSdyoung 187e57d534eSdyoung void (*sparc_write_8)( 188e57d534eSdyoung bus_space_tag_t space, 189e57d534eSdyoung bus_space_handle_t handle, 190e57d534eSdyoung bus_size_t offset, 191e57d534eSdyoung uint64_t value); 192e57d534eSdyoung }; 193e57d534eSdyoung 194e57d534eSdyoung /* flags for bus space map functions */ 195e57d534eSdyoung #define BUS_SPACE_MAP_BUS1 0x0100 /* placeholders for bus functions... */ 196e57d534eSdyoung #define BUS_SPACE_MAP_BUS2 0x0200 197e57d534eSdyoung #define BUS_SPACE_MAP_BUS3 0x0400 198e57d534eSdyoung #define BUS_SPACE_MAP_LARGE 0x0800 /* map outside IODEV range */ 199e57d534eSdyoung 200e57d534eSdyoung 201e57d534eSdyoung /* flags for bus_space_barrier() */ 202e57d534eSdyoung #define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */ 203e57d534eSdyoung #define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */ 204e57d534eSdyoung 205e57d534eSdyoung #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 206e57d534eSdyoung 207e57d534eSdyoung /* 208e57d534eSdyoung * Flags used in various bus DMA methods. 209e57d534eSdyoung */ 210e57d534eSdyoung #define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */ 211e57d534eSdyoung #define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */ 212e57d534eSdyoung #define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */ 213e57d534eSdyoung #define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */ 214e57d534eSdyoung #define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */ 215e57d534eSdyoung #define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */ 216e57d534eSdyoung #define BUS_DMA_BUS2 0x020 217e57d534eSdyoung #define BUS_DMA_BUS3 0x040 218e57d534eSdyoung #define BUS_DMA_BUS4 0x080 219e57d534eSdyoung #define BUS_DMA_READ 0x100 /* mapping is device -> memory only */ 220e57d534eSdyoung #define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */ 221e57d534eSdyoung #define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */ 222e57d534eSdyoung 223e57d534eSdyoung /* For devices that have a 24-bit address space */ 224e57d534eSdyoung #define BUS_DMA_24BIT BUS_DMA_BUS1 225e57d534eSdyoung 226e57d534eSdyoung /* Internal flag: current DVMA address is equal to the KVA buffer address */ 227e57d534eSdyoung #define _BUS_DMA_DIRECTMAP BUS_DMA_BUS2 228e57d534eSdyoung 229e57d534eSdyoung /* Forwards needed by prototypes below. */ 230e57d534eSdyoung struct mbuf; 231e57d534eSdyoung struct uio; 232e57d534eSdyoung 233e57d534eSdyoung /* 234e57d534eSdyoung * Operations performed by bus_dmamap_sync(). 235e57d534eSdyoung */ 236e57d534eSdyoung #define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */ 237e57d534eSdyoung #define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */ 238e57d534eSdyoung #define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */ 239e57d534eSdyoung #define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */ 240e57d534eSdyoung 241e57d534eSdyoung typedef struct sparc_bus_dma_tag *bus_dma_tag_t; 242e57d534eSdyoung typedef struct sparc_bus_dmamap *bus_dmamap_t; 243e57d534eSdyoung 244e57d534eSdyoung #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 245e57d534eSdyoung 246e57d534eSdyoung /* 247e57d534eSdyoung * bus_dma_segment_t 248e57d534eSdyoung * 249e57d534eSdyoung * Describes a single contiguous DMA transaction. Values 250e57d534eSdyoung * are suitable for programming into DMA registers. 251e57d534eSdyoung */ 252e57d534eSdyoung struct sparc_bus_dma_segment { 253e57d534eSdyoung bus_addr_t ds_addr; /* DVMA address */ 254e57d534eSdyoung bus_size_t ds_len; /* length of transfer */ 255e57d534eSdyoung bus_size_t _ds_sgsize; /* size of allocated DVMA segment */ 256e57d534eSdyoung void *_ds_mlist; /* page list when dmamem_alloc'ed */ 257e57d534eSdyoung vaddr_t _ds_va; /* VA when dmamem_map'ed */ 258e57d534eSdyoung }; 259e57d534eSdyoung typedef struct sparc_bus_dma_segment bus_dma_segment_t; 260e57d534eSdyoung 261e57d534eSdyoung 262e57d534eSdyoung /* 263e57d534eSdyoung * bus_dma_tag_t 264e57d534eSdyoung * 265e57d534eSdyoung * A machine-dependent opaque type describing the implementation of 266e57d534eSdyoung * DMA for a given bus. 267e57d534eSdyoung */ 268e57d534eSdyoung struct sparc_bus_dma_tag { 269e57d534eSdyoung void *_cookie; /* cookie used in the guts */ 270e57d534eSdyoung 271e57d534eSdyoung /* 272e57d534eSdyoung * DMA mapping methods. 273e57d534eSdyoung */ 274e57d534eSdyoung int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 275e57d534eSdyoung bus_size_t, bus_size_t, int, bus_dmamap_t *); 276e57d534eSdyoung void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 277e57d534eSdyoung int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 278e57d534eSdyoung bus_size_t, struct proc *, int); 279e57d534eSdyoung int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 280e57d534eSdyoung struct mbuf *, int); 281e57d534eSdyoung int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 282e57d534eSdyoung struct uio *, int); 283e57d534eSdyoung int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 284e57d534eSdyoung bus_dma_segment_t *, int, bus_size_t, int); 285e57d534eSdyoung void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 286e57d534eSdyoung void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, 287e57d534eSdyoung bus_addr_t, bus_size_t, int); 288e57d534eSdyoung 289e57d534eSdyoung /* 290e57d534eSdyoung * DMA memory utility functions. 291e57d534eSdyoung */ 292e57d534eSdyoung int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 293e57d534eSdyoung bus_size_t, bus_dma_segment_t *, int, int *, int); 294e57d534eSdyoung void (*_dmamem_free)(bus_dma_tag_t, 295e57d534eSdyoung bus_dma_segment_t *, int); 296e57d534eSdyoung int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 297e57d534eSdyoung int, size_t, void **, int); 298e57d534eSdyoung void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 299e57d534eSdyoung paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 300e57d534eSdyoung int, off_t, int, int); 301e57d534eSdyoung }; 302e57d534eSdyoung 303e57d534eSdyoung /* 304e57d534eSdyoung * bus_dmamap_t 305e57d534eSdyoung * 306e57d534eSdyoung * Describes a DMA mapping. 307e57d534eSdyoung */ 308e57d534eSdyoung struct sparc_bus_dmamap { 309e57d534eSdyoung /* 310e57d534eSdyoung * PRIVATE MEMBERS: not for use by machine-independent code. 311e57d534eSdyoung */ 312e57d534eSdyoung bus_size_t _dm_size; /* largest DMA transfer mappable */ 313e57d534eSdyoung int _dm_segcnt; /* number of segs this map can map */ 314e57d534eSdyoung bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 315e57d534eSdyoung bus_size_t _dm_boundary; /* don't cross this */ 316e57d534eSdyoung int _dm_flags; /* misc. flags */ 317e57d534eSdyoung 318e57d534eSdyoung void *_dm_cookie; /* cookie for bus-specific functions */ 319e57d534eSdyoung 320e57d534eSdyoung u_long _dm_align; /* DVMA alignment; must be a 321e57d534eSdyoung multiple of the page size */ 322e57d534eSdyoung u_long _dm_ex_start; /* constraints on DVMA map */ 323e57d534eSdyoung u_long _dm_ex_end; /* allocations; used by the VME bus 324e57d534eSdyoung driver and by the IOMMU driver 325e57d534eSdyoung when mapping 24-bit devices */ 326e57d534eSdyoung 327e57d534eSdyoung /* 328e57d534eSdyoung * PUBLIC MEMBERS: these are used by machine-independent code. 329e57d534eSdyoung */ 330e57d534eSdyoung bus_size_t dm_maxsegsz; /* largest possible segment */ 331e57d534eSdyoung bus_size_t dm_mapsize; /* size of the mapping */ 332e57d534eSdyoung int dm_nsegs; /* # valid segments in mapping */ 333e57d534eSdyoung bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 334e57d534eSdyoung }; 335e57d534eSdyoung 336e57d534eSdyoung #endif /* _SPARC_BUS_DEFS_H_ */ 337