1 /* $NetBSD: mha.c,v 1.22 2001/04/25 17:53:26 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 1996-1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, Masaru Oki, Takumi Nakamura, Masanobu Saitoh and 9 * Minoura Makoto. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /*- 41 * Copyright (c) 1994 Jarle Greipsland 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 57 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 58 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 59 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 60 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 63 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 64 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #include "opt_ddb.h" 69 70 /* Synchronous data transfers? */ 71 #define SPC_USE_SYNCHRONOUS 0 72 #define SPC_SYNC_REQ_ACK_OFS 8 73 74 /* Default DMA mode? */ 75 #define MHA_DMA_LIMIT_XFER 1 76 #define MHA_DMA_BURST_XFER 1 77 #define MHA_DMA_SHORT_BUS_CYCLE 1 78 79 #define MHA_DMA_DATAIN (0 | (MHA_DMA_LIMIT_XFER << 1) \ 80 | (MHA_DMA_BURST_XFER << 2) \ 81 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 82 #define MHA_DMA_DATAOUT (1 | (MHA_DMA_LIMIT_XFER << 1) \ 83 | (MHA_DMA_BURST_XFER << 2) \ 84 | (MHA_DMA_SHORT_BUS_CYCLE << 3)) 85 86 /* Include debug functions? At the end of this file there are a bunch of 87 * functions that will print out various information regarding queued SCSI 88 * commands, driver state and chip contents. You can call them from the 89 * kernel debugger. If you set SPC_DEBUG to 0 they are not included (the 90 * kernel uses less memory) but you lose the debugging facilities. 91 */ 92 #define SPC_DEBUG 0 93 94 /* End of customizable parameters */ 95 96 /* 97 * MB86601A SCSI Protocol Controller (SPC) routines for MANKAI Mach-2 98 */ 99 100 #include <sys/types.h> 101 #include <sys/param.h> 102 #include <sys/systm.h> 103 #include <sys/kernel.h> 104 #include <sys/errno.h> 105 #include <sys/ioctl.h> 106 #include <sys/device.h> 107 #include <sys/buf.h> 108 #include <sys/proc.h> 109 #include <sys/user.h> 110 #include <sys/queue.h> 111 112 #include <machine/bus.h> 113 114 #include <dev/scsipi/scsi_all.h> 115 #include <dev/scsipi/scsipi_all.h> 116 #include <dev/scsipi/scsi_message.h> 117 #include <dev/scsipi/scsiconf.h> 118 119 #include <x68k/x68k/iodevice.h> 120 #include <x68k/dev/mb86601reg.h> 121 #include <x68k/dev/mhavar.h> 122 #include <x68k/dev/intiovar.h> 123 #include <x68k/dev/scsiromvar.h> 124 125 #if 0 126 #define WAIT {if (sc->sc_pc[2]) {printf("[W_%d", __LINE__); while (sc->sc_pc[2] & 0x40);printf("]");}} 127 #else 128 #define WAIT {while (sc->sc_pc[2] & 0x40);} 129 #endif 130 131 #define SSR (sc->sc_pc[2]) 132 #define SS_IREQUEST 0x80 133 #define SS_BUSY 0x40 134 #define SS_DREG_FULL 0x02 135 136 #define NSR (sc->sc_pc[3]) 137 138 #define SIR (sc->sc_pc[4]) 139 140 #define CMR (sc->sc_pc[5]) 141 #define CMD_SEL_AND_CMD 0x00 142 #define CMD_SELECT 0x09 143 #define CMD_SET_ATN 0x0a 144 #define CMD_RESET_ATN 0x0b 145 #define CMD_RESET_ACK 0x0d 146 #define CMD_SEND_FROM_MPU 0x10 147 #define CMD_SEND_FROM_DMA 0x11 148 #define CMD_RECEIVE_TO_MPU 0x12 149 #define CMD_RECEIVE_TO_DMA 0x13 150 #define CMD_RECEIVE_MSG 0x1a 151 #define CMD_RECEIVE_STS 0x1c 152 #define CMD_SOFT_RESET 0x40 153 #define CMD_SCSI_RESET 0x42 154 #define CMD_SET_UP_REG 0x43 155 156 #define SCR (sc->sc_pc[11]) 157 158 #define TMR (sc->sc_pc[12]) 159 #define TM_SYNC 0x80 160 #define TM_ASYNC 0x00 161 162 #define WAR (sc->sc_pc[15]) 163 #define WA_MCSBUFWIN 0x00 164 #define WA_UPMWIN 0x80 165 #define WA_INITWIN 0xc0 166 167 #define MBR (sc->sc_pc[15]) 168 169 #define ISCSR (sc->sc_ps[2]) 170 171 #define CCR (sc->sc_pcx[0]) 172 #define OIR (sc->sc_pcx[1]) 173 #define AMR (sc->sc_pcx[2]) 174 #define SMR (sc->sc_pcx[3]) 175 #define SRR (sc->sc_pcx[4]) 176 #define STR (sc->sc_pcx[5]) 177 #define RTR (sc->sc_pcx[6]) 178 #define ATR (sc->sc_pcx[7]) 179 #define PER (sc->sc_pcx[8]) 180 #define IER (sc->sc_pcx[9]) 181 #define IE_ALL 0xBF 182 183 #define GLR (sc->sc_pcx[10]) 184 #define DMR (sc->sc_pcx[11]) 185 #define IMR (sc->sc_pcx[12]) 186 187 188 #ifndef DDB 189 #define Debugger() panic("should call debugger here (mha.c)") 190 #endif /* ! DDB */ 191 192 193 #if SPC_DEBUG 194 #define SPC_SHOWACBS 0x01 195 #define SPC_SHOWINTS 0x02 196 #define SPC_SHOWCMDS 0x04 197 #define SPC_SHOWMISC 0x08 198 #define SPC_SHOWTRAC 0x10 199 #define SPC_SHOWSTART 0x20 200 #define SPC_SHOWPHASE 0x40 201 #define SPC_SHOWDMA 0x80 202 #define SPC_SHOWCCMDS 0x100 203 #define SPC_SHOWMSGS 0x200 204 #define SPC_DOBREAK 0x400 205 206 int mha_debug = 207 #if 0 208 0x7FF; 209 #else 210 SPC_SHOWSTART|SPC_SHOWTRAC; 211 #endif 212 213 214 #define SPC_ACBS(str) do {if (mha_debug & SPC_SHOWACBS) printf str;} while (0) 215 #define SPC_MISC(str) do {if (mha_debug & SPC_SHOWMISC) printf str;} while (0) 216 #define SPC_INTS(str) do {if (mha_debug & SPC_SHOWINTS) printf str;} while (0) 217 #define SPC_TRACE(str) do {if (mha_debug & SPC_SHOWTRAC) printf str;} while (0) 218 #define SPC_CMDS(str) do {if (mha_debug & SPC_SHOWCMDS) printf str;} while (0) 219 #define SPC_START(str) do {if (mha_debug & SPC_SHOWSTART) printf str;}while (0) 220 #define SPC_PHASE(str) do {if (mha_debug & SPC_SHOWPHASE) printf str;}while (0) 221 #define SPC_DMA(str) do {if (mha_debug & SPC_SHOWDMA) printf str;}while (0) 222 #define SPC_MSGS(str) do {if (mha_debug & SPC_SHOWMSGS) printf str;}while (0) 223 #define SPC_BREAK() do {if ((mha_debug & SPC_DOBREAK) != 0) Debugger();} while (0) 224 #define SPC_ASSERT(x) do {if (x) {} else {printf("%s at line %d: assertion failed\n", sc->sc_dev.dv_xname, __LINE__); Debugger();}} while (0) 225 #else 226 #define SPC_ACBS(str) 227 #define SPC_MISC(str) 228 #define SPC_INTS(str) 229 #define SPC_TRACE(str) 230 #define SPC_CMDS(str) 231 #define SPC_START(str) 232 #define SPC_PHASE(str) 233 #define SPC_DMA(str) 234 #define SPC_MSGS(str) 235 #define SPC_BREAK() 236 #define SPC_ASSERT(x) 237 #endif 238 239 int mhamatch __P((struct device *, struct cfdata *, void *)); 240 void mhaattach __P((struct device *, struct device *, void *)); 241 void mhaselect __P((struct mha_softc *, 242 u_char, u_char, u_char *, u_char)); 243 void mha_scsi_reset __P((struct mha_softc *)); 244 void mha_reset __P((struct mha_softc *)); 245 void mha_free_acb __P((struct mha_softc *, struct acb *, int)); 246 void mha_sense __P((struct mha_softc *, struct acb *)); 247 void mha_msgin __P((struct mha_softc *)); 248 void mha_msgout __P((struct mha_softc *)); 249 int mha_dataout_pio __P((struct mha_softc *, u_char *, int)); 250 int mha_datain_pio __P((struct mha_softc *, u_char *, int)); 251 int mha_dataout __P((struct mha_softc *, u_char *, int)); 252 int mha_datain __P((struct mha_softc *, u_char *, int)); 253 void mha_abort __P((struct mha_softc *, struct acb *)); 254 void mha_init __P((struct mha_softc *)); 255 void mha_scsi_request __P((struct scsipi_channel *, 256 scsipi_adapter_req_t, void *)); 257 void mha_poll __P((struct mha_softc *, struct acb *)); 258 void mha_sched __P((struct mha_softc *)); 259 void mha_done __P((struct mha_softc *, struct acb *)); 260 int mhaintr __P((void*)); 261 void mha_timeout __P((void *)); 262 void mha_minphys __P((struct buf *)); 263 void mha_dequeue __P((struct mha_softc *, struct acb *)); 264 inline void mha_setsync __P((struct mha_softc *, struct spc_tinfo *)); 265 #if SPC_DEBUG 266 void mha_print_acb __P((struct acb *)); 267 void mha_show_scsi_cmd __P((struct acb *)); 268 void mha_print_active_acb __P((void)); 269 void mha_dump_driver __P((struct mha_softc *)); 270 #endif 271 272 static int mha_dataio_dma __P((int, int, struct mha_softc *, u_char *, int)); 273 274 struct cfattach mha_ca = { 275 sizeof(struct mha_softc), mhamatch, mhaattach 276 }; 277 278 extern struct cfdriver mha_cd; 279 280 281 /* 282 * returns non-zero value if a controller is found. 283 */ 284 int 285 mhamatch(parent, cf, aux) 286 struct device *parent; 287 struct cfdata *cf; 288 void *aux; 289 { 290 struct intio_attach_args *ia = aux; 291 bus_space_tag_t iot = ia->ia_bst; 292 bus_space_handle_t ioh; 293 294 ia->ia_size=0x20; 295 if (ia->ia_addr != 0xea0000) 296 return 0; 297 298 if (intio_map_allocate_region(parent->dv_parent, ia, 299 INTIO_MAP_TESTONLY) < 0) /* FAKE */ 300 return 0; 301 302 if (bus_space_map(iot, ia->ia_addr, 0x20, BUS_SPACE_MAP_SHIFTED, 303 &ioh) < 0) 304 return 0; 305 if (!badaddr ((caddr_t)INTIO_ADDR(ia->ia_addr + 0))) 306 return 0; 307 bus_space_unmap(iot, ioh, 0x20); 308 309 return 1; 310 } 311 312 /* 313 */ 314 315 struct mha_softc *tmpsc; 316 317 void 318 mhaattach(parent, self, aux) 319 struct device *parent, *self; 320 void *aux; 321 { 322 struct mha_softc *sc = (void *)self; 323 struct intio_attach_args *ia = aux; 324 325 tmpsc = sc; /* XXX */ 326 327 printf (": Mankai Mach-2 Fast SCSI Host Adaptor\n"); 328 329 SPC_TRACE(("mhaattach ")); 330 sc->sc_state = SPC_INIT; 331 sc->sc_iobase = INTIO_ADDR(ia->ia_addr + 0x80); /* XXX */ 332 intio_map_allocate_region (parent->dv_parent, ia, INTIO_MAP_ALLOCATE); 333 /* XXX: FAKE */ 334 sc->sc_dmat = ia->ia_dmat; 335 336 sc->sc_pc = (volatile u_char *)sc->sc_iobase; 337 sc->sc_ps = (volatile u_short *)sc->sc_iobase; 338 sc->sc_pcx = &sc->sc_pc[0x10]; 339 340 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 341 342 intio_intr_establish (ia->ia_intr, "mha", mhaintr, sc); 343 344 mha_init(sc); /* Init chip and driver */ 345 346 mha_scsi_reset(sc); /* XXX: some devices need this. */ 347 348 sc->sc_phase = BUSFREE_PHASE; 349 350 /* 351 * Fill in the adapter. 352 */ 353 sc->sc_adapter.adapt_dev = &sc->sc_dev; 354 sc->sc_adapter.adapt_nchannels = 1; 355 sc->sc_adapter.adapt_openings = 7; 356 sc->sc_adapter.adapt_max_periph = 1; 357 sc->sc_adapter.adapt_ioctl = NULL; 358 sc->sc_adapter.adapt_minphys = mha_minphys; 359 sc->sc_adapter.adapt_request = mha_scsi_request; 360 361 sc->sc_channel.chan_adapter = &sc->sc_adapter; 362 sc->sc_channel.chan_bustype = &scsi_bustype; 363 sc->sc_channel.chan_channel = 0; 364 sc->sc_channel.chan_ntargets = 8; 365 sc->sc_channel.chan_nluns = 8; 366 sc->sc_channel.chan_id = sc->sc_id; 367 368 sc->sc_spcinitialized = 0; 369 WAR = WA_INITWIN; 370 #if 1 371 CCR = 0x14; 372 OIR = sc->sc_id; 373 AMR = 0x00; 374 SMR = 0x00; 375 SRR = 0x00; 376 STR = 0x20; 377 RTR = 0x40; 378 ATR = 0x01; 379 PER = 0xc9; 380 #endif 381 IER = IE_ALL; /* $B$9$Y$F$N3d$j9~$_$r5v2D(B */ 382 #if 1 383 GLR = 0x00; 384 DMR = 0x30; 385 IMR = 0x00; 386 #endif 387 WAR = WA_MCSBUFWIN; 388 389 /* drop off */ 390 while (SSR & SS_IREQUEST) 391 { 392 unsigned a = ISCSR; 393 } 394 395 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 396 397 SPC_TRACE(("waiting for intr...")); 398 while (!(SSR & SS_IREQUEST)) 399 delay(10); 400 mhaintr (sc); 401 402 tmpsc = NULL; 403 404 config_found(self, &sc->sc_channel, scsiprint); 405 } 406 407 #if 0 408 void 409 mha_reset(sc) 410 struct mha_softc *sc; 411 { 412 u_short dummy; 413 printf("reset..."); 414 CMR = CMD_SOFT_RESET; 415 asm volatile ("nop"); /* XXX wait (4clk in 20mhz) ??? */ 416 dummy = sc->sc_ps[-1]; 417 dummy = sc->sc_ps[-1]; 418 dummy = sc->sc_ps[-1]; 419 dummy = sc->sc_ps[-1]; 420 asm volatile ("nop"); 421 CMR = CMD_SOFT_RESET; 422 sc->sc_spcinitialized = 0; 423 CMR = CMD_SET_UP_REG; /* setup reg cmd. */ 424 while(!sc->sc_spcinitialized); 425 426 sc->sc_id = IODEVbase->io_sram[0x70] & 0x7; /* XXX */ 427 printf("done.\n"); 428 } 429 #endif 430 431 /* 432 * Pull the SCSI RST line for 500us. 433 */ 434 void 435 mha_scsi_reset(sc) /* FINISH? */ 436 struct mha_softc *sc; 437 { 438 439 CMR = CMD_SCSI_RESET; /* SCSI RESET */ 440 while (!(SSR&SS_IREQUEST)) 441 delay(10); 442 } 443 444 /* 445 * Initialize mha SCSI driver. 446 */ 447 void 448 mha_init(sc) 449 struct mha_softc *sc; 450 { 451 struct acb *acb; 452 int r; 453 454 if (sc->sc_state == SPC_INIT) { 455 /* First time through; initialize. */ 456 TAILQ_INIT(&sc->ready_list); 457 TAILQ_INIT(&sc->nexus_list); 458 TAILQ_INIT(&sc->free_list); 459 sc->sc_nexus = NULL; 460 acb = sc->sc_acb; 461 bzero(acb, sizeof(sc->sc_acb)); 462 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 463 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 464 acb++; 465 } 466 bzero(&sc->sc_tinfo, sizeof(sc->sc_tinfo)); 467 468 r = bus_dmamem_alloc(sc->sc_dmat, MAXBSIZE, 0, 0, 469 sc->sc_dmaseg, 1, &sc->sc_ndmasegs, 470 BUS_DMA_NOWAIT); 471 if (r) 472 panic("mha_init: cannot allocate dma memory"); 473 if (sc->sc_ndmasegs != 1) 474 panic("mha_init: number of segment > 1??"); 475 r = bus_dmamem_map(sc->sc_dmat, sc->sc_dmaseg, sc->sc_ndmasegs, 476 MAXBSIZE, &sc->sc_dmabuf, BUS_DMA_NOWAIT); 477 if (r) 478 panic("mha_init: cannot map dma memory"); 479 r = bus_dmamap_create(sc->sc_dmat, MAXBSIZE, 1, 480 MAXBSIZE, 0, BUS_DMA_NOWAIT, 481 &sc->sc_dmamap); 482 if (r) 483 panic("mha_init: cannot create dmamap structure"); 484 r = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 485 sc->sc_dmabuf, MAXBSIZE, NULL, 486 BUS_DMA_NOWAIT); 487 if (r) 488 panic("mha_init: cannot load dma buffer into dmamap"); 489 sc->sc_p = 0; 490 } else { 491 /* Cancel any active commands. */ 492 sc->sc_flags |= SPC_ABORTING; 493 sc->sc_state = SPC_IDLE; 494 if ((acb = sc->sc_nexus) != NULL) { 495 acb->xs->error = XS_DRIVER_STUFFUP; 496 mha_done(sc, acb); 497 } 498 while ((acb = sc->nexus_list.tqh_first) != NULL) { 499 acb->xs->error = XS_DRIVER_STUFFUP; 500 mha_done(sc, acb); 501 } 502 } 503 504 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 505 for (r = 0; r < 8; r++) { 506 struct spc_tinfo *ti = &sc->sc_tinfo[r]; 507 508 ti->flags = 0; 509 #if SPC_USE_SYNCHRONOUS 510 ti->flags |= T_SYNCMODE; 511 ti->period = sc->sc_minsync; 512 ti->offset = SPC_SYNC_REQ_ACK_OFS; 513 #else 514 ti->period = ti->offset = 0; 515 #endif 516 ti->width = 0; 517 } 518 519 sc->sc_state = SPC_IDLE; 520 } 521 522 void 523 mha_free_acb(sc, acb, flags) 524 struct mha_softc *sc; 525 struct acb *acb; 526 int flags; 527 { 528 int s; 529 530 s = splbio(); 531 532 acb->flags = 0; 533 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 534 535 /* 536 * If there were none, wake anybody waiting for one to come free, 537 * starting with queued entries. 538 */ 539 if (acb->chain.tqe_next == 0) 540 wakeup(&sc->free_list); 541 542 splx(s); 543 } 544 545 546 /* 547 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 548 */ 549 550 /* 551 * Expected sequence: 552 * 1) Command inserted into ready list 553 * 2) Command selected for execution 554 * 3) Command won arbitration and has selected target device 555 * 4) Send message out (identify message, eventually also sync.negotiations) 556 * 5) Send command 557 * 5a) Receive disconnect message, disconnect. 558 * 5b) Reselected by target 559 * 5c) Receive identify message from target. 560 * 6) Send or receive data 561 * 7) Receive status 562 * 8) Receive message (command complete etc.) 563 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 564 * Repeat 2-8 (no disconnects please...) 565 */ 566 567 /* 568 * Start a selection. This is used by mha_sched() to select an idle target, 569 * and by mha_done() to immediately reselect a target to get sense information. 570 */ 571 void 572 mhaselect(sc, target, lun, cmd, clen) 573 struct mha_softc *sc; 574 u_char target, lun; 575 u_char *cmd; 576 u_char clen; 577 { 578 struct spc_tinfo *ti = &sc->sc_tinfo[target]; 579 int i; 580 int s; 581 582 s = splbio(); /* XXX */ 583 584 SPC_TRACE(("[mhaselect(t%d,l%d,cmd:%x)] ", target, lun, *(u_char *)cmd)); 585 586 /* CDB $B$r(B SPC $B$N(B MCS REG $B$K%;%C%H$9$k(B */ 587 /* Now the command into the FIFO */ 588 WAIT; 589 #if 1 590 SPC_MISC(("[cmd:")); 591 for (i = 0; i < clen; i++) 592 { 593 unsigned c = cmd[i]; 594 if (i == 1) 595 c |= lun << 5; 596 SPC_MISC((" %02x", c)); 597 sc->sc_pcx[i] = c; 598 } 599 SPC_MISC(("], target=%d\n", target)); 600 #else 601 bcopy(cmd, sc->sc_pcx, clen); 602 #endif 603 if (NSR & 0x80) 604 panic("scsistart: already selected..."); 605 sc->sc_phase = COMMAND_PHASE; 606 607 /* new state ASP_SELECTING */ 608 sc->sc_state = SPC_SELECTING; 609 610 SIR = target; 611 #if 0 612 CMR = CMD_SELECT; 613 #else 614 CMR = CMD_SEL_AND_CMD; /* select & cmd */ 615 #endif 616 splx(s); 617 } 618 619 #if 0 620 int 621 mha_reselect(sc, message) 622 struct mha_softc *sc; 623 u_char message; 624 { 625 u_char selid, target, lun; 626 struct acb *acb; 627 struct scsipi_periph *periph; 628 struct spc_tinfo *ti; 629 630 /* 631 * The SCSI chip made a snapshot of the data bus while the reselection 632 * was being negotiated. This enables us to determine which target did 633 * the reselect. 634 */ 635 selid = sc->sc_selid & ~(1 << sc->sc_id); 636 if (selid & (selid - 1)) { 637 printf("%s: reselect with invalid selid %02x; sending DEVICE RESET\n", 638 sc->sc_dev.dv_xname, selid); 639 SPC_BREAK(); 640 goto reset; 641 } 642 643 /* 644 * Search wait queue for disconnected cmd 645 * The list should be short, so I haven't bothered with 646 * any more sophisticated structures than a simple 647 * singly linked list. 648 */ 649 target = ffs(selid) - 1; 650 lun = message & 0x07; 651 for (acb = sc->nexus_list.tqh_first; acb != NULL; 652 acb = acb->chain.tqe_next) { 653 periph = acb->xs->xs_periph; 654 if (periph->periph_target == target && 655 periph->periph_lun == lun) 656 break; 657 } 658 if (acb == NULL) { 659 printf("%s: reselect from target %d lun %d with no nexus; sending ABORT\n", 660 sc->sc_dev.dv_xname, target, lun); 661 SPC_BREAK(); 662 goto abort; 663 } 664 665 /* Make this nexus active again. */ 666 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 667 sc->sc_state = SPC_HASNEXUS; 668 sc->sc_nexus = acb; 669 ti = &sc->sc_tinfo[target]; 670 ti->lubusy |= (1 << lun); 671 mha_setsync(sc, ti); 672 673 if (acb->flags & ACB_RESET) 674 mha_sched_msgout(sc, SEND_DEV_RESET); 675 else if (acb->flags & ACB_ABORTED) 676 mha_sched_msgout(sc, SEND_ABORT); 677 678 /* Do an implicit RESTORE POINTERS. */ 679 sc->sc_dp = acb->daddr; 680 sc->sc_dleft = acb->dleft; 681 sc->sc_cp = (u_char *)&acb->cmd; 682 sc->sc_cleft = acb->clen; 683 684 return (0); 685 686 reset: 687 mha_sched_msgout(sc, SEND_DEV_RESET); 688 return (1); 689 690 abort: 691 mha_sched_msgout(sc, SEND_ABORT); 692 return (1); 693 } 694 #endif 695 /* 696 * Start a SCSI-command 697 * This function is called by the higher level SCSI-driver to queue/run 698 * SCSI-commands. 699 */ 700 void 701 mha_scsi_request(chan, req, arg) 702 struct scsipi_channel *chan; 703 scsipi_adapter_req_t req; 704 void *arg; 705 { 706 struct scsipi_xfer *xs; 707 struct scsipi_periph *periph; 708 struct mha_softc *sc = (void *)chan->chan_adapter->adapt_dev; 709 struct acb *acb; 710 int s, flags; 711 712 switch (req) { 713 case ADAPTER_REQ_RUN_XFER: 714 xs = arg; 715 periph = xs->xs_periph; 716 717 SPC_TRACE(("[mha_scsi_cmd] ")); 718 SPC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 719 periph->periph_target)); 720 721 flags = xs->xs_control; 722 723 /* Get a mha command block */ 724 s = splbio(); 725 acb = sc->free_list.tqh_first; 726 if (acb) { 727 TAILQ_REMOVE(&sc->free_list, acb, chain); 728 ACB_SETQ(acb, ACB_QNONE); 729 } 730 731 if (acb == NULL) { 732 xs->error = XS_RESOURCE_SHORTAGE; 733 scsipi_done(xs); 734 splx(s); 735 return; 736 } 737 splx(s); 738 739 /* Initialize acb */ 740 acb->xs = xs; 741 bcopy(xs->cmd, &acb->cmd, xs->cmdlen); 742 acb->clen = xs->cmdlen; 743 acb->daddr = xs->data; 744 acb->dleft = xs->datalen; 745 acb->stat = 0; 746 747 s = splbio(); 748 ACB_SETQ(acb, ACB_QREADY); 749 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 750 #if 1 751 callout_reset(&acb->xs->xs_callout, 752 ((u_int64_t)xs->timeout * (u_int64_t)hz) / 1000, 753 mha_timeout, acb); 754 #endif 755 756 /* 757 * $B%-%e!<$N=hM}Cf$G$J$1$l$P!"%9%1%8%e!<%j%s%03+;O$9$k(B 758 */ 759 if (sc->sc_state == SPC_IDLE) 760 mha_sched(sc); 761 762 splx(s); 763 764 if (flags & XS_CTL_POLL) { 765 /* Not allowed to use interrupts, use polling instead */ 766 mha_poll(sc, acb); 767 } 768 769 SPC_MISC(("SUCCESSFULLY_QUEUED")); 770 return; 771 772 case ADAPTER_REQ_GROW_RESOURCES: 773 /* XXX Not supported. */ 774 return; 775 776 case ADAPTER_REQ_SET_XFER_MODE: 777 /* XXX Not supported. */ 778 return; 779 } 780 } 781 782 /* 783 * Adjust transfer size in buffer structure 784 */ 785 void 786 mha_minphys(bp) 787 struct buf *bp; 788 { 789 790 SPC_TRACE(("mha_minphys ")); 791 minphys(bp); 792 } 793 794 /* 795 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 796 */ 797 void 798 mha_poll(sc, acb) 799 struct mha_softc *sc; 800 struct acb *acb; 801 { 802 struct scsipi_xfer *xs = acb->xs; 803 int count = xs->timeout * 100; 804 int s = splbio(); 805 806 SPC_TRACE(("[mha_poll] ")); 807 808 while (count) { 809 /* 810 * If we had interrupts enabled, would we 811 * have got an interrupt? 812 */ 813 if (SSR & SS_IREQUEST) 814 mhaintr(sc); 815 if ((xs->xs_status & XS_STS_DONE) != 0) 816 break; 817 DELAY(10); 818 #if 1 819 if (sc->sc_state == SPC_IDLE) { 820 SPC_TRACE(("[mha_poll: rescheduling] ")); 821 mha_sched(sc); 822 } 823 #endif 824 count--; 825 } 826 827 if (count == 0) { 828 SPC_MISC(("mha_poll: timeout")); 829 mha_timeout((caddr_t)acb); 830 } 831 splx(s); 832 scsipi_done(xs); 833 } 834 835 /* 836 * LOW LEVEL SCSI UTILITIES 837 */ 838 839 /* 840 * Set synchronous transfer offset and period. 841 */ 842 inline void 843 mha_setsync(sc, ti) 844 struct mha_softc *sc; 845 struct spc_tinfo *ti; 846 { 847 } 848 849 850 /* 851 * Schedule a SCSI operation. This has now been pulled out of the interrupt 852 * handler so that we may call it from mha_scsi_cmd and mha_done. This may 853 * save us an unecessary interrupt just to get things going. Should only be 854 * called when state == SPC_IDLE and at bio pl. 855 */ 856 void 857 mha_sched(sc) 858 register struct mha_softc *sc; 859 { 860 struct scsipi_periph *periph; 861 struct acb *acb; 862 int t; 863 864 SPC_TRACE(("[mha_sched] ")); 865 if (sc->sc_state != SPC_IDLE) 866 panic("mha_sched: not IDLE (state=%d)", sc->sc_state); 867 868 if (sc->sc_flags & SPC_ABORTING) 869 return; 870 871 /* 872 * Find first acb in ready queue that is for a target/lunit 873 * combinations that is not busy. 874 */ 875 for (acb = sc->ready_list.tqh_first; acb ; acb = acb->chain.tqe_next) { 876 struct spc_tinfo *ti; 877 periph = acb->xs->xs_periph; 878 t = periph->periph_target; 879 ti = &sc->sc_tinfo[t]; 880 if (!(ti->lubusy & (1 << periph->periph_lun))) { 881 if ((acb->flags & ACB_QBITS) != ACB_QREADY) 882 panic("mha: busy entry on ready list"); 883 TAILQ_REMOVE(&sc->ready_list, acb, chain); 884 ACB_SETQ(acb, ACB_QNONE); 885 sc->sc_nexus = acb; 886 sc->sc_flags = 0; 887 sc->sc_prevphase = INVALID_PHASE; 888 sc->sc_dp = acb->daddr; 889 sc->sc_dleft = acb->dleft; 890 ti->lubusy |= (1<<periph->periph_lun); 891 mhaselect(sc, t, periph->periph_lun, 892 (u_char *)&acb->cmd, acb->clen); 893 break; 894 } else { 895 SPC_MISC(("%d:%d busy\n", 896 periph->periph_target, 897 periph->periph_lun)); 898 } 899 } 900 } 901 902 /* 903 * POST PROCESSING OF SCSI_CMD (usually current) 904 */ 905 void 906 mha_done(sc, acb) 907 struct mha_softc *sc; 908 struct acb *acb; 909 { 910 struct scsipi_xfer *xs = acb->xs; 911 struct scsipi_periph *periph = xs->xs_periph; 912 struct spc_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 913 914 SPC_TRACE(("[mha_done(error:%x)] ", xs->error)); 915 916 #if 1 917 callout_stop(&acb->xs->xs_callout); 918 #endif 919 920 /* 921 * Now, if we've come here with no error code, i.e. we've kept the 922 * initial XS_NOERROR, and the status code signals that we should 923 * check sense, we'll need to set up a request sense cmd block and 924 * push the command back into the ready queue *before* any other 925 * commands for this target/lunit, else we lose the sense info. 926 * We don't support chk sense conditions for the request sense cmd. 927 */ 928 if (xs->error == XS_NOERROR) { 929 if ((acb->flags & ACB_ABORTED) != 0) { 930 xs->error = XS_TIMEOUT; 931 } else if (acb->flags & ACB_CHKSENSE) { 932 xs->error = XS_SENSE; 933 } else { 934 xs->status = acb->stat & ST_MASK; 935 switch (xs->status) { 936 case SCSI_CHECK: 937 xs->resid = acb->dleft; 938 /* FALLTHOUGH */ 939 case SCSI_BUSY: 940 xs->error = XS_BUSY; 941 break; 942 case SCSI_OK: 943 xs->resid = acb->dleft; 944 break; 945 default: 946 xs->error = XS_DRIVER_STUFFUP; 947 #if SPC_DEBUG 948 printf("%s: mha_done: bad stat 0x%x\n", 949 sc->sc_dev.dv_xname, acb->stat); 950 #endif 951 break; 952 } 953 } 954 } 955 956 #if SPC_DEBUG 957 if ((mha_debug & SPC_SHOWMISC) != 0) { 958 if (xs->resid != 0) 959 printf("resid=%d ", xs->resid); 960 if (xs->error == XS_SENSE) 961 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 962 else 963 printf("error=%d\n", xs->error); 964 } 965 #endif 966 967 /* 968 * Remove the ACB from whatever queue it's on. 969 */ 970 switch (acb->flags & ACB_QBITS) { 971 case ACB_QNONE: 972 if (acb != sc->sc_nexus) { 973 panic("%s: floating acb", sc->sc_dev.dv_xname); 974 } 975 sc->sc_nexus = NULL; 976 sc->sc_state = SPC_IDLE; 977 ti->lubusy &= ~(1<<periph->periph_lun); 978 mha_sched(sc); 979 break; 980 case ACB_QREADY: 981 TAILQ_REMOVE(&sc->ready_list, acb, chain); 982 break; 983 case ACB_QNEXUS: 984 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 985 ti->lubusy &= ~(1<<periph->periph_lun); 986 break; 987 case ACB_QFREE: 988 panic("%s: dequeue: busy acb on free list", 989 sc->sc_dev.dv_xname); 990 break; 991 default: 992 panic("%s: dequeue: unknown queue %d", 993 sc->sc_dev.dv_xname, acb->flags & ACB_QBITS); 994 } 995 996 /* Put it on the free list, and clear flags. */ 997 #if 0 998 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 999 acb->flags = ACB_QFREE; 1000 #else 1001 mha_free_acb(sc, acb, xs->xs_control); 1002 #endif 1003 1004 ti->cmds++; 1005 scsipi_done(xs); 1006 } 1007 1008 void 1009 mha_dequeue(sc, acb) 1010 struct mha_softc *sc; 1011 struct acb *acb; 1012 { 1013 1014 if (acb->flags & ACB_QNEXUS) { 1015 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 1016 } else { 1017 TAILQ_REMOVE(&sc->ready_list, acb, chain); 1018 } 1019 } 1020 1021 /* 1022 * INTERRUPT/PROTOCOL ENGINE 1023 */ 1024 1025 /* 1026 * Schedule an outgoing message by prioritizing it, and asserting 1027 * attention on the bus. We can only do this when we are the initiator 1028 * else there will be an illegal command interrupt. 1029 */ 1030 #define mha_sched_msgout(m) \ 1031 do { \ 1032 SPC_MISC(("mha_sched_msgout %d ", m)); \ 1033 CMR = CMD_SET_ATN; \ 1034 sc->sc_msgpriq |= (m); \ 1035 } while (0) 1036 1037 #define IS1BYTEMSG(m) (((m) != 0x01 && (m) < 0x20) || (m) >= 0x80) 1038 #define IS2BYTEMSG(m) (((m) & 0xf0) == 0x20) 1039 #define ISEXTMSG(m) ((m) == 0x01) 1040 1041 /* 1042 * Precondition: 1043 * The SCSI bus is already in the MSGI phase and there is a message byte 1044 * on the bus, along with an asserted REQ signal. 1045 */ 1046 void 1047 mha_msgin(sc) 1048 register struct mha_softc *sc; 1049 { 1050 register int v; 1051 int n; 1052 1053 SPC_TRACE(("[mha_msgin(curmsglen:%d)] ", sc->sc_imlen)); 1054 1055 /* 1056 * Prepare for a new message. A message should (according 1057 * to the SCSI standard) be transmitted in one single 1058 * MESSAGE_IN_PHASE. If we have been in some other phase, 1059 * then this is a new message. 1060 */ 1061 if (sc->sc_prevphase != MESSAGE_IN_PHASE) { 1062 sc->sc_flags &= ~SPC_DROP_MSGI; 1063 sc->sc_imlen = 0; 1064 } 1065 1066 WAIT; 1067 1068 v = MBR; /* modified byte */ 1069 v = sc->sc_pcx[0]; 1070 1071 sc->sc_imess[sc->sc_imlen] = v; 1072 1073 /* 1074 * If we're going to reject the message, don't bother storing 1075 * the incoming bytes. But still, we need to ACK them. 1076 */ 1077 1078 if ((sc->sc_flags & SPC_DROP_MSGI)) { 1079 CMR = CMD_SET_ATN; 1080 /* ESPCMD(sc, ESPCMD_MSGOK);*/ 1081 printf("<dropping msg byte %x>", 1082 sc->sc_imess[sc->sc_imlen]); 1083 return; 1084 } 1085 1086 if (sc->sc_imlen >= SPC_MAX_MSG_LEN) { 1087 mha_sched_msgout(SEND_REJECT); 1088 sc->sc_flags |= SPC_DROP_MSGI; 1089 } else { 1090 sc->sc_imlen++; 1091 /* 1092 * This testing is suboptimal, but most 1093 * messages will be of the one byte variety, so 1094 * it should not effect performance 1095 * significantly. 1096 */ 1097 if (sc->sc_imlen == 1 && IS1BYTEMSG(sc->sc_imess[0])) 1098 goto gotit; 1099 if (sc->sc_imlen == 2 && IS2BYTEMSG(sc->sc_imess[0])) 1100 goto gotit; 1101 if (sc->sc_imlen >= 3 && ISEXTMSG(sc->sc_imess[0]) && 1102 sc->sc_imlen == sc->sc_imess[1] + 2) 1103 goto gotit; 1104 } 1105 #if 0 1106 /* Ack what we have so far */ 1107 ESPCMD(sc, ESPCMD_MSGOK); 1108 #endif 1109 return; 1110 1111 gotit: 1112 SPC_MSGS(("gotmsg(%x)", sc->sc_imess[0])); 1113 /* 1114 * Now we should have a complete message (1 byte, 2 byte 1115 * and moderately long extended messages). We only handle 1116 * extended messages which total length is shorter than 1117 * SPC_MAX_MSG_LEN. Longer messages will be amputated. 1118 */ 1119 if (sc->sc_state == SPC_HASNEXUS) { 1120 struct acb *acb = sc->sc_nexus; 1121 struct spc_tinfo *ti = 1122 &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1123 1124 switch (sc->sc_imess[0]) { 1125 case MSG_CMDCOMPLETE: 1126 SPC_MSGS(("cmdcomplete ")); 1127 if (sc->sc_dleft < 0) { 1128 struct scsipi_periph *periph = acb->xs->xs_periph; 1129 printf("mha: %d extra bytes from %d:%d\n", 1130 -sc->sc_dleft, 1131 periph->periph_target, 1132 periph->periph_lun); 1133 sc->sc_dleft = 0; 1134 } 1135 acb->xs->resid = acb->dleft = sc->sc_dleft; 1136 sc->sc_flags |= SPC_BUSFREE_OK; 1137 break; 1138 1139 case MSG_MESSAGE_REJECT: 1140 #if SPC_DEBUG 1141 if (mha_debug & SPC_SHOWMSGS) 1142 printf("%s: our msg rejected by target\n", 1143 sc->sc_dev.dv_xname); 1144 #endif 1145 #if 1 /* XXX - must remember last message */ 1146 scsipi_printaddr(acb->xs->xs_periph); 1147 printf("MSG_MESSAGE_REJECT>>"); 1148 #endif 1149 if (sc->sc_flags & SPC_SYNCHNEGO) { 1150 ti->period = ti->offset = 0; 1151 sc->sc_flags &= ~SPC_SYNCHNEGO; 1152 ti->flags &= ~T_NEGOTIATE; 1153 } 1154 /* Not all targets understand INITIATOR_DETECTED_ERR */ 1155 if (sc->sc_msgout == SEND_INIT_DET_ERR) 1156 mha_sched_msgout(SEND_ABORT); 1157 break; 1158 case MSG_NOOP: 1159 SPC_MSGS(("noop ")); 1160 break; 1161 case MSG_DISCONNECT: 1162 SPC_MSGS(("disconnect ")); 1163 ti->dconns++; 1164 sc->sc_flags |= SPC_DISCON; 1165 sc->sc_flags |= SPC_BUSFREE_OK; 1166 if ((acb->xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) == 0) 1167 break; 1168 /*FALLTHROUGH*/ 1169 case MSG_SAVEDATAPOINTER: 1170 SPC_MSGS(("save datapointer ")); 1171 acb->dleft = sc->sc_dleft; 1172 acb->daddr = sc->sc_dp; 1173 break; 1174 case MSG_RESTOREPOINTERS: 1175 SPC_MSGS(("restore datapointer ")); 1176 if (!acb) { 1177 mha_sched_msgout(SEND_ABORT); 1178 printf("%s: no DATAPOINTERs to restore\n", 1179 sc->sc_dev.dv_xname); 1180 break; 1181 } 1182 sc->sc_dp = acb->daddr; 1183 sc->sc_dleft = acb->dleft; 1184 break; 1185 case MSG_PARITY_ERROR: 1186 printf("%s:target%d: MSG_PARITY_ERROR\n", 1187 sc->sc_dev.dv_xname, 1188 acb->xs->xs_periph->periph_target); 1189 break; 1190 case MSG_EXTENDED: 1191 SPC_MSGS(("extended(%x) ", sc->sc_imess[2])); 1192 switch (sc->sc_imess[2]) { 1193 case MSG_EXT_SDTR: 1194 SPC_MSGS(("SDTR period %d, offset %d ", 1195 sc->sc_imess[3], sc->sc_imess[4])); 1196 ti->period = sc->sc_imess[3]; 1197 ti->offset = sc->sc_imess[4]; 1198 if (sc->sc_minsync == 0) { 1199 /* We won't do synch */ 1200 ti->offset = 0; 1201 mha_sched_msgout(SEND_SDTR); 1202 } else if (ti->offset == 0) { 1203 printf("%s:%d: async\n", "mha", 1204 acb->xs->xs_periph->periph_target); 1205 ti->offset = 0; 1206 sc->sc_flags &= ~SPC_SYNCHNEGO; 1207 } else if (ti->period > 124) { 1208 printf("%s:%d: async\n", "mha", 1209 acb->xs->xs_periph->periph_target); 1210 ti->offset = 0; 1211 mha_sched_msgout(SEND_SDTR); 1212 } else { 1213 int r = 250/ti->period; 1214 int s = (100*250)/ti->period - 100*r; 1215 int p; 1216 #if 0 1217 p = mha_stp2cpb(sc, ti->period); 1218 ti->period = mha_cpb2stp(sc, p); 1219 #endif 1220 1221 #if SPC_DEBUG 1222 scsipi_printaddr(acb->xs->xs_periph); 1223 #endif 1224 if ((sc->sc_flags&SPC_SYNCHNEGO) == 0) { 1225 /* Target initiated negotiation */ 1226 if (ti->flags & T_SYNCMODE) { 1227 ti->flags &= ~T_SYNCMODE; 1228 #if SPC_DEBUG 1229 printf("renegotiated "); 1230 #endif 1231 } 1232 TMR=TM_ASYNC; 1233 /* Clamp to our maxima */ 1234 if (ti->period < sc->sc_minsync) 1235 ti->period = sc->sc_minsync; 1236 if (ti->offset > 15) 1237 ti->offset = 15; 1238 mha_sched_msgout(SEND_SDTR); 1239 } else { 1240 /* we are sync */ 1241 sc->sc_flags &= ~SPC_SYNCHNEGO; 1242 TMR = TM_SYNC; 1243 ti->flags |= T_SYNCMODE; 1244 } 1245 #if SPC_DEBUG 1246 printf("max sync rate %d.%02dMb/s\n", 1247 r, s); 1248 #endif 1249 } 1250 ti->flags &= ~T_NEGOTIATE; 1251 break; 1252 default: /* Extended messages we don't handle */ 1253 CMR = CMD_SET_ATN; /* XXX? */ 1254 break; 1255 } 1256 break; 1257 default: 1258 SPC_MSGS(("ident ")); 1259 /* thanks for that ident... */ 1260 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1261 SPC_MISC(("unknown ")); 1262 printf("%s: unimplemented message: %d\n", sc->sc_dev.dv_xname, sc->sc_imess[0]); 1263 CMR = CMD_SET_ATN; /* XXX? */ 1264 } 1265 break; 1266 } 1267 } else if (sc->sc_state == SPC_RESELECTED) { 1268 struct scsipi_periph *periph = NULL; 1269 struct acb *acb; 1270 struct spc_tinfo *ti; 1271 u_char lunit; 1272 1273 if (MSG_ISIDENTIFY(sc->sc_imess[0])) { /* Identify? */ 1274 SPC_MISC(("searching ")); 1275 /* 1276 * Search wait queue for disconnected cmd 1277 * The list should be short, so I haven't bothered with 1278 * any more sophisticated structures than a simple 1279 * singly linked list. 1280 */ 1281 lunit = sc->sc_imess[0] & 0x07; 1282 for (acb = sc->nexus_list.tqh_first; acb; 1283 acb = acb->chain.tqe_next) { 1284 periph = acb->xs->xs_periph; 1285 if (periph->periph_lun == lunit && 1286 sc->sc_selid == (1<<periph->periph_target)) { 1287 TAILQ_REMOVE(&sc->nexus_list, acb, 1288 chain); 1289 ACB_SETQ(acb, ACB_QNONE); 1290 break; 1291 } 1292 } 1293 1294 if (!acb) { /* Invalid reselection! */ 1295 mha_sched_msgout(SEND_ABORT); 1296 printf("mha: invalid reselect (idbit=0x%2x)\n", 1297 sc->sc_selid); 1298 } else { /* Reestablish nexus */ 1299 /* 1300 * Setup driver data structures and 1301 * do an implicit RESTORE POINTERS 1302 */ 1303 ti = &sc->sc_tinfo[periph->periph_target]; 1304 sc->sc_nexus = acb; 1305 sc->sc_dp = acb->daddr; 1306 sc->sc_dleft = acb->dleft; 1307 sc->sc_tinfo[periph->periph_target].lubusy 1308 |= (1<<periph->periph_lun); 1309 if (ti->flags & T_SYNCMODE) { 1310 TMR = TM_SYNC; /* XXX */ 1311 } else { 1312 TMR = TM_ASYNC; 1313 } 1314 SPC_MISC(("... found acb")); 1315 sc->sc_state = SPC_HASNEXUS; 1316 } 1317 } else { 1318 printf("%s: bogus reselect (no IDENTIFY) %0x2x\n", 1319 sc->sc_dev.dv_xname, sc->sc_selid); 1320 mha_sched_msgout(SEND_DEV_RESET); 1321 } 1322 } else { /* Neither SPC_HASNEXUS nor SPC_RESELECTED! */ 1323 printf("%s: unexpected message in; will send DEV_RESET\n", 1324 sc->sc_dev.dv_xname); 1325 mha_sched_msgout(SEND_DEV_RESET); 1326 } 1327 1328 /* Ack last message byte */ 1329 #if 0 1330 ESPCMD(sc, ESPCMD_MSGOK); 1331 #endif 1332 1333 /* Done, reset message pointer. */ 1334 sc->sc_flags &= ~SPC_DROP_MSGI; 1335 sc->sc_imlen = 0; 1336 } 1337 1338 /* 1339 * Send the highest priority, scheduled message. 1340 */ 1341 void 1342 mha_msgout(sc) 1343 register struct mha_softc *sc; 1344 { 1345 struct spc_tinfo *ti; 1346 int n; 1347 1348 SPC_TRACE(("mha_msgout ")); 1349 1350 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 1351 if (sc->sc_omp == sc->sc_omess) { 1352 /* 1353 * This is a retransmission. 1354 * 1355 * We get here if the target stayed in MESSAGE OUT 1356 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1357 * that all of the previously transmitted messages must 1358 * be sent again, in the same order. Therefore, we 1359 * requeue all the previously transmitted messages, and 1360 * start again from the top. Our simple priority 1361 * scheme keeps the messages in the right order. 1362 */ 1363 SPC_MISC(("retransmitting ")); 1364 sc->sc_msgpriq |= sc->sc_msgoutq; 1365 /* 1366 * Set ATN. If we're just sending a trivial 1-byte 1367 * message, we'll clear ATN later on anyway. 1368 */ 1369 CMR = CMD_SET_ATN; /* XXX? */ 1370 } else { 1371 /* This is a continuation of the previous message. */ 1372 n = sc->sc_omp - sc->sc_omess; 1373 goto nextbyte; 1374 } 1375 } 1376 1377 /* No messages transmitted so far. */ 1378 sc->sc_msgoutq = 0; 1379 sc->sc_lastmsg = 0; 1380 1381 nextmsg: 1382 /* Pick up highest priority message. */ 1383 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1384 sc->sc_msgpriq &= ~sc->sc_currmsg; 1385 sc->sc_msgoutq |= sc->sc_currmsg; 1386 1387 /* Build the outgoing message data. */ 1388 switch (sc->sc_currmsg) { 1389 case SEND_IDENTIFY: 1390 SPC_ASSERT(sc->sc_nexus != NULL); 1391 sc->sc_omess[0] = 1392 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1); 1393 n = 1; 1394 break; 1395 1396 #if SPC_USE_SYNCHRONOUS 1397 case SEND_SDTR: 1398 SPC_ASSERT(sc->sc_nexus != NULL); 1399 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1400 sc->sc_omess[4] = MSG_EXTENDED; 1401 sc->sc_omess[3] = 3; 1402 sc->sc_omess[2] = MSG_EXT_SDTR; 1403 sc->sc_omess[1] = ti->period >> 2; 1404 sc->sc_omess[0] = ti->offset; 1405 n = 5; 1406 break; 1407 #endif 1408 1409 #if SPC_USE_WIDE 1410 case SEND_WDTR: 1411 SPC_ASSERT(sc->sc_nexus != NULL); 1412 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1413 sc->sc_omess[3] = MSG_EXTENDED; 1414 sc->sc_omess[2] = 2; 1415 sc->sc_omess[1] = MSG_EXT_WDTR; 1416 sc->sc_omess[0] = ti->width; 1417 n = 4; 1418 break; 1419 #endif 1420 1421 case SEND_DEV_RESET: 1422 sc->sc_flags |= SPC_ABORTING; 1423 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1424 n = 1; 1425 break; 1426 1427 case SEND_REJECT: 1428 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1429 n = 1; 1430 break; 1431 1432 case SEND_PARITY_ERROR: 1433 sc->sc_omess[0] = MSG_PARITY_ERROR; 1434 n = 1; 1435 break; 1436 1437 case SEND_INIT_DET_ERR: 1438 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1439 n = 1; 1440 break; 1441 1442 case SEND_ABORT: 1443 sc->sc_flags |= SPC_ABORTING; 1444 sc->sc_omess[0] = MSG_ABORT; 1445 n = 1; 1446 break; 1447 1448 default: 1449 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1450 sc->sc_dev.dv_xname); 1451 SPC_BREAK(); 1452 sc->sc_omess[0] = MSG_NOOP; 1453 n = 1; 1454 break; 1455 } 1456 sc->sc_omp = &sc->sc_omess[n]; 1457 1458 nextbyte: 1459 /* Send message bytes. */ 1460 /* send TRANSFER command. */ 1461 sc->sc_ps[3] = 1; 1462 sc->sc_ps[4] = n >> 8; 1463 sc->sc_pc[10] = n; 1464 sc->sc_ps[-1] = 0x000F; /* burst */ 1465 asm volatile ("nop"); 1466 CMR = CMD_SEND_FROM_DMA; /* send from DMA */ 1467 for (;;) { 1468 if ((SSR & SS_BUSY) != 0) 1469 break; 1470 if (SSR & SS_IREQUEST) 1471 goto out; 1472 } 1473 for (;;) { 1474 #if 0 1475 for (;;) { 1476 if ((PSNS & PSNS_REQ) != 0) 1477 break; 1478 /* Wait for REQINIT. XXX Need timeout. */ 1479 } 1480 #endif 1481 if (SSR & SS_IREQUEST) { 1482 /* 1483 * Target left MESSAGE OUT, possibly to reject 1484 * our message. 1485 * 1486 * If this is the last message being sent, then we 1487 * deassert ATN, since either the target is going to 1488 * ignore this message, or it's going to ask for a 1489 * retransmission via MESSAGE PARITY ERROR (in which 1490 * case we reassert ATN anyway). 1491 */ 1492 #if 0 1493 if (sc->sc_msgpriq == 0) 1494 CMR = CMD_RESET_ATN; 1495 #endif 1496 goto out; 1497 } 1498 1499 #if 0 1500 /* Clear ATN before last byte if this is the last message. */ 1501 if (n == 1 && sc->sc_msgpriq == 0) 1502 CMR = CMD_RESET_ATN; 1503 #endif 1504 1505 while ((SSR & SS_DREG_FULL) != 0) 1506 ; 1507 /* Send message byte. */ 1508 sc->sc_pc[0] = *--sc->sc_omp; 1509 --n; 1510 /* Keep track of the last message we've sent any bytes of. */ 1511 sc->sc_lastmsg = sc->sc_currmsg; 1512 1513 if (n == 0) 1514 break; 1515 } 1516 1517 /* We get here only if the entire message has been transmitted. */ 1518 if (sc->sc_msgpriq != 0) { 1519 /* There are more outgoing messages. */ 1520 goto nextmsg; 1521 } 1522 1523 /* 1524 * The last message has been transmitted. We need to remember the last 1525 * message transmitted (in case the target switches to MESSAGE IN phase 1526 * and sends a MESSAGE REJECT), and the list of messages transmitted 1527 * this time around (in case the target stays in MESSAGE OUT phase to 1528 * request a retransmit). 1529 */ 1530 1531 out: 1532 /* Disable REQ/ACK protocol. */ 1533 } 1534 1535 1536 /*************************************************************** 1537 * 1538 * datain/dataout 1539 * 1540 */ 1541 1542 int 1543 mha_datain_pio(sc, p, n) 1544 register struct mha_softc *sc; 1545 u_char *p; 1546 int n; 1547 { 1548 u_short d; 1549 int a; 1550 int total_n = n; 1551 1552 SPC_TRACE(("[mha_datain_pio(%x,%d)", p, n)); 1553 1554 WAIT; 1555 sc->sc_ps[3] = 1; 1556 sc->sc_ps[4] = n >> 8; 1557 sc->sc_pc[10] = n; 1558 /* $BHa$7$-%=%U%HE>Aw(B */ 1559 CMR = CMD_RECEIVE_TO_MPU; 1560 for (;;) { 1561 a = SSR; 1562 if (a & 0x04) { 1563 d = sc->sc_ps[0]; 1564 *p++ = d >> 8; 1565 if (--n > 0) { 1566 *p++ = d; 1567 --n; 1568 } 1569 a = SSR; 1570 } 1571 if (a & 0x40) 1572 continue; 1573 if (a & 0x80) 1574 break; 1575 } 1576 SPC_TRACE(("...%d resd]", n)); 1577 return total_n - n; 1578 } 1579 1580 int 1581 mha_dataout_pio(sc, p, n) 1582 register struct mha_softc *sc; 1583 u_char *p; 1584 int n; 1585 { 1586 u_short d; 1587 int a; 1588 int total_n = n; 1589 1590 SPC_TRACE(("[mha_dataout_pio(%x,%d)", p, n)); 1591 1592 WAIT; 1593 sc->sc_ps[3] = 1; 1594 sc->sc_ps[4] = n >> 8; 1595 sc->sc_pc[10] = n; 1596 /* $BHa$7$-%=%U%HE>Aw(B */ 1597 CMR = CMD_SEND_FROM_MPU; 1598 for (;;) { 1599 a = SSR; 1600 if (a & 0x04) { 1601 d = *p++ << 8; 1602 if (--n > 0) { 1603 d |= *p++; 1604 --n; 1605 } 1606 sc->sc_ps[0] = d; 1607 a = SSR; 1608 } 1609 if (a & 0x40) 1610 continue; 1611 if (a & 0x80) 1612 break; 1613 } 1614 SPC_TRACE(("...%d resd]", n)); 1615 return total_n - n; 1616 } 1617 1618 static int 1619 mha_dataio_dma(dw, cw, sc, p, n) 1620 int dw; /* DMA word */ 1621 int cw; /* CMR word */ 1622 register struct mha_softc *sc; 1623 u_char *p; 1624 int n; 1625 { 1626 char *paddr, *vaddr; 1627 1628 if (n > MAXBSIZE) 1629 panic("transfer size exceeds MAXBSIZE"); 1630 if (sc->sc_dmasize > 0) 1631 panic("DMA request while another DMA transfer is in pregress"); 1632 1633 if (cw == CMD_SEND_FROM_DMA) { 1634 memcpy(sc->sc_dmabuf, p, n); 1635 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREWRITE); 1636 } else { 1637 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 0, n, BUS_DMASYNC_PREREAD); 1638 } 1639 sc->sc_p = p; 1640 sc->sc_dmasize = n; 1641 1642 paddr = (char *)sc->sc_dmaseg[0].ds_addr; 1643 #if MHA_DMA_SHORT_BUS_CYCLE == 1 1644 if ((*(int *)&IODEVbase->io_sram[0xac]) & (1 << ((paddr_t)paddr >> 19))) 1645 dw &= ~(1 << 3); 1646 #endif 1647 dma_cachectl((caddr_t) sc->sc_dmabuf, n); 1648 #if 0 1649 printf("(%x,%x)->(%x,%x)\n", p, n, paddr, n); 1650 PCIA(); /* XXX */ 1651 #endif 1652 sc->sc_pc[0x80 + (((long)paddr >> 16) & 0xFF)] = 0; 1653 sc->sc_pc[0x180 + (((long)paddr >> 8) & 0xFF)] = 0; 1654 sc->sc_pc[0x280 + (((long)paddr >> 0) & 0xFF)] = 0; 1655 WAIT; 1656 sc->sc_ps[3] = 1; 1657 sc->sc_ps[4] = n >> 8; 1658 sc->sc_pc[10] = n; 1659 /* DMA $BE>Aw@)8f$O0J2<$NDL$j!#(B 1660 3 ... short bus cycle 1661 2 ... MAXIMUM XFER. 1662 1 ... BURST XFER. 1663 0 ... R/W */ 1664 sc->sc_ps[-1] = dw; /* burst */ 1665 asm volatile ("nop"); 1666 CMR = cw; /* receive to DMA */ 1667 return n; 1668 } 1669 int 1670 mha_dataout(sc, p, n) 1671 register struct mha_softc *sc; 1672 u_char *p; 1673 int n; 1674 { 1675 register struct acb *acb = sc->sc_nexus; 1676 1677 if (n == 0) 1678 return n; 1679 1680 if (n & 1) 1681 return mha_dataout_pio(sc, p, n); 1682 return mha_dataio_dma(MHA_DMA_DATAOUT, CMD_SEND_FROM_DMA, sc, p, n); 1683 } 1684 1685 int 1686 mha_datain(sc, p, n) 1687 register struct mha_softc *sc; 1688 u_char *p; 1689 int n; 1690 { 1691 int ts; 1692 register struct acb *acb = sc->sc_nexus; 1693 char *paddr, *vaddr; 1694 1695 if (n == 0) 1696 return n; 1697 if (acb->cmd.opcode == REQUEST_SENSE || (n & 1)) 1698 return mha_datain_pio(sc, p, n); 1699 return mha_dataio_dma(MHA_DMA_DATAIN, CMD_RECEIVE_TO_DMA, sc, p, n); 1700 } 1701 1702 1703 /* 1704 * Catch an interrupt from the adaptor 1705 */ 1706 /* 1707 * This is the workhorse routine of the driver. 1708 * Deficiencies (for now): 1709 * 1) always uses programmed I/O 1710 */ 1711 int 1712 mhaintr(arg) 1713 void *arg; 1714 { 1715 struct mha_softc *sc = arg; 1716 #if 0 1717 u_char ints; 1718 #endif 1719 struct acb *acb; 1720 struct scsipi_periph *periph; 1721 struct spc_tinfo *ti; 1722 u_char ph; 1723 u_short r; 1724 int n; 1725 1726 #if 1 /* XXX called during attach? */ 1727 if (tmpsc != NULL) { 1728 SPC_MISC(("[%x %x]\n", mha_cd.cd_devs, sc)); 1729 sc = tmpsc; 1730 } else { 1731 #endif 1732 1733 #if 1 /* XXX */ 1734 } 1735 #endif 1736 1737 #if 0 1738 /* 1739 * $B3d$j9~$_6X;_$K$9$k(B 1740 */ 1741 SCTL &= ~SCTL_INTR_ENAB; 1742 #endif 1743 1744 SPC_TRACE(("[mhaintr]")); 1745 1746 loop: 1747 /* 1748 * $BA4E>Aw$,40A4$K=*N;$9$k$^$G%k!<%W$9$k(B 1749 */ 1750 /* 1751 * First check for abnormal conditions, such as reset. 1752 */ 1753 #if 0 1754 #if 1 /* XXX? */ 1755 while (((ints = SSR) & SS_IREQUEST) == 0) 1756 delay(1); 1757 SPC_MISC(("ints = 0x%x ", ints)); 1758 #else /* usually? */ 1759 ints = SSR; 1760 #endif 1761 #endif 1762 while (SSR & SS_IREQUEST) { 1763 acb = sc->sc_nexus; 1764 r = ISCSR; 1765 SPC_MISC(("[r=0x%x]", r)); 1766 switch (r >> 8) { 1767 default: 1768 printf("[addr=%x\n" 1769 "result=0x%x\n" 1770 "cmd=0x%x\n" 1771 "ph=0x%x(ought to be %d)]\n", 1772 &ISCSR, 1773 r, 1774 acb->xs->cmd->opcode, 1775 SCR, sc->sc_phase); 1776 panic("unexpected result."); 1777 case 0x82: /* selection timeout */ 1778 SPC_MISC(("selection timeout ")); 1779 sc->sc_phase = BUSFREE_PHASE; 1780 SPC_ASSERT(sc->sc_nexus != NULL); 1781 acb = sc->sc_nexus; 1782 delay(250); 1783 acb->xs->error = XS_SELTIMEOUT; 1784 mha_done(sc, acb); 1785 continue; /* XXX ??? msaitoh */ 1786 case 0x60: /* command completed */ 1787 sc->sc_spcinitialized++; 1788 if (sc->sc_phase == BUSFREE_PHASE) 1789 continue; 1790 ph = SCR; 1791 if (ph & PSNS_ACK) { 1792 int s; 1793 /* $B$U$D!<$N%3%^%s%I$,=*N;$7$?$i$7$$(B */ 1794 SPC_MISC(("0x60)phase = %x(ought to be %x)\n", 1795 ph & PHASE_MASK, sc->sc_phase)); 1796 #if 0 1797 /* switch (sc->sc_phase) {*/ 1798 #else 1799 switch (ph & PHASE_MASK) { 1800 #endif 1801 case STATUS_PHASE: 1802 if (sc->sc_state != SPC_HASNEXUS) 1803 printf("stsin: !SPC_HASNEXUS->(%d)\n", 1804 sc->sc_state); 1805 SPC_ASSERT(sc->sc_nexus != NULL); 1806 acb = sc->sc_nexus; 1807 WAIT; 1808 s = MBR; 1809 SPC_ASSERT(s == 1); 1810 acb->stat = sc->sc_pcx[0]; /* XXX */ 1811 SPC_MISC(("stat=0x%02x ", acb->stat)); 1812 sc->sc_prevphase = STATUS_PHASE; 1813 break; 1814 case MESSAGE_IN_PHASE: 1815 mha_msgin(sc); 1816 sc->sc_prevphase = MESSAGE_IN_PHASE; 1817 /* thru */ 1818 case DATA_IN_PHASE: 1819 if (sc->sc_dmasize == 0) 1820 break; 1821 bus_dmamap_sync(sc->sc_dmat, 1822 sc->sc_dmamap, 1823 0, sc->sc_dmasize, 1824 BUS_DMASYNC_POSTREAD); 1825 memcpy(sc->sc_p, sc->sc_dmabuf, 1826 sc->sc_dmasize); 1827 sc->sc_dmasize = 0; 1828 break; 1829 case DATA_OUT_PHASE: 1830 if (sc->sc_dmasize == 0) 1831 break; 1832 bus_dmamap_sync(sc->sc_dmat, 1833 sc->sc_dmamap, 1834 0, sc->sc_dmasize, 1835 BUS_DMASYNC_POSTWRITE); 1836 sc->sc_dmasize = 0; 1837 break; 1838 } 1839 WAIT; 1840 CMR = CMD_RESET_ACK; /* reset ack */ 1841 /*mha_done(sc, acb); XXX */ 1842 continue; 1843 } else if (NSR & 0x80) { /* nexus */ 1844 #if 1 1845 if (sc->sc_state == SPC_SELECTING) /* XXX msaitoh */ 1846 sc->sc_state = SPC_HASNEXUS; 1847 /* $B%U%'!<%:$N7h$aBG$A$r$9$k(B 1848 $B30$l$?$i!"(Binitial-phase error(0x54) $B$,(B 1849 $BJV$C$F$/$k$s$GCm0U$7$?$^$(!#(B 1850 $B$G$b$J$<$+(B 0x65 $B$,JV$C$F$-$?$j$7$F$M!<$+(B? */ 1851 WAIT; 1852 if (SSR & SS_IREQUEST) 1853 continue; 1854 switch (sc->sc_phase) { 1855 default: 1856 panic("$B8+CN$i$L(B phase $B$,Mh$A$^$C$?$@$h(B"); 1857 case MESSAGE_IN_PHASE: 1858 /* $B2?$b$7$J$$(B */ 1859 continue; 1860 case STATUS_PHASE: 1861 sc->sc_phase = MESSAGE_IN_PHASE; 1862 CMR = CMD_RECEIVE_MSG; /* receive msg */ 1863 continue; 1864 case DATA_IN_PHASE: 1865 sc->sc_prevphase = DATA_IN_PHASE; 1866 if (sc->sc_dleft == 0) { 1867 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1868 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1869 sc->sc_phase = STATUS_PHASE; 1870 CMR = CMD_RECEIVE_STS; /* receive sts */ 1871 continue; 1872 } 1873 n = mha_datain(sc, sc->sc_dp, 1874 sc->sc_dleft); 1875 sc->sc_dp += n; 1876 sc->sc_dleft -= n; 1877 continue; 1878 case DATA_OUT_PHASE: 1879 sc->sc_prevphase = DATA_OUT_PHASE; 1880 if (sc->sc_dleft == 0) { 1881 /* $BE>Aw%G!<%?$O$b$&$J$$$N$G(B 1882 $B%9%F!<%?%9%U%'!<%:$r4|BT$7$h$&(B */ 1883 sc->sc_phase = STATUS_PHASE; 1884 CMR = CMD_RECEIVE_STS; /* receive sts */ 1885 continue; 1886 } 1887 /* data phase $B$NB3$-$r$d$m$&(B */ 1888 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1889 sc->sc_dp += n; 1890 sc->sc_dleft -= n; 1891 continue; 1892 case COMMAND_PHASE: 1893 /* $B:G=i$O(B CMD PHASE $B$H$$$&$3$H$i$7$$(B */ 1894 if (acb->dleft) { 1895 /* $B%G!<%?E>Aw$,$"$j$&$k>l9g(B */ 1896 if (acb->xs->xs_control & XS_CTL_DATA_IN) { 1897 sc->sc_phase = DATA_IN_PHASE; 1898 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1899 sc->sc_dp += n; 1900 sc->sc_dleft -= n; 1901 } 1902 else if (acb->xs->xs_control & XS_CTL_DATA_OUT) { 1903 sc->sc_phase = DATA_OUT_PHASE; 1904 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1905 sc->sc_dp += n; 1906 sc->sc_dleft -= n; 1907 } 1908 continue; 1909 } 1910 else { 1911 /* $B%G!<%?E>Aw$O$J$$$i$7$$(B?! */ 1912 WAIT; 1913 sc->sc_phase = STATUS_PHASE; 1914 CMR = CMD_RECEIVE_STS; /* receive sts */ 1915 continue; 1916 } 1917 } 1918 #endif 1919 } 1920 continue; 1921 case 0x31: /* disconnected in xfer progress. */ 1922 SPC_MISC(("[0x31]")); 1923 case 0x70: /* disconnected. */ 1924 SPC_ASSERT(sc->sc_flags & SPC_BUSFREE_OK); 1925 sc->sc_phase = BUSFREE_PHASE; 1926 sc->sc_state = SPC_IDLE; 1927 #if 1 1928 acb = sc->sc_nexus; 1929 SPC_ASSERT(sc->sc_nexus != NULL); 1930 acb->xs->error = XS_NOERROR; 1931 mha_done(sc, acb); 1932 #else 1933 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1934 mha_sched(sc); 1935 #endif 1936 continue; 1937 case 0x32: /* phase error in xfer progress. */ 1938 SPC_MISC(("[0x32]")); 1939 #if 0 1940 case 0x65: /* invalid command. 1941 $B$J$<$3$s$J$b$N$,=P$k$N$+(B 1942 $B26$K$OA4$/M}2r$G$-$J$$(B */ 1943 #if 1 1944 SPC_MISC(("[0x%04x]", r)); 1945 #endif 1946 #endif 1947 case 0x54: /* initial-phase error. */ 1948 SPC_MISC(("[0x54, ns=%x, ph=%x(ought to be %x)]", 1949 NSR, 1950 SCR, sc->sc_phase)); 1951 /* thru */ 1952 case 0x71: /* assert req */ 1953 WAIT; 1954 if (SSR & 0x40) { 1955 printf("SPC sts=%2x, r=%04x, ns=%x, ph=%x\n", 1956 SSR, r, NSR, SCR); 1957 WAIT; 1958 } 1959 ph = SCR; 1960 if (sc->sc_state == SPC_SELECTING) { /* XXX msaitoh */ 1961 sc->sc_state = SPC_HASNEXUS; 1962 } 1963 if (ph & 0x80) { 1964 switch (ph & PHASE_MASK) { 1965 default: 1966 printf("phase = %x\n", ph); 1967 panic("assert req: the phase I don't know!"); 1968 case DATA_IN_PHASE: 1969 sc->sc_prevphase = DATA_IN_PHASE; 1970 SPC_MISC(("DATAIN(%d)...", sc->sc_dleft)); 1971 n = mha_datain(sc, sc->sc_dp, sc->sc_dleft); 1972 sc->sc_dp += n; 1973 sc->sc_dleft -= n; 1974 SPC_MISC(("done\n")); 1975 continue; 1976 case DATA_OUT_PHASE: 1977 sc->sc_prevphase = DATA_OUT_PHASE; 1978 SPC_MISC(("DATAOUT\n")); 1979 n = mha_dataout(sc, sc->sc_dp, sc->sc_dleft); 1980 sc->sc_dp += n; 1981 sc->sc_dleft -= n; 1982 continue; 1983 case STATUS_PHASE: 1984 sc->sc_phase = STATUS_PHASE; 1985 SPC_MISC(("[RECV_STS]")); 1986 WAIT; 1987 CMR = CMD_RECEIVE_STS; /* receive sts */ 1988 continue; 1989 case MESSAGE_IN_PHASE: 1990 sc->sc_phase = MESSAGE_IN_PHASE; 1991 WAIT; 1992 CMR = CMD_RECEIVE_MSG; 1993 continue; 1994 } 1995 } 1996 continue; 1997 } 1998 } 1999 } 2000 2001 void 2002 mha_abort(sc, acb) 2003 struct mha_softc *sc; 2004 struct acb *acb; 2005 { 2006 acb->flags |= ACB_ABORTED; 2007 2008 if (acb == sc->sc_nexus) { 2009 /* 2010 * If we're still selecting, the message will be scheduled 2011 * after selection is complete. 2012 */ 2013 if (sc->sc_state == SPC_HASNEXUS) { 2014 sc->sc_flags |= SPC_ABORTING; 2015 mha_sched_msgout(SEND_ABORT); 2016 } 2017 } else { 2018 if (sc->sc_state == SPC_IDLE) 2019 mha_sched(sc); 2020 } 2021 } 2022 2023 void 2024 mha_timeout(arg) 2025 void *arg; 2026 { 2027 int s = splbio(); 2028 struct acb *acb = (struct acb *)arg; 2029 struct scsipi_xfer *xs = acb->xs; 2030 struct scsipi_periph *periph = xs->xs_periph; 2031 struct mha_softc *sc = 2032 (void*)periph->periph_channel->chan_adapter->adapt_dev; 2033 2034 scsipi_printaddr(periph); 2035 again: 2036 printf("%s: timed out [acb %p (flags 0x%x, dleft %x, stat %x)], " 2037 "<state %d, nexus %p, phase(c %x, p %x), resid %x, msg(q %x,o %x) >", 2038 sc->sc_dev.dv_xname, 2039 acb, acb->flags, acb->dleft, acb->stat, 2040 sc->sc_state, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 2041 sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout 2042 ); 2043 printf("[%04x %02x]\n", sc->sc_ps[1], SCR); 2044 panic("timeout, ouch!"); 2045 2046 if (acb->flags & ACB_ABORTED) { 2047 /* abort timed out */ 2048 printf(" AGAIN\n"); 2049 #if 0 2050 mha_init(sc, 1); /* XXX 1?*/ 2051 #endif 2052 } else { 2053 /* abort the operation that has timed out */ 2054 printf("\n"); 2055 xs->error = XS_TIMEOUT; 2056 mha_abort(sc, acb); 2057 } 2058 2059 splx(s); 2060 } 2061 2062 #if SPC_DEBUG 2063 /* 2064 * The following functions are mostly used for debugging purposes, either 2065 * directly called from the driver or from the kernel debugger. 2066 */ 2067 2068 void 2069 mha_show_scsi_cmd(acb) 2070 struct acb *acb; 2071 { 2072 u_char *b = (u_char *)&acb->cmd; 2073 struct scsipi_periph *periph = acb->xs->xs_periph; 2074 int i; 2075 2076 scsipi_printaddr(periph); 2077 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2078 for (i = 0; i < acb->clen; i++) { 2079 if (i) 2080 printf(","); 2081 printf("%x", b[i]); 2082 } 2083 printf("\n"); 2084 } else 2085 printf("RESET\n"); 2086 } 2087 2088 void 2089 mha_print_acb(acb) 2090 struct acb *acb; 2091 { 2092 2093 printf("acb@%x xs=%x flags=%x", acb, acb->xs, acb->flags); 2094 printf(" dp=%x dleft=%d stat=%x\n", 2095 (long)acb->daddr, acb->dleft, acb->stat); 2096 mha_show_scsi_cmd(acb); 2097 } 2098 2099 void 2100 mha_print_active_acb() 2101 { 2102 struct acb *acb; 2103 struct mha_softc *sc = mha_cd.cd_devs[0]; /* XXX */ 2104 2105 printf("ready list:\n"); 2106 for (acb = sc->ready_list.tqh_first; acb != NULL; 2107 acb = acb->chain.tqe_next) 2108 mha_print_acb(acb); 2109 printf("nexus:\n"); 2110 if (sc->sc_nexus != NULL) 2111 mha_print_acb(sc->sc_nexus); 2112 printf("nexus list:\n"); 2113 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2114 acb = acb->chain.tqe_next) 2115 mha_print_acb(acb); 2116 } 2117 2118 void 2119 mha_dump_driver(sc) 2120 struct mha_softc *sc; 2121 { 2122 struct spc_tinfo *ti; 2123 int i; 2124 2125 printf("nexus=%x prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2126 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x currmsg=%x\n", 2127 sc->sc_state, sc->sc_imess[0], 2128 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2129 for (i = 0; i < 7; i++) { 2130 ti = &sc->sc_tinfo[i]; 2131 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2132 i, ti->cmds, ti->dconns, ti->touts); 2133 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2134 } 2135 } 2136 #endif 2137