xref: /netbsd/sys/dev/ic/advlib.h (revision 2cb48d6c)
1 /*      $NetBSD: advlib.h,v 1.5 1998/10/28 20:39:46 dante Exp $        */
2 
3 /*
4  * Definitions for low level routines and data structures
5  * for the Advanced Systems Inc. SCSI controllers chips.
6  *
7  * Copyright (c) 1998 The NetBSD Foundation, Inc.
8  * All rights reserved.
9  *
10  * Author: Baldassare Dante Profeta <dante@mclink.it>
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer.
17  * 2. Redistributions in binary form must reproduce the above copyright
18  *    notice, this list of conditions and the following disclaimer in the
19  *    documentation and/or other materials provided with the distribution.
20  * 3. All advertising materials mentioning features or use of this software
21  *    must display the following acknowledgement:
22  *        This product includes software developed by the NetBSD
23  *        Foundation, Inc. and its contributors.
24  * 4. Neither the name of The NetBSD Foundation nor the names of its
25  *    contributors may be used to endorse or promote products derived
26  *    from this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38  * POSSIBILITY OF SUCH DAMAGE.
39  */
40 /*
41  * Ported from:
42  */
43 /*
44  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
45  *
46  * Copyright (c) 1995-1996 Advanced System Products, Inc.
47  * All Rights Reserved.
48  *
49  * Redistribution and use in source and binary forms, with or without
50  * modification, are permitted provided that redistributions of source
51  * code retain the above copyright notice and this comment without
52  * modification.
53  */
54 
55 #ifndef	_ADVANSYS_NARROW_LIBRARY_H_
56 #define	_ADVANSYS_NARROW_LIBRARY_H_
57 
58 #include <dev/ic/adv.h>
59 
60 /******************************************************************************/
61 
62 #define ADV_VERSION	"3.1E"		/* AdvanSys Driver Version */
63 
64 #define ASC_LIB_VERSION_MAJOR  1
65 #define ASC_LIB_VERSION_MINOR  22
66 #define ASC_LIB_SERIAL_NUMBER  113
67 
68 
69 #define ASC_NOERROR	1
70 #define ASC_BUSY	0
71 #define ASC_ERROR	-1
72 
73 
74 #if BYTE_ORDER == BIG_ENDIAN
75 #define LO_BYTE(x)	(*((u_int8_t *)(&(x))+1))
76 #define HI_BYTE(x)	(*((u_int8_t *)&(x)))
77 #define LO_WORD(x)	(*((u_int16_t *)(&(x))+1))
78 #define HI_WORD(x)	(*((u_int16_t *)&(x)))
79 #else
80 #define HI_BYTE(x)	(*((u_int8_t *)(&(x))+1))
81 #define LO_BYTE(x)	(*((u_int8_t *)&(x)))
82 #define HI_WORD(x)	(*((u_int16_t *)(&(x))+1))
83 #define LO_WORD(x)	(*((u_int16_t *)&(x)))
84 #endif
85 
86 #define MAKEWORD(lo, hi)	((u_int16_t) (((u_int16_t) (lo)) | \
87 				((u_int16_t) (hi) << 8)))
88 
89 #define MAKELONG(lo, hi)	((u_int32_t) (((u_int32_t) (lo)) | \
90 				((u_int32_t) (hi) << 16)))
91 
92 #define SWAPWORDS(dWord)	((u_int32_t) ((dWord) >> 16) | ((dWord) << 16))
93 #define SWAPBYTES(word)		((u_int16_t) ((word) >> 8) | ((word) << 8))
94 #define	BIGTOLITTLE(dWord)	(u_int32_t)(SWAPBYTES(SWAPWORDS(dWord) >> 16 ) << 16) | \
95 				SWAPBYTES(SWAPWORDS(dWord) & 0xFFFF)
96 #define LITTLETOBIG(dWord)	BIGTOLITTLE(dWord)
97 
98 
99 #define ASC_PCI_ID2BUS(id)	((id) & 0xFF)
100 #define ASC_PCI_ID2DEV(id)	(((id) >> 11) & 0x1F)
101 #define ASC_PCI_ID2FUNC(id)	(((id) >> 8) & 0x7)
102 #define ASC_PCI_MKID(bus, dev, func)	((((dev) & 0x1F) << 11) | \
103 				(((func) & 0x7) << 8) | ((bus) & 0xFF))
104 #define ASC_PCI_REVISION_3150	0x02
105 #define ASC_PCI_REVISION_3050	0x03
106 
107 
108 #define ASC_MAX_SG_QUEUE	7
109 #define ASC_SG_LIST_PER_Q 	ASC_MAX_SG_QUEUE
110 #define ASC_MAX_SG_LIST		(1 + ((ASC_SG_LIST_PER_Q) * \
111 				(ASC_MAX_SG_QUEUE)))		/* SG_ALL */
112 
113 
114 #define ASC_IS_ISA		0x0001
115 #define ASC_IS_ISAPNP		0x0081
116 #define ASC_IS_EISA		0x0002
117 #define ASC_IS_PCI		0x0004
118 #define ASC_IS_PCI_ULTRA	0x0104
119 #define ASC_IS_PCMCIA		0x0008
120 #define ASC_IS_MCA		0x0020
121 #define ASC_IS_VL		0x0040
122 
123 
124 #define ASC_ISA_PNP_PORT_ADDR	0x279
125 #define ASC_ISA_PNP_PORT_WRITE	(ASC_ISA_PNP_PORT_ADDR+0x800)
126 
127 #define ASC_IS_WIDESCSI_16	0x0100
128 #define ASC_IS_WIDESCSI_32	0x0200
129 #define ASC_IS_BIG_ENDIAN	0x8000
130 
131 
132 #define ASC_CHIP_MIN_VER_VL		0x01
133 #define ASC_CHIP_MAX_VER_VL		0x07
134 #define ASC_CHIP_MIN_VER_PCI		0x09
135 #define ASC_CHIP_MAX_VER_PCI		0x0F
136 #define ASC_CHIP_VER_PCI_BIT		0x08
137 #define ASC_CHIP_MIN_VER_ISA		0x11
138 #define ASC_CHIP_MIN_VER_ISA_PNP	0x21
139 #define ASC_CHIP_MAX_VER_ISA		0x27
140 #define ASC_CHIP_VER_ISA_BIT		0x30
141 #define ASC_CHIP_VER_ISAPNP_BIT		0x20
142 #define ASC_CHIP_VER_ASYN_BUG		0x21
143 #define ASC_CHIP_VER_PCI		0x08
144 #define ASC_CHIP_VER_PCI_ULTRA_3150	(ASC_CHIP_VER_PCI | 0x02)
145 #define ASC_CHIP_VER_PCI_ULTRA_3050	(ASC_CHIP_VER_PCI | 0x03)
146 #define ASC_CHIP_MIN_VER_EISA		0x41
147 #define ASC_CHIP_MAX_VER_EISA		0x47
148 #define ASC_CHIP_VER_EISA_BIT		0x40
149 #define ASC_CHIP_LATEST_VER_EISA	((ASC_CHIP_MIN_VER_EISA - 1) + 3)
150 
151 
152 #define ASC_MAX_VL_DMA_ADDR	0x07FFFFFFL
153 #define ASC_MAX_VL_DMA_COUNT	0x07FFFFFFL
154 #define ASC_MAX_PCI_DMA_ADDR	0xFFFFFFFFL
155 #define ASC_MAX_PCI_DMA_COUNT	0xFFFFFFFFL
156 #define ASC_MAX_ISA_DMA_ADDR	0x00FFFFFFL
157 #define ASC_MAX_ISA_DMA_COUNT	0x00FFFFFFL
158 #define ASC_MAX_EISA_DMA_ADDR	0x07FFFFFFL
159 #define ASC_MAX_EISA_DMA_COUNT	0x07FFFFFFL
160 
161 
162 #define ASC_SCSI_ID_BITS	3
163 #define ASC_SCSI_TIX_TYPE	u_int8_t
164 
165 #define ASC_ALL_DEVICE_BIT_SET	0xFF
166 
167 #ifdef ASC_WIDESCSI_16
168 #undef  ASC_SCSI_ID_BITS
169 #define ASC_SCSI_ID_BITS	4
170 #define ASC_ALL_DEVICE_BIT_SET	0xFFFF
171 #endif
172 
173 #ifdef ASC_WIDESCSI_32
174 #undef  ASC_SCSI_ID_BITS
175 #define ASC_SCSI_ID_BITS	5
176 #define ASC_ALL_DEVICE_BIT_SET	0xFFFFFFFFL
177 #endif
178 
179 #if ASC_SCSI_ID_BITS == 3
180 #define ASC_SCSI_BIT_ID_TYPE	u_int8_t
181 #define ASC_MAX_TID		7
182 #define ASC_MAX_LUN		7
183 #define ASC_SCSI_WIDTH_BIT_SET	0xFF
184 #elif ASC_SCSI_ID_BITS == 4
185 #define ASC_SCSI_BIT_ID_TYPE	u_int16_t
186 #define ASC_MAX_TID		15
187 #define ASC_MAX_LUN		7
188 #define ASC_SCSI_WIDTH_BIT_SET	0xFFFF
189 #elif ASC_SCSI_ID_BITS == 5
190 #define ASC_SCSI_BIT_ID_TYPE	u_int32_t
191 #define ASC_MAX_TID		31
192 #define ASC_MAX_LUN		7
193 #define ASC_SCSI_WIDTH_BIT_SET	0xFFFFFFFF
194 #else
195 #error  ASC_SCSI_ID_BITS definition is wrong
196 #endif
197 
198 
199 #define ASC_MAX_SENSE_LEN	32
200 #define ASC_MIN_SENSE_LEN	14
201 #define ASC_MAX_CDB_LEN		12
202 
203 #define ASC_SCSI_RESET_HOLD_TIME_US  60
204 
205 
206 #define SCSICMD_TestUnitReady		0x00
207 #define SCSICMD_Rewind			0x01
208 #define SCSICMD_Rezero			0x01
209 #define SCSICMD_RequestSense		0x03
210 #define SCSICMD_Format			0x04
211 #define SCSICMD_FormatUnit		0x04
212 #define SCSICMD_Read6			0x08
213 #define SCSICMD_Write6			0x0A
214 #define SCSICMD_Seek6			0x0B
215 #define SCSICMD_Inquiry			0x12
216 #define SCSICMD_Verify6			0x13
217 #define SCSICMD_ModeSelect6		0x15
218 #define SCSICMD_ModeSense6		0x1A
219 #define SCSICMD_StartStopUnit		0x1B
220 #define SCSICMD_LoadUnloadTape		0x1B
221 #define SCSICMD_ReadCapacity		0x25
222 #define SCSICMD_Read10			0x28
223 #define SCSICMD_Write10			0x2A
224 #define SCSICMD_Seek10			0x2B
225 #define SCSICMD_Erase10			0x2C
226 #define SCSICMD_WriteAndVerify10	0x2E
227 #define SCSICMD_Verify10		0x2F
228 #define SCSICMD_WriteBuffer		0x3B
229 #define SCSICMD_ReadBuffer		0x3C
230 #define SCSICMD_ReadLong		0x3E
231 #define SCSICMD_WriteLong		0x3F
232 #define SCSICMD_ReadTOC			0x43
233 #define SCSICMD_ReadHeader		0x44
234 #define SCSICMD_ModeSelect10		0x55
235 #define SCSICMD_ModeSense10		0x5A
236 
237 
238 #define SCSI_TYPE_DASD		0x00
239 #define SCSI_TYPE_SASD		0x01
240 #define SCSI_TYPE_PRN		0x02
241 #define SCSI_TYPE_PROC		0x03
242 #define SCSI_TYPE_WORM		0x04
243 #define SCSI_TYPE_CDROM		0x05
244 #define SCSI_TYPE_SCANNER	0x06
245 #define SCSI_TYPE_OPTMEM	0x07
246 #define SCSI_TYPE_MED_CHG	0x08
247 #define SCSI_TYPE_COMM		0x09
248 #define SCSI_TYPE_UNKNOWN	0x1F
249 #define SCSI_TYPE_NO_DVC	0xFF
250 
251 
252 #define ASC_SCSIDIR_NOCHK	0x00
253 #define ASC_SCSIDIR_T2H		0x08
254 #define ASC_SCSIDIR_H2T		0x10
255 #define ASC_SCSIDIR_NODATA	0x18
256 
257 
258 #define SCSI_SENKEY_NO_SENSE		0x00
259 #define SCSI_SENKEY_UNDEFINED		0x01
260 #define SCSI_SENKEY_NOT_READY		0x02
261 #define SCSI_SENKEY_MEDIUM_ERR		0x03
262 #define SCSI_SENKEY_HW_ERR		0x04
263 #define SCSI_SENKEY_ILLEGAL		0x05
264 #define SCSI_SENKEY_ATTENTION		0x06
265 #define SCSI_SENKEY_PROTECTED		0x07
266 #define SCSI_SENKEY_BLANK		0x08
267 #define SCSI_SENKEY_V_UNIQUE		0x09
268 #define SCSI_SENKEY_CPY_ABORT		0x0A
269 #define SCSI_SENKEY_ABORT		0x0B
270 #define SCSI_SENKEY_EQUAL		0x0C
271 #define SCSI_SENKEY_VOL_OVERFLOW	0x0D
272 #define SCSI_SENKEY_MISCOMP		0x0E
273 #define SCSI_SENKEY_RESERVED		0x0F
274 #define SCSI_ASC_NOMEDIA		0x3A
275 
276 
277 #define ASC_CCB_HOST(x)  ((u_int8_t)((u_int8_t)(x) >> 4))
278 #define ASC_CCB_TID(x)   ((u_int8_t)((u_int8_t)(x) & (u_int8_t)0x0F))
279 #define ASC_CCB_LUN(x)   ((u_int8_t)((uint)(x) >> 13))
280 
281 
282 #define SS_GOOD				0x00
283 #define SS_CHK_CONDITION		0x02
284 #define SS_CONDITION_MET		0x04
285 #define SS_TARGET_BUSY			0x08
286 #define SS_INTERMID			0x10
287 #define SS_INTERMID_COND_MET		0x14
288 #define SS_RSERV_CONFLICT		0x18
289 #define SS_CMD_TERMINATED		0x22
290 #define SS_QUEUE_FULL			0x28
291 
292 
293 #define MS_CMD_DONE			0x00
294 #define MS_EXTEND			0x01
295 #define MS_SDTR_LEN			0x03
296 #define MS_SDTR_CODE			0x01
297 #define MS_WDTR_LEN			0x02
298 #define MS_WDTR_CODE			0x03
299 #define MS_MDP_LEN			0x05
300 #define MS_MDP_CODE			0x00
301 
302 
303 #define M1_SAVE_DATA_PTR		0x02
304 #define M1_RESTORE_PTRS			0x03
305 #define M1_DISCONNECT			0x04
306 #define M1_INIT_DETECTED_ERR		0x05
307 #define M1_ABORT			0x06
308 #define M1_MSG_REJECT			0x07
309 #define M1_NO_OP			0x08
310 #define M1_MSG_PARITY_ERR		0x09
311 #define M1_LINK_CMD_DONE		0x0A
312 #define M1_LINK_CMD_DONE_WFLAG		0x0B
313 #define M1_BUS_DVC_RESET		0x0C
314 #define M1_ABORT_TAG			0x0D
315 #define M1_CLR_QUEUE			0x0E
316 #define M1_INIT_RECOVERY		0x0F
317 #define M1_RELEASE_RECOVERY		0x10
318 #define M1_KILL_IO_PROC			0x11
319 #define M2_QTAG_MSG_SIMPLE		0x20
320 #define M2_QTAG_MSG_HEAD		0x21
321 #define M2_QTAG_MSG_ORDERED		0x22
322 #define M2_IGNORE_WIDE_RESIDUE		0x23
323 
324 
325 /*
326  * SCSI Iquiry structure
327  */
328 
329 typedef struct
330 {
331 	u_int8_t	peri_dvc_type:5;
332 	u_int8_t	peri_qualifier:3;
333 } ASC_SCSI_INQ0;
334 
335 typedef struct
336 {
337 	u_int8_t	dvc_type_modifier:7;
338 	u_int8_t	rmb:1;
339 } ASC_SCSI_INQ1;
340 
341 typedef struct
342 {
343 	u_int8_t	ansi_apr_ver:3;
344 	u_int8_t	ecma_ver:3;
345 	u_int8_t	iso_ver:2;
346 } ASC_SCSI_INQ2;
347 
348 typedef struct
349 {
350 	u_int8_t	rsp_data_fmt:4;
351 	u_int8_t	res:2;
352 	u_int8_t	TemIOP:1;
353 	u_int8_t	aenc:1;
354 } ASC_SCSI_INQ3;
355 
356 typedef struct
357 {
358 	u_int8_t	StfRe:1;
359 	u_int8_t	CmdQue:1;
360 	u_int8_t	Reserved:1;
361 	u_int8_t	Linked:1;
362 	u_int8_t	Sync:1;
363 	u_int8_t	WBus16:1;
364 	u_int8_t	WBus32:1;
365 	u_int8_t	RelAdr:1;
366 } ASC_SCSI_INQ7;
367 
368 typedef struct
369 {
370 	ASC_SCSI_INQ0	byte0;
371 	ASC_SCSI_INQ1	byte1;
372 	ASC_SCSI_INQ2	byte2;
373 	ASC_SCSI_INQ3	byte3;
374 	u_int8_t	add_len;
375 	u_int8_t	res1;
376 	u_int8_t	res2;
377 	ASC_SCSI_INQ7	byte7;
378 	u_int8_t	vendor_id[8];
379 	u_int8_t	product_id[16];
380 	u_int8_t	product_rev_level[4];
381 } ASC_SCSI_INQUIRY;
382 
383 
384 /*
385  * SCSIQ Microcode offsets
386  */
387 #define ASC_SCSIQ_CPY_BEG		 4
388 #define ASC_SCSIQ_SGHD_CPY_BEG		 2
389 #define ASC_SCSIQ_B_FWD			 0
390 #define ASC_SCSIQ_B_BWD			 1
391 #define ASC_SCSIQ_B_STATUS		 2
392 #define ASC_SCSIQ_B_QNO			 3
393 #define ASC_SCSIQ_B_CNTL		 4
394 #define ASC_SCSIQ_B_SG_QUEUE_CNT	 5
395 #define ASC_SCSIQ_D_DATA_ADDR		 8
396 #define ASC_SCSIQ_D_DATA_CNT		12
397 #define ASC_SCSIQ_B_SENSE_LEN		20
398 #define ASC_SCSIQ_DONE_INFO_BEG		22
399 #define ASC_SCSIQ_D_CCBPTR		22
400 #define ASC_SCSIQ_B_TARGET_IX		26
401 #define ASC_SCSIQ_B_CDB_LEN		28
402 #define ASC_SCSIQ_B_TAG_CODE		29
403 #define ASC_SCSIQ_W_VM_ID		30
404 #define ASC_SCSIQ_DONE_STATUS		32
405 #define ASC_SCSIQ_HOST_STATUS		33
406 #define ASC_SCSIQ_SCSI_STATUS		34
407 #define ASC_SCSIQ_CDB_BEG		36
408 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR	56
409 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 	60
410 #define ASC_SCSIQ_B_SG_WK_QP		49
411 #define ASC_SCSIQ_B_SG_WK_IX		50
412 #define ASC_SCSIQ_W_REQ_COUNT		52
413 #define ASC_SCSIQ_B_LIST_CNT		 6
414 #define ASC_SCSIQ_B_CUR_LIST_CNT	 7
415 
416 
417 #define ASC_DEF_SCSI1_QNG	4
418 #define ASC_MAX_SCSI1_QNG	4
419 #define ASC_DEF_SCSI2_QNG	16
420 #define ASC_MAX_SCSI2_QNG	32
421 
422 #define ASC_TAG_CODE_MASK	0x23
423 
424 #define ASC_STOP_REQ_RISC_STOP		0x01
425 #define ASC_STOP_ACK_RISC_STOP		0x03
426 #define ASC_STOP_CLEAN_UP_BUSY_Q	0x10
427 #define ASC_STOP_CLEAN_UP_DISC_Q	0x20
428 #define ASC_STOP_HOST_REQ_RISC_HALT	0x40
429 
430 #define ASC_TIDLUN_TO_IX(tid, lun)	(ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
431 #define ASC_TID_TO_TARGET_ID(tid)	(ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
432 #define ASC_TIX_TO_TARGET_ID(tix)	(0x01 << ((tix) & ASC_MAX_TID))
433 #define ASC_TIX_TO_TID(tix)		((tix) & ASC_MAX_TID)
434 #define ASC_TID_TO_TIX(tid)		((tid) & ASC_MAX_TID)
435 #define ASC_TIX_TO_LUN(tix)		(((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
436 #define ASC_QNO_TO_QADDR(q_no)		((ASC_QADR_BEG)+((int)(q_no) << 6))
437 
438 
439 /*
440  * Structures used to dialog with the RISC engine
441  */
442 
443 typedef struct asc_scisq_1
444 {
445 	u_int8_t	status;	/* see below status values */
446 	u_int8_t	q_no;	/* Queue ID of the first queue for this transaction */
447 	u_int8_t	cntl;	/* see below cntl values */
448 	u_int8_t	sg_queue_cnt;	/* number of SG entries */
449 	u_int8_t	target_id;
450 	u_int8_t	target_lun;
451 	u_int32_t	data_addr; /* physical address of first segment to transef */
452 	u_int32_t	data_cnt;  /* byte count of first segment to transfer */
453 	u_int32_t	sense_addr; /* physical address of the sense buffer */
454 	u_int8_t	sense_len; /* lenght of sense buffer */
455 	u_int8_t	extra_bytes;
456 } ASC_SCSIQ_1;
457 
458 /* status values */
459 #define ASC_QS_FREE		0x00
460 #define ASC_QS_READY		0x01
461 #define ASC_QS_DISC1		0x02
462 #define ASC_QS_DISC2		0x04
463 #define ASC_QS_BUSY		0x08
464 #define ASC_QS_ABORTED		0x40
465 #define ASC_QS_DONE		0x80
466 
467 /* cntl values */
468 #define ASC_QC_NO_CALLBACK	0x01
469 #define ASC_QC_SG_SWAP_QUEUE	0x02
470 #define ASC_QC_SG_HEAD		0x04
471 #define ASC_QC_DATA_IN		0x08
472 #define ASC_QC_DATA_OUT		0x10
473 #define ASC_QC_URGENT		0x20
474 #define ASC_QC_MSG_OUT		0x40
475 #define ASC_QC_REQ_SENSE	0x80
476 
477 
478 typedef struct asc_scisq_2
479 {
480 	u_int32_t	ccb_ptr;	/* pointer to our CCB */
481 	u_int8_t	target_ix;	/* combined TID and LUN */
482 	u_int8_t	flag;
483 	u_int8_t	cdb_len;	/* bytes of Command Descriptor Block */
484 	u_int8_t	tag_code;	/* type of this transaction. see below */
485 	u_int16_t	vm_id;
486 } ASC_SCSIQ_2;
487 
488 /* tag_code values */
489 #define ASC_TAG_FLAG_EXTRA_BYTES		0x10
490 #define ASC_TAG_FLAG_DISABLE_DISCONNECT		0x04
491 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX	0x08
492 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST	0x40
493 
494 
495 typedef struct asc_scsiq_3
496 {
497 	u_int8_t	done_stat;	/* see below done_stat values */
498 	u_int8_t	host_stat;	/* see below host_stat values */
499 	u_int8_t	scsi_stat;
500 	u_int8_t	scsi_msg;
501 } ASC_SCSIQ_3;
502 
503 /* done_stat values */
504 #define ASC_QD_IN_PROGRESS		0x00
505 #define ASC_QD_NO_ERROR			0x01
506 #define ASC_QD_ABORTED_BY_HOST		0x02
507 #define ASC_QD_WITH_ERROR		0x04
508 #define ASC_QD_INVALID_REQUEST		0x80
509 #define ASC_QD_INVALID_HOST_NUM		0x81
510 #define ASC_QD_INVALID_DEVICE		0x82
511 #define ASC_QD_ERR_INTERNAL		0xFF
512 
513 /* host_stat values */
514 #define ASC_QHSTA_NO_ERROR			0x00
515 #define ASC_QHSTA_M_SEL_TIMEOUT			0x11
516 #define ASC_QHSTA_M_DATA_OVER_RUN		0x12
517 #define ASC_QHSTA_M_DATA_UNDER_RUN		0x12
518 #define ASC_QHSTA_M_UNEXPECTED_BUS_FREE		0x13
519 #define ASC_QHSTA_M_BAD_BUS_PHASE_SEQ		0x14
520 #define ASC_QHSTA_D_QDONE_SG_LIST_CORRUPTED	0x21
521 #define ASC_QHSTA_D_ASC_DVC_ERROR_CODE_SET	0x22
522 #define ASC_QHSTA_D_HOST_ABORT_FAILED		0x23
523 #define ASC_QHSTA_D_EXE_SCSI_Q_FAILED		0x24
524 #define ASC_QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT	0x25
525 #define ASC_QHSTA_D_ASPI_NO_BUF_POOL		0x26
526 #define ASC_QHSTA_M_WTM_TIMEOUT			0x41
527 #define ASC_QHSTA_M_BAD_CMPL_STATUS_IN		0x42
528 #define ASC_QHSTA_M_NO_AUTO_REQ_SENSE		0x43
529 #define ASC_QHSTA_M_AUTO_REQ_SENSE_FAIL		0x44
530 #define ASC_QHSTA_M_TARGET_STATUS_BUSY		0x45
531 #define ASC_QHSTA_M_BAD_TAG_CODE		0x46
532 #define ASC_QHSTA_M_BAD_QUEUE_FULL_OR_BUSY	0x47
533 #define ASC_QHSTA_M_HUNG_REQ_SCSI_BUS_RESET	0x48
534 #define ASC_QHSTA_D_LRAM_CMP_ERROR		0x81
535 #define ASC_QHSTA_M_MICRO_CODE_ERROR_HALT	0xA1
536 
537 
538 typedef struct asc_scsiq_4
539 {
540 	u_int8_t	cdb[ASC_MAX_CDB_LEN];
541 	u_int8_t	y_first_sg_list_qp;
542 	u_int8_t	y_working_sg_qp;
543 	u_int8_t	y_working_sg_ix;
544 	u_int8_t	y_res;
545 	u_int16_t	x_req_count;
546 	u_int16_t	x_reconnect_rtn;
547 	u_int32_t	x_saved_data_addr;
548 	u_int32_t	x_saved_data_cnt;
549 } ASC_SCSIQ_4;
550 
551 typedef struct asc_q_done_info
552 {
553 	ASC_SCSIQ_2	d2;
554 	ASC_SCSIQ_3	d3;
555 	u_int8_t	q_status;
556 	u_int8_t	q_no;
557 	u_int8_t	cntl;
558 	u_int8_t	sense_len;
559 	u_int8_t	extra_bytes;
560 	u_int8_t	res;
561 	u_int32_t	remain_bytes;
562 } ASC_QDONE_INFO;
563 
564 typedef struct asc_sg_list
565 {
566 	u_int32_t	addr;
567 	u_int32_t	bytes;
568 } ASC_SG_LIST;
569 
570 typedef struct asc_sg_head
571 {
572 	u_int16_t	entry_cnt;	/* number of SG entries */
573 	u_int16_t	queue_cnt;	/* number of queues required to store SG entries */
574 	u_int16_t	entry_to_copy;	/* number of SG entries to copy to the board */
575 	u_int16_t	res;
576 	ASC_SG_LIST	sg_list[ASC_MAX_SG_LIST];
577 } ASC_SG_HEAD;
578 
579 #define ASC_MIN_SG_LIST   2
580 
581 typedef struct asc_min_sg_head
582 {
583 	u_int16_t	entry_cnt;
584 	u_int16_t	queue_cnt;
585 	u_int16_t	entry_to_copy;
586 	u_int16_t	res;
587 	ASC_SG_LIST	sg_list[ASC_MIN_SG_LIST];
588 } ASC_MIN_SG_HEAD;
589 
590 #define ASC_QCX_SORT		0x0001
591 #define ASC_QCX_COALEASE	0x0002
592 
593 typedef struct asc_scsi_q
594 {
595 	ASC_SCSIQ_1	q1;
596 	ASC_SCSIQ_2	q2;
597 	u_int8_t	*cdbptr;	/* pointer to CDB to execute */
598 	ASC_SG_HEAD	*sg_head;	/* pointer to SG list */
599 } ASC_SCSI_Q;
600 
601 typedef struct asc_scsi_req_q
602 {
603 	ASC_SCSIQ_1	q1;
604 	ASC_SCSIQ_2	q2;
605 	u_int8_t	*cdbptr;
606 	ASC_SG_HEAD	*sg_head;
607 	u_int8_t	*sense_ptr;
608 	ASC_SCSIQ_3	q3;
609 	u_int8_t	cdb[ASC_MAX_CDB_LEN];
610 	u_int8_t	sense[ASC_MIN_SENSE_LEN];
611 } ASC_SCSI_REQ_Q;
612 
613 typedef struct asc_scsi_bios_req_q
614 {
615 	ASC_SCSIQ_1	q1;
616 	ASC_SCSIQ_2	q2;
617 	u_int8_t	*cdbptr;
618 	ASC_SG_HEAD	*sg_head;
619 	u_int8_t	*sense_ptr;
620 	ASC_SCSIQ_3	q3;
621 	u_int8_t	cdb[ASC_MAX_CDB_LEN];
622 	u_int8_t	sense[ASC_MIN_SENSE_LEN];
623 } ASC_SCSI_BIOS_REQ_Q;
624 
625 typedef struct asc_risc_q
626 {
627 	u_int8_t	fwd;
628 	u_int8_t	bwd;
629 	ASC_SCSIQ_1	i1;
630 	ASC_SCSIQ_2	i2;
631 	ASC_SCSIQ_3	i3;
632 	ASC_SCSIQ_4	i4;
633 } ASC_RISC_Q;
634 
635 typedef struct asc_sg_list_q
636 {
637 	u_int8_t	seq_no;
638 	u_int8_t	q_no;
639 	u_int8_t	cntl;		/* see below cntl values */
640 	u_int8_t	sg_head_qp;
641 	u_int8_t	sg_list_cnt;
642 	u_int8_t	sg_cur_list_cnt;
643 } ASC_SG_LIST_Q;
644 
645 /* cntl values */
646 #define ASC_QCSG_SG_XFER_LIST	0x02
647 #define ASC_QCSG_SG_XFER_MORE	0x04
648 #define ASC_QCSG_SG_XFER_END	0x08
649 
650 #define ASC_SGQ_B_SG_CNTL		4
651 #define ASC_SGQ_B_SG_HEAD_QP		5
652 #define ASC_SGQ_B_SG_LIST_CNT		6
653 #define ASC_SGQ_B_SG_CUR_LIST_CNT	7
654 #define ASC_SGQ_LIST_BEG		8
655 
656 
657 typedef struct asc_risc_sg_list_q
658 {
659 	u_int8_t	fwd;
660 	u_int8_t	bwd;
661 	ASC_SG_LIST_Q	sg;
662 	ASC_SG_LIST	sg_list[7];
663 } ASC_RISC_SG_LIST_Q;
664 
665 
666 #define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP  0x1000000UL
667 #define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP  1024
668 
669 #define ASCQ_ERR_NO_ERROR		0x00
670 #define ASCQ_ERR_IO_NOT_FOUND		0x01
671 #define ASCQ_ERR_LOCAL_MEM		0x02
672 #define ASCQ_ERR_CHKSUM			0x03
673 #define ASCQ_ERR_START_CHIP		0x04
674 #define ASCQ_ERR_INT_TARGET_ID		0x05
675 #define ASCQ_ERR_INT_LOCAL_MEM		0x06
676 #define ASCQ_ERR_HALT_RISC		0x07
677 #define ASCQ_ERR_GET_ASPI_ENTRY		0x08
678 #define ASCQ_ERR_CLOSE_ASPI		0x09
679 #define ASCQ_ERR_HOST_INQUIRY		0x0A
680 #define ASCQ_ERR_SAVED_CCB_BAD		0x0B
681 #define ASCQ_ERR_QCNTL_SG_LIST		0x0C
682 #define ASCQ_ERR_Q_STATUS		0x0D
683 #define ASCQ_ERR_WR_SCSIQ		0x0E
684 #define ASCQ_ERR_PC_ADDR		0x0F
685 #define ASCQ_ERR_SYN_OFFSET		0x10
686 #define ASCQ_ERR_SYN_XFER_TIME		0x11
687 #define ASCQ_ERR_LOCK_DMA		0x12
688 #define ASCQ_ERR_UNLOCK_DMA		0x13
689 #define ASCQ_ERR_VDS_CHK_INSTALL	0x14
690 #define ASCQ_ERR_MICRO_CODE_HALT	0x15
691 #define ASCQ_ERR_SET_LRAM_ADDR		0x16
692 #define ASCQ_ERR_CUR_QNG		0x17
693 #define ASCQ_ERR_SG_Q_LINKS		0x18
694 #define ASCQ_ERR_SCSIQ_PTR		0x19
695 #define ASCQ_ERR_ISR_RE_ENTRY		0x1A
696 #define ASCQ_ERR_CRITICAL_RE_ENTRY	0x1B
697 #define ASCQ_ERR_ISR_ON_CRITICAL	0x1C
698 #define ASCQ_ERR_SG_LIST_ODD_ADDRESS	0x1D
699 #define ASCQ_ERR_XFER_ADDRESS_TOO_BIG	0x1E
700 #define ASCQ_ERR_SCSIQ_NULL_PTR		0x1F
701 #define ASCQ_ERR_SCSIQ_BAD_NEXT_PTR 	0x20
702 #define ASCQ_ERR_GET_NUM_OF_FREE_Q	0x21
703 #define ASCQ_ERR_SEND_SCSI_Q		0x22
704 #define ASCQ_ERR_HOST_REQ_RISC_HALT 	0x23
705 #define ASCQ_ERR_RESET_SDTR		0x24
706 
707 #define ASC_WARN_NO_ERROR		0x0000
708 #define ASC_WARN_IO_PORT_ROTATE		0x0001
709 #define ASC_WARN_EEPROM_CHKSUM		0x0002
710 #define ASC_WARN_IRQ_MODIFIED		0x0004
711 #define ASC_WARN_AUTO_CONFIG		0x0008
712 #define ASC_WARN_CMD_QNG_CONFLICT	0x0010
713 #define ASC_WARN_EEPROM_RECOVER		0x0020
714 #define ASC_WARN_CFG_MSW_RECOVER	0x0040
715 #define ASC_WARN_SET_PCI_CONFIG_SPACE	0x0080
716 
717 #define ASC_IERR_WRITE_EEPROM		0x0001
718 #define ASC_IERR_MCODE_CHKSUM		0x0002
719 #define ASC_IERR_SET_PC_ADDR		0x0004
720 #define ASC_IERR_START_STOP_CHIP	0x0008
721 #define ASC_IERR_IRQ_NO			0x0010
722 #define ASC_IERR_SET_IRQ_NO		0x0020
723 #define ASC_IERR_CHIP_VERSION		0x0040
724 #define ASC_IERR_SET_SCSI_ID		0x0080
725 #define ASC_IERR_GET_PHY_ADDR		0x0100
726 #define ASC_IERR_BAD_SIGNATURE		0x0200
727 #define ASC_IERR_NO_BUS_TYPE		0x0400
728 #define ASC_IERR_SCAM			0x0800
729 #define ASC_IERR_SET_SDTR		0x1000
730 #define ASC_IERR_RW_LRAM		0x8000
731 
732 #define ASC_DEF_IRQ_NO			10
733 #define ASC_MAX_IRQ_NO			15
734 #define ASC_MIN_IRQ_NO			10
735 #define ASC_MIN_REMAIN_Q		0x02
736 #define ASC_DEF_MAX_TOTAL_QNG   0xF0
737 #define ASC_MIN_TAG_Q_PER_DVC   0x04
738 #define ASC_DEF_TAG_Q_PER_DVC   0x04
739 #define ASC_MIN_FREE_Q		ASC_MIN_REMAIN_Q
740 #define ASC_MIN_TOTAL_QNG	((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
741 #define ASC_MAX_TOTAL_QNG	240
742 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG	16
743 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG		8
744 #define ASC_MAX_PCI_INRAM_TOTAL_QNG		20
745 #define ASC_MAX_INRAM_TAG_QNG	16
746 #define ASC_IOADR_TABLE_MAX_IX	11
747 #define ASC_IOADR_GAP			0x10
748 #define ASC_SEARCH_IOP_GAP		0x10
749 #define ASC_MIN_IOP_ADDR		0x0100
750 #define ASC_MAX_IOP_ADDR		0x03F0
751 
752 #define ASC_IOADR_1			0x0110
753 #define ASC_IOADR_2			0x0130
754 #define ASC_IOADR_3			0x0150
755 #define ASC_IOADR_4			0x0190
756 #define ASC_IOADR_5			0x0210
757 #define ASC_IOADR_6			0x0230
758 #define ASC_IOADR_7			0x0250
759 #define ASC_IOADR_8			0x0330
760 
761 #define ASC_IOADR_DEF			ASC_IOADR_8
762 #define ASC_LIB_SCSIQ_WK_SP		256
763 #define ASC_MAX_SYN_XFER_NO		16
764 #define ASC_SYN_MAX_OFFSET		0x0F
765 #define ASC_DEF_SDTR_OFFSET		0x0F
766 #define ASC_DEF_SDTR_INDEX		0x00
767 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX	0x02
768 
769 
770 /*
771  * This structure is used to handle internal messages
772  * during interrupt handling routine
773  */
774 typedef struct ext_msg
775 {
776 	u_int8_t	msg_type;
777 	u_int8_t	msg_len;
778 	u_int8_t	msg_req;
779 
780 	union
781 	{
782 		struct
783 		{
784 			u_int8_t	sdtr_xfer_period;
785 			u_int8_t	sdtr_req_ack_offset;
786 		} sdtr;
787 
788 		struct
789 		{
790 			u_int8_t	wdtr_width;
791 		} wdtr;
792 
793 		struct
794 		{
795 			u_int8_t	mdp_b3;
796 			u_int8_t	mdp_b2;
797 			u_int8_t	mdp_b1;
798 			u_int8_t	mdp_b0;
799 		} mdp;
800 	} u_ext_msg;
801 
802 	u_int8_t	res;
803 } EXT_MSG;
804 
805 #define xfer_period	u_ext_msg.sdtr.sdtr_xfer_period
806 #define req_ack_offset	u_ext_msg.sdtr.sdtr_req_ack_offset
807 #define wdtr_width	u_ext_msg.wdtr.wdtr_width
808 #define mdp_b3		u_ext_msg.mdp_b3
809 #define mdp_b2		u_ext_msg.mdp_b2
810 #define mdp_b1		u_ext_msg.mdp_b1
811 #define mdp_b0		u_ext_msg.mdp_b0
812 
813 
814 #define ASC_DEF_DVC_CNTL		0xFFFF
815 #define ASC_DEF_CHIP_SCSI_ID		7
816 #define ASC_DEF_ISA_DMA_SPEED		4
817 
818 #define ASC_PCI_DEVICE_ID_REV_A		0x1100
819 #define ASC_PCI_DEVICE_ID_REV_B		0x1200
820 
821 #define ASC_BUG_FIX_IF_NOT_DWB		0x0001
822 #define ASC_BUG_FIX_ASYN_USE_SYN	0x0002
823 
824 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB	0x41
825 
826 #define ASC_MIN_TAGGED_CMD	7
827 
828 #define ASC_MAX_SCSI_RESET_WAIT	30
829 
830 
831 typedef struct asc_softc
832 {
833 	struct device		sc_dev;
834 
835 	bus_space_tag_t		sc_iot;
836 	bus_space_handle_t	sc_ioh;
837 	bus_dma_tag_t		sc_dmat;
838 	bus_dmamap_t		sc_dmamap_control; /* maps the control structures */
839 	void			*sc_ih;
840 
841 	struct adv_control	*sc_control; /* control structures */
842 	TAILQ_HEAD(, adv_ccb)	sc_free_ccb, sc_waiting_ccb;
843 	struct scsipi_link	sc_link;     /* prototype for devs */
844 
845 	LIST_HEAD(, scsipi_xfer) sc_queue;
846 	struct scsipi_xfer	*sc_queuelast;
847 
848 	u_int8_t		*overrun_buf;
849 
850 	u_int16_t		sc_flags;	/* see below sc_flags values */
851 
852 	u_int16_t		dvc_cntl;
853 	u_int16_t		bug_fix_cntl;
854 	u_int16_t		bus_type;
855 
856 	ulong			isr_callback;
857 
858 	ASC_SCSI_BIT_ID_TYPE	init_sdtr;
859 	ASC_SCSI_BIT_ID_TYPE	sdtr_done;
860 	ASC_SCSI_BIT_ID_TYPE	use_tagged_qng;
861 	ASC_SCSI_BIT_ID_TYPE	unit_not_ready;
862 	ASC_SCSI_BIT_ID_TYPE	queue_full_or_busy;
863 	ASC_SCSI_BIT_ID_TYPE	start_motor;
864 
865 	ASC_SCSI_BIT_ID_TYPE	can_tagged_qng;
866 	ASC_SCSI_BIT_ID_TYPE	cmd_qng_enabled;
867 	ASC_SCSI_BIT_ID_TYPE	disc_enable;
868 	ASC_SCSI_BIT_ID_TYPE	sdtr_enable;
869 	u_int8_t		chip_scsi_id;
870 	u_int8_t		isa_dma_speed;
871 	u_int8_t		isa_dma_channel;
872 	u_int8_t		chip_version;
873 	u_int16_t		pci_device_id;
874 	u_int16_t		lib_serial_no;
875 	u_int16_t		lib_version;
876 	u_int16_t		mcode_date;
877 	u_int16_t		mcode_version;
878 	u_int8_t		max_tag_qng[ASC_MAX_TID + 1];
879 	u_int8_t		sdtr_period_offset[ASC_MAX_TID + 1];
880 	u_int8_t		adapter_info[6];
881 
882 	u_int8_t		scsi_reset_wait;
883 	u_int8_t		max_total_qng;
884 	u_int8_t		cur_total_qng;
885 	u_int8_t		irq_no;
886 	u_int8_t		last_q_shortage;
887 
888 	u_int8_t		cur_dvc_qng[ASC_MAX_TID + 1];
889 	u_int8_t		max_dvc_qng[ASC_MAX_TID + 1];
890 	u_int8_t		sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
891 	u_int8_t		sdtr_period_tbl_size;	/* see below */
892 	u_int8_t		sdtr_data[ASC_MAX_TID+1];
893 
894 	u_int16_t		reqcnt[ASC_MAX_TID+1]; /* Starvation request count */
895 
896 	u_int32_t		max_dma_count;
897 	ASC_SCSI_BIT_ID_TYPE	pci_fix_asyn_xfer;
898 	ASC_SCSI_BIT_ID_TYPE	pci_fix_asyn_xfer_always;
899 	u_int8_t		max_sdtr_index;
900 	u_int8_t		host_init_sdtr_index;
901 } ASC_SOFTC;
902 
903 /* sc_flags values */
904 #define ASC_HOST_IN_RESET		0x01
905 #define ASC_HOST_IN_ABORT		0x02
906 #define ASC_WIDE_BOARD			0x04
907 #define ASC_SELECT_QUEUE_DEPTHS		0x08
908 
909 /* sdtr_period_tbl_size values */
910 #define SYN_XFER_NS_0		 25
911 #define SYN_XFER_NS_1		 30
912 #define SYN_XFER_NS_2		 35
913 #define SYN_XFER_NS_3		 40
914 #define SYN_XFER_NS_4		 50
915 #define SYN_XFER_NS_5		 60
916 #define SYN_XFER_NS_6		 70
917 #define SYN_XFER_NS_7		 85
918 
919 #define SYN_ULTRA_XFER_NS_0	 12
920 #define SYN_ULTRA_XFER_NS_1	 19
921 #define SYN_ULTRA_XFER_NS_2	 25
922 #define SYN_ULTRA_XFER_NS_3	 32
923 #define SYN_ULTRA_XFER_NS_4	 38
924 #define SYN_ULTRA_XFER_NS_5	 44
925 #define SYN_ULTRA_XFER_NS_6	 50
926 #define SYN_ULTRA_XFER_NS_7	 57
927 #define SYN_ULTRA_XFER_NS_8	 63
928 #define SYN_ULTRA_XFER_NS_9	 69
929 #define SYN_ULTRA_XFER_NS_10	 75
930 #define SYN_ULTRA_XFER_NS_11	 82
931 #define SYN_ULTRA_XFER_NS_12	 88
932 #define SYN_ULTRA_XFER_NS_13	 94
933 #define SYN_ULTRA_XFER_NS_14	100
934 #define SYN_ULTRA_XFER_NS_15	107
935 
936 
937 /* second level interrupt callback type definition */
938 typedef int (* ASC_ISR_CALLBACK) (ASC_SOFTC *, ASC_QDONE_INFO *);
939 
940 
941 #define ASC_MCNTL_NO_SEL_TIMEOUT	0x0001
942 #define ASC_MCNTL_NULL_TARGET		0x0002
943 
944 #define ASC_CNTL_INITIATOR		0x0001
945 #define ASC_CNTL_BIOS_GT_1GB		0x0002
946 #define ASC_CNTL_BIOS_GT_2_DISK		0x0004
947 #define ASC_CNTL_BIOS_REMOVABLE		0x0008
948 #define ASC_CNTL_NO_SCAM		0x0010
949 #define ASC_CNTL_INT_MULTI_Q		0x0080
950 #define ASC_CNTL_NO_LUN_SUPPORT		0x0040
951 #define ASC_CNTL_NO_VERIFY_COPY		0x0100
952 #define ASC_CNTL_RESET_SCSI		0x0200
953 #define ASC_CNTL_INIT_INQUIRY	 	0x0400
954 #define ASC_CNTL_INIT_VERBOSE		0x0800
955 #define ASC_CNTL_SCSI_PARITY		0x1000
956 #define ASC_CNTL_BURST_MODE		0x2000
957 #define ASC_CNTL_SDTR_ENABLE_ULTRA	0x4000
958 
959 #define ASC_EEP_DVC_CFG_BEG_VL		 2
960 #define ASC_EEP_MAX_DVC_ADDR_VL		15
961 #define ASC_EEP_DVC_CFG_BEG		32
962 #define ASC_EEP_MAX_DVC_ADDR		45
963 #define ASC_EEP_DEFINED_WORDS		10
964 #define ASC_EEP_MAX_ADDR		63
965 #define ASC_EEP_RES_WORDS		 0
966 #define ASC_EEP_MAX_RETRY		20
967 #define ASC_MAX_INIT_BUSY_RETRY		 8
968 #define ASC_EEP_ISA_PNP_WSIZE		16
969 
970 
971 /*
972  * This structure is used to read/write EEProm configuration
973  */
974 typedef struct asceep_config
975 {
976 	u_int16_t	cfg_lsw;
977 	u_int16_t	cfg_msw;
978 #if BYTE_ORDER == BIG_ENDIAN
979 	u_int8_t	disc_enable;
980 	u_int8_t	init_sdtr;
981 	u_int8_t	start_motor;
982 	u_int8_t	use_cmd_qng;
983 	u_int8_t	max_tag_qng;
984 	u_int8_t	max_total_qng;
985 	u_int8_t	power_up_wait;
986 	u_int8_t	bios_scan;
987 	u_int8_t	isa_dma_speed:4;
988 	u_int8_t	chip_scsi_id:4;
989 	u_int8_t	no_scam;
990 #else
991 	u_int8_t	init_sdtr;
992 	u_int8_t	disc_enable;
993 	u_int8_t	use_cmd_qng;
994 	u_int8_t	start_motor;
995 	u_int8_t	max_total_qng;
996 	u_int8_t	max_tag_qng;
997 	u_int8_t	bios_scan;
998 	u_int8_t	power_up_wait;
999 	u_int8_t	no_scam;
1000 	u_int8_t	chip_scsi_id:4;
1001 	u_int8_t	isa_dma_speed:4;
1002 #endif
1003 	u_int8_t	dos_int13_table[ASC_MAX_TID + 1];
1004 	u_int8_t	adapter_info[6];
1005 	u_int16_t	cntl;
1006 	u_int16_t	chksum;
1007 } ASCEEP_CONFIG;
1008 
1009 #define ASC_PCI_CFG_LSW_SCSI_PARITY	0x0800
1010 #define ASC_PCI_CFG_LSW_BURST_MODE	0x0080
1011 #define ASC_PCI_CFG_LSW_INTR_ABLE	0x0020
1012 
1013 #define ASC_EEP_CMD_READ		0x80
1014 #define ASC_EEP_CMD_WRITE		0x40
1015 #define ASC_EEP_CMD_WRITE_ABLE		0x30
1016 #define ASC_EEP_CMD_WRITE_DISABLE	0x00
1017 
1018 #define ASC_OVERRUN_BSIZE		0x00000048UL
1019 
1020 #define ASC_CTRL_BREAK_ONCE		0x0001
1021 #define ASC_CTRL_BREAK_STAY_IDLE	0x0002
1022 
1023 #define ASCV_MSGOUT_BEG			0x0000
1024 #define ASCV_MSGOUT_SDTR_PERIOD		(ASCV_MSGOUT_BEG+3)
1025 #define ASCV_MSGOUT_SDTR_OFFSET		(ASCV_MSGOUT_BEG+4)
1026 #define ASCV_BREAK_SAVED_CODE		0x0006
1027 #define ASCV_MSGIN_BEG			(ASCV_MSGOUT_BEG+8)
1028 #define ASCV_MSGIN_SDTR_PERIOD		(ASCV_MSGIN_BEG+3)
1029 #define ASCV_MSGIN_SDTR_OFFSET		(ASCV_MSGIN_BEG+4)
1030 #define ASCV_SDTR_DATA_BEG		(ASCV_MSGIN_BEG+8)
1031 #define ASCV_SDTR_DONE_BEG		(ASCV_SDTR_DATA_BEG+8)
1032 #define ASCV_MAX_DVC_QNG_BEG		0x0020
1033 #define ASCV_BREAK_ADDR		   	0x0028
1034 #define ASCV_BREAK_NOTIFY_COUNT 	0x002A
1035 #define ASCV_BREAK_CONTROL		0x002C
1036 #define ASCV_BREAK_HIT_COUNT		0x002E
1037 
1038 #define ASCV_ASCDVC_ERR_CODE_W		0x0030
1039 #define ASCV_MCODE_CHKSUM_W		0x0032
1040 #define ASCV_MCODE_SIZE_W		0x0034
1041 #define ASCV_STOP_CODE_B		0x0036
1042 #define ASCV_DVC_ERR_CODE_B		0x0037
1043 #define ASCV_OVERRUN_PADDR_D		0x0038
1044 #define ASCV_OVERRUN_BSIZE_D		0x003C
1045 #define ASCV_HALTCODE_W			0x0040
1046 #define ASCV_CHKSUM_W			0x0042
1047 #define ASCV_MC_DATE_W			0x0044
1048 #define ASCV_MC_VER_W			0x0046
1049 #define ASCV_NEXTRDY_B			0x0048
1050 #define ASCV_DONENEXT_B	  		0x0049
1051 #define ASCV_USE_TAGGED_QNG_B		0x004A
1052 #define ASCV_SCSIBUSY_B	 		0x004B
1053 #define ASCV_Q_DONE_IN_PROGRESS_B	0x004C
1054 #define ASCV_CURCDB_B			0x004D
1055 #define ASCV_RCLUN_B			0x004E
1056 #define ASCV_BUSY_QHEAD_B		0x004F
1057 #define ASCV_DISC1_QHEAD_B		0x0050
1058 #define ASCV_DISC_ENABLE_B		0x0052
1059 #define ASCV_CAN_TAGGED_QNG_B 		0x0053
1060 #define ASCV_HOSTSCSI_ID_B		0x0055
1061 #define ASCV_MCODE_CNTL_B		0x0056
1062 #define ASCV_NULL_TARGET_B		0x0057
1063 #define ASCV_FREE_Q_HEAD_W		0x0058
1064 #define ASCV_DONE_Q_TAIL_W		0x005A
1065 #define ASCV_FREE_Q_HEAD_B		(ASCV_FREE_Q_HEAD_W+1)
1066 #define ASCV_DONE_Q_TAIL_B		(ASCV_DONE_Q_TAIL_W+1)
1067 #define ASCV_HOST_FLAG_B		0x005D
1068 #define ASCV_TOTAL_READY_Q_B  		0x0064
1069 #define ASCV_VER_SERIAL_B	 	0x0065
1070 #define ASCV_HALTCODE_SAVED_W		0x0066
1071 #define ASCV_WTM_FLAG_B			0x0068
1072 #define ASCV_RISC_FLAG_B		0x006A
1073 #define ASCV_REQ_SG_LIST_QP		0x006B
1074 
1075 #define ASC_HOST_FLAG_IN_ISR		0x01
1076 #define ASC_HOST_FLAG_ACK_INT		0x02
1077 #define ASC_RISC_FLAG_GEN_INT		0x01
1078 #define ASC_RISC_FLAG_REQ_SG_LIST	0x02
1079 
1080 #define ASC_IOP_CTRL			0x0F
1081 #define ASC_IOP_STATUS			0x0E
1082 #define ASC_IOP_INT_ACK			ASC_IOP_STATUS
1083 #define ASC_IOP_REG_IFC			0x0D
1084 #define ASC_IOP_SYN_OFFSET		0x0B
1085 #define ASC_IOP_EXTRA_CONTROL	0x0D
1086 #define ASC_IOP_REG_PC			0x0C
1087 #define ASC_IOP_RAM_ADDR		0x0A
1088 #define ASC_IOP_RAM_DATA		0x08
1089 #define ASC_IOP_EEP_DATA		0x06
1090 #define ASC_IOP_EEP_CMD			0x07
1091 #define ASC_IOP_VERSION			0x03
1092 #define ASC_IOP_CONFIG_HIGH		0x04
1093 #define ASC_IOP_CONFIG_LOW		0x02
1094 #define ASC_IOP_SIG_BYTE		0x01
1095 #define ASC_IOP_SIG_WORD		0x00
1096 #define ASC_IOP_REG_DC1			0x0E
1097 #define ASC_IOP_REG_DC0			0x0C
1098 #define ASC_IOP_REG_SB			0x0B
1099 #define ASC_IOP_REG_DA1			0x0A
1100 #define ASC_IOP_REG_DA0			0x08
1101 #define ASC_IOP_REG_SC			0x09
1102 #define ASC_IOP_DMA_SPEED		0x07
1103 #define ASC_IOP_REG_FLAG		0x07
1104 #define ASC_IOP_FIFO_H			0x06
1105 #define ASC_IOP_FIFO_L			0x04
1106 #define ASC_IOP_REG_ID			0x05
1107 #define ASC_IOP_REG_QP			0x03
1108 #define ASC_IOP_REG_IH	 		0x02
1109 #define ASC_IOP_REG_IX	 		0x01
1110 #define ASC_IOP_REG_AX			0x00
1111 
1112 #define ASC_IFC_REG_LOCK		0x00
1113 #define ASC_IFC_REG_UNLOCK		0x09
1114 #define ASC_IFC_WR_EN_FILTER		0x10
1115 #define ASC_IFC_RD_NO_EEPROM		0x10
1116 #define ASC_IFC_SLEW_RATE		0x20
1117 #define ASC_IFC_ACT_NEG			0x40
1118 #define ASC_IFC_INP_FILTER		0x80
1119 #define ASC_IFC_INIT_DEFAULT	(ASC_IFC_ACT_NEG | ASC_IFC_REG_UNLOCK)
1120 
1121 #define SC_SEL	0x80
1122 #define SC_BSY	0x40
1123 #define SC_ACK	0x20
1124 #define SC_REQ	0x10
1125 #define SC_ATN	0x08
1126 #define SC_IO	0x04
1127 #define SC_CD	0x02
1128 #define SC_MSG	0x01
1129 
1130 #define SEC_SCSI_CTL		0x80
1131 #define SEC_ACTIVE_NEGATE	0x40
1132 #define SEC_SLEW_RATE		0x20
1133 #define SEC_ENABLE_FILTER	0x10
1134 
1135 #define ASC_HALT_EXTMSG_IN			0x8000
1136 #define ASC_HALT_CHK_CONDITION			0x8100
1137 #define ASC_HALT_SS_QUEUE_FULL			0x8200
1138 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX	0x8300
1139 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX	0x8400
1140 #define ASC_HALT_SDTR_REJECTED			0x4000
1141 
1142 #define ASC_MAX_QNO		0xF8
1143 
1144 #define ASC_DATA_SEC_BEG	0x0080
1145 #define ASC_DATA_SEC_END	0x0080
1146 #define ASC_CODE_SEC_BEG	0x0080
1147 #define ASC_CODE_SEC_END	0x0080
1148 #define ASC_QADR_BEG		(0x4000)
1149 #define ASC_QADR_USED		(ASC_MAX_QNO * 64)
1150 #define ASC_QADR_END		0x7FFF
1151 #define ASC_QLAST_ADR		0x7FC0
1152 #define ASC_QBLK_SIZE		0x40
1153 #define ASC_BIOS_DATA_QBEG	0xF8
1154 #define ASC_MIN_ACTIVE_QNO	0x01
1155 #define ASC_QLINK_END		0xFF
1156 #define ASC_EEPROM_WORDS	0x10
1157 #define ASC_MAX_MGS_LEN		0x10
1158 
1159 #define ASC_BIOS_ADDR_DEF	0xDC00
1160 #define ASC_BIOS_SIZE		0x3800
1161 #define ASC_BIOS_RAM_OFF	0x3800
1162 #define ASC_BIOS_RAM_SIZE 	0x800
1163 #define ASC_BIOS_MIN_ADDR	0xC000
1164 #define ASC_BIOS_MAX_ADDR	0xEC00
1165 #define ASC_BIOS_BANK_SIZE	0x0400
1166 
1167 #define ASC_MCODE_START_ADDR	0x0080
1168 
1169 #define ASC_CFG0_HOST_INT_ON	0x0020
1170 #define ASC_CFG0_BIOS_ON	0x0040
1171 #define ASC_CFG0_VERA_BURST_ON	0x0080
1172 #define ASC_CFG0_SCSI_PARITY_ON	0x0800
1173 #define ASC_CFG1_SCSI_TARGET_ON	0x0080
1174 #define ASC_CFG1_LRAM_8BITS_ON	0x0800
1175 #define ASC_CFG_MSW_CLR_MASK	0x3080
1176 
1177 #define ASC_CSW_TEST1			0x8000
1178 #define ASC_CSW_AUTO_CONFIG		0x4000
1179 #define ASC_CSW_RESERVED1		0x2000
1180 #define ASC_CSW_IRQ_WRITTEN		0x1000
1181 #define ASC_CSW_33MHZ_SELECTED		0x0800
1182 #define ASC_CSW_TEST2			0x0400
1183 #define ASC_CSW_TEST3			0x0200
1184 #define ASC_CSW_RESERVED2		0x0100
1185 #define ASC_CSW_DMA_DONE		0x0080
1186 #define ASC_CSW_FIFO_RDY		0x0040
1187 #define ASC_CSW_EEP_READ_DONE		0x0020
1188 #define ASC_CSW_HALTED			0x0010
1189 #define ASC_CSW_SCSI_RESET_ACTIVE	0x0008
1190 #define ASC_CSW_PARITY_ERR		0x0004
1191 #define ASC_CSW_SCSI_RESET_LATCH  	0x0002
1192 #define ASC_CSW_INT_PENDING		0x0001
1193 
1194 #define ASC_CIW_CLR_SCSI_RESET_INT	0x1000
1195 #define ASC_CIW_INT_ACK			0x0100
1196 #define ASC_CIW_TEST1			0x0200
1197 #define ASC_CIW_TEST2			0x0400
1198 #define ASC_CIW_SEL_33MHZ		0x0800
1199 #define ASC_CIW_IRQ_ACT			0x1000
1200 
1201 #define ASC_CC_CHIP_RESET	0x80
1202 #define ASC_CC_SCSI_RESET	0x40
1203 #define ASC_CC_HALT		0x20
1204 #define ASC_CC_SINGLE_STEP	0x10
1205 #define ASC_CC_DMA_ABLE		0x08
1206 #define ASC_CC_TEST		0x04
1207 #define ASC_CC_BANK_ONE		0x02
1208 #define ASC_CC_DIAG		0x01
1209 
1210 #define ASC_1000_ID0W		0x04C1
1211 #define ASC_1000_ID0W_FIX	0x00C1
1212 #define ASC_1000_ID1B		0x25
1213 
1214 #define ASC_EISA_BIG_IOP_GAP	(0x1C30-0x0C50)
1215 #define ASC_EISA_SMALL_IOP_GAP	(0x0020)
1216 #define ASC_EISA_MIN_IOP_ADDR	(0x0C30)
1217 #define ASC_EISA_MAX_IOP_ADDR	(0xFC50)
1218 #define ASC_EISA_REV_IOP_MASK	(0x0C83)
1219 #define ASC_EISA_PID_IOP_MASK	(0x0C80)
1220 #define ASC_EISA_CFG_IOP_MASK	(0x0C86)
1221 
1222 #define ASC_GET_EISA_SLOT(iop)	((iop) & 0xF000)
1223 
1224 #define ASC_EISA_ID_740	0x01745004UL
1225 #define ASC_EISA_ID_750	0x01755004UL
1226 
1227 #define ASC_INS_HALTINT		0x6281
1228 #define ASC_INS_HALT		0x6280
1229 #define ASC_INS_SINT		0x6200
1230 #define ASC_INS_RFLAG_WTM	0x7380
1231 
1232 
1233 /******************************************************************************/
1234 /*                                      Macro                                 */
1235 /******************************************************************************/
1236 
1237 /*
1238  * These Macros are used to deal with board CPU Registers and LRAM
1239  */
1240 
1241 #define ASC_GET_QDONE_IN_PROGRESS(iot, ioh)			AscReadLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B)
1242 #define ASC_PUT_QDONE_IN_PROGRESS(iot, ioh, val)		AscWriteLramByte((iot), (ioh), ASCV_Q_DONE_IN_PROGRESS_B, val)
1243 #define ASC_GET_VAR_FREE_QHEAD(iot, ioh)			AscReadLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W)
1244 #define ASC_GET_VAR_DONE_QTAIL(iot, ioh)			AscReadLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W)
1245 #define ASC_PUT_VAR_FREE_QHEAD(iot, ioh, val)			AscWriteLramWord((iot), (ioh), ASCV_FREE_Q_HEAD_W, val)
1246 #define ASC_PUT_VAR_DONE_QTAIL(iot, ioh, val)			AscWriteLramWord((iot), (ioh), ASCV_DONE_Q_TAIL_W, val)
1247 #define ASC_GET_RISC_VAR_FREE_QHEAD(iot, ioh)			AscReadLramByte((iot), (ioh), ASCV_NEXTRDY_B)
1248 #define ASC_GET_RISC_VAR_DONE_QTAIL(iot, ioh)			AscReadLramByte((iot), (ioh), ASCV_DONENEXT_B)
1249 #define ASC_PUT_RISC_VAR_FREE_QHEAD(iot, ioh, val)   		AscWriteLramByte((iot), (ioh), ASCV_NEXTRDY_B, val)
1250 #define ASC_PUT_RISC_VAR_DONE_QTAIL(iot, ioh, val)   		AscWriteLramByte((iot), (ioh), ASCV_DONENEXT_B, val)
1251 #define ASC_PUT_MCODE_SDTR_DONE_AT_ID(iot, ioh, id, data)	AscWriteLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DONE_BEG+(u_int16_t)id), (data)) ;
1252 #define ASC_GET_MCODE_SDTR_DONE_AT_ID(iot, ioh, id)		AscReadLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DONE_BEG+(u_int16_t)id)) ;
1253 #define ASC_PUT_MCODE_INIT_SDTR_AT_ID(iot, ioh, id, data)	AscWriteLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DATA_BEG+(u_int16_t)id), data) ;
1254 #define ASC_GET_MCODE_INIT_SDTR_AT_ID(iot, ioh, id)		AscReadLramByte((iot), (ioh), (u_int16_t)((u_int16_t)ASCV_SDTR_DATA_BEG+(u_int16_t)id)) ;
1255 #define ASC_SYN_INDEX_TO_PERIOD(sc, index)			(u_int8_t)((sc)->sdtr_period_tbl[ (index) ])
1256 #define ASC_GET_CHIP_SIGNATURE_BYTE(iot, ioh)			bus_space_read_1((iot), (ioh), ASC_IOP_SIG_BYTE)
1257 #define ASC_GET_CHIP_SIGNATURE_WORD(iot, ioh)			bus_space_read_2((iot), (ioh), ASC_IOP_SIG_WORD)
1258 #define ASC_GET_CHIP_VER_NO(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_VERSION)
1259 #define ASC_GET_CHIP_CFG_LSW(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_CONFIG_LOW)
1260 #define ASC_GET_CHIP_CFG_MSW(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_CONFIG_HIGH)
1261 #define ASC_SET_CHIP_CFG_LSW(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_CONFIG_LOW, data)
1262 #define ASC_SET_CHIP_CFG_MSW(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_CONFIG_HIGH, data)
1263 #define ASC_GET_CHIP_EEP_CMD(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_EEP_CMD)
1264 #define ASC_SET_CHIP_EEP_CMD(iot, ioh, data)			bus_space_write_1((iot), (ioh), ASC_IOP_EEP_CMD, data)
1265 #define ASC_GET_CHIP_EEP_DATA(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_EEP_DATA)
1266 #define ASC_SET_CHIP_EEP_DATA(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_EEP_DATA, data)
1267 #define ASC_GET_CHIP_LRAM_ADDR(iot, ioh)			bus_space_read_2((iot), (ioh), ASC_IOP_RAM_ADDR)
1268 #define ASC_SET_CHIP_LRAM_ADDR(iot, ioh, addr)			bus_space_write_2((iot), (ioh), ASC_IOP_RAM_ADDR, addr)
1269 #define ASC_GET_CHIP_LRAM_DATA(iot, ioh)			bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA)
1270 #define ASC_SET_CHIP_LRAM_DATA(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, data)
1271 #if BYTE_ORDER == BIG_ENDIAN
1272 #define ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh)		SWAPBYTES(bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA))
1273 #define ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, data)		bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, SWAPBYTES(data))
1274 #else
1275 #define ASC_GET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh)		bus_space_read_2((iot), (ioh), ASC_IOP_RAM_DATA)
1276 #define ASC_SET_CHIP_LRAM_DATA_NO_SWAP(iot, ioh, data)		bus_space_write_2((iot), (ioh), ASC_IOP_RAM_DATA, data)
1277 #endif
1278 #define ASC_GET_CHIP_IFC(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_REG_IFC)
1279 #define ASC_SET_CHIP_IFC(iot, ioh, data)			bus_space_write_1((iot), (ioh), ASC_IOP_REG_IFC, data)
1280 #define ASC_GET_CHIP_STATUS(iot, ioh)				(u_int16_t)bus_space_read_2((iot), (ioh), ASC_IOP_STATUS)
1281 #define ASC_SET_CHIP_STATUS(iot, ioh, cs_val)			bus_space_write_2((iot), (ioh), ASC_IOP_STATUS, cs_val)
1282 #define ASC_GET_CHIP_CONTROL(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_CTRL)
1283 #define ASC_SET_CHIP_CONTROL(iot, ioh, cc_val)			bus_space_write_1((iot), (ioh), ASC_IOP_CTRL, cc_val)
1284 #define ASC_GET_CHIP_SYN(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_SYN_OFFSET)
1285 #define ASC_SET_CHIP_SYN(iot, ioh, data)			bus_space_write_1((iot), (ioh), ASC_IOP_SYN_OFFSET, data)
1286 #define ASC_SET_PC_ADDR(iot, ioh, data)				bus_space_write_2((iot), (ioh), ASC_IOP_REG_PC, data)
1287 #define ASC_GET_PC_ADDR(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_PC)
1288 #define ASC_IS_INT_PENDING(iot, ioh)				(ASC_GET_CHIP_STATUS((iot), (ioh)) & (ASC_CSW_INT_PENDING | ASC_CSW_SCSI_RESET_LATCH))
1289 #define ASC_GET_CHIP_SCSI_ID(iot, ioh)				((ASC_GET_CHIP_CFG_LSW((iot), (ioh)) >> 8) & ASC_MAX_TID)
1290 #define ASC_GET_EXTRA_CONTROL(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_EXTRA_CONTROL)
1291 #define ASC_SET_EXTRA_CONTROL(iot, ioh, data)			bus_space_write_1((iot), (ioh), ASC_IOP_EXTRA_CONTROL, data)
1292 #define ASC_READ_CHIP_AX(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_AX)
1293 #define ASC_WRITE_CHIP_AX(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_REG_AX, data)
1294 #define ASC_READ_CHIP_IX(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_REG_IX)
1295 #define ASC_WRITE_CHIP_IX(iot, ioh, data)			bus_space_write_1((iot), (ioh), ASC_IOP_REG_IX, data)
1296 #define ASC_READ_CHIP_IH(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_IH)
1297 #define ASC_WRITE_CHIP_IH(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_REG_IH, data)
1298 #define ASC_READ_CHIP_QP(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_REG_QP)
1299 #define ASC_WRITE_CHIP_QP(iot, ioh, data)			bus_space_write_1((iot), (ioh), ASC_IOP_REG_QP, data)
1300 #define ASC_READ_CHIP_FIFO_L(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_FIFO_L)
1301 #define ASC_WRITE_CHIP_FIFO_L(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_REG_FIFO_L, data)
1302 #define ASC_READ_CHIP_FIFO_H(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_FIFO_H)
1303 #define ASC_WRITE_CHIP_FIFO_H(iot, ioh, data)			bus_space_write_2((iot), (ioh), ASC_IOP_REG_FIFO_H, data)
1304 #define ASC_READ_CHIP_DMA_SPEED(iot, ioh)			bus_space_read_1((iot), (ioh), ASC_IOP_DMA_SPEED)
1305 #define ASC_WRITE_CHIP_DMA_SPEED(iot, ioh, data)		bus_space_write_1((iot), (ioh), ASC_IOP_DMA_SPEED, data)
1306 #define ASC_READ_CHIP_DA0(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_DA0)
1307 #define ASC_WRITE_CHIP_DA0(iot, ioh)				bus_space_write_2((iot), (ioh), ASC_IOP_REG_DA0, data)
1308 #define ASC_READ_CHIP_DA1(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_DA1)
1309 #define ASC_WRITE_CHIP_DA1(iot, ioh)				bus_space_write_2((iot), (ioh), ASC_IOP_REG_DA1, data)
1310 #define ASC_READ_CHIP_DC0(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_DC0)
1311 #define ASC_WRITE_CHIP_DC0(iot, ioh)				bus_space_write_2((iot), (ioh), ASC_IOP_REG_DC0, data)
1312 #define ASC_READ_CHIP_DC1(iot, ioh)				bus_space_read_2((iot), (ioh), ASC_IOP_REG_DC1)
1313 #define ASC_WRITE_CHIP_DC1(iot, ioh)				bus_space_write_2((iot), (ioh), ASC_IOP_REG_DC1, data)
1314 #define ASC_READ_CHIP_DVC_ID(iot, ioh)				bus_space_read_1((iot), (ioh), ASC_IOP_REG_ID)
1315 #define ASC_WRITE_CHIP_DVC_ID(iot, ioh, data)			bus_space_write_1((iot), (ioh), ASC_IOP_REG_ID, data)
1316 
1317 
1318 /******************************************************************************/
1319 /*                                Exported functions                          */
1320 /******************************************************************************/
1321 
1322 
1323 void AscInitASC_SOFTC __P((ASC_SOFTC *));
1324 u_int16_t AscInitFromEEP __P((ASC_SOFTC *));
1325 u_int16_t AscInitFromASC_SOFTC __P((ASC_SOFTC *));
1326 int AscInitDriver __P((ASC_SOFTC *));
1327 void AscReInitLram __P((ASC_SOFTC *));
1328 int AscFindSignature __P((bus_space_tag_t, bus_space_handle_t));
1329 int AscISR __P((ASC_SOFTC *));
1330 int AscExeScsiQueue __P((ASC_SOFTC *, ASC_SCSI_Q *));
1331 void AscInquiryHandling __P((ASC_SOFTC *, u_int8_t, ASC_SCSI_INQUIRY *));
1332 int AscAbortCCB __P((ASC_SOFTC *, u_int32_t));
1333 int AscResetBus __P((ASC_SOFTC *));
1334 int AscResetDevice __P((ASC_SOFTC *, u_char));
1335 
1336 
1337 /******************************************************************************/
1338 #endif	/* _ADVANSYS_NARROW_LIBRARY_H_ */
1339