1 /* $NetBSD: hme.c,v 1.108 2020/03/12 03:01:46 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * HME Ethernet module driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.108 2020/03/12 03:01:46 thorpej Exp $"); 38 39 /* #define HMEDEBUG */ 40 41 #include "opt_inet.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/mbuf.h> 47 #include <sys/syslog.h> 48 #include <sys/socket.h> 49 #include <sys/device.h> 50 #include <sys/malloc.h> 51 #include <sys/ioctl.h> 52 #include <sys/errno.h> 53 #include <sys/rndsource.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_ether.h> 58 #include <net/if_media.h> 59 #include <net/bpf.h> 60 61 #ifdef INET 62 #include <net/if_vlanvar.h> 63 #include <netinet/in.h> 64 #include <netinet/if_inarp.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <sys/bus.h> 76 77 #include <dev/ic/hmereg.h> 78 #include <dev/ic/hmevar.h> 79 80 static void hme_start(struct ifnet *); 81 static void hme_stop(struct ifnet *, int); 82 static int hme_ioctl(struct ifnet *, u_long, void *); 83 static void hme_tick(void *); 84 static void hme_watchdog(struct ifnet *); 85 static bool hme_shutdown(device_t, int); 86 static int hme_init(struct ifnet *); 87 static void hme_meminit(struct hme_softc *); 88 static void hme_mifinit(struct hme_softc *); 89 static void hme_reset(struct hme_softc *); 90 static void hme_chipreset(struct hme_softc *); 91 static void hme_setladrf(struct hme_softc *); 92 93 /* MII methods & callbacks */ 94 static int hme_mii_readreg(device_t, int, int, uint16_t *); 95 static int hme_mii_writereg(device_t, int, int, uint16_t); 96 static void hme_mii_statchg(struct ifnet *); 97 98 static int hme_mediachange(struct ifnet *); 99 100 static struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 101 static int hme_put(struct hme_softc *, int, struct mbuf *); 102 static void hme_read(struct hme_softc *, int, uint32_t); 103 static int hme_eint(struct hme_softc *, u_int); 104 static int hme_rint(struct hme_softc *); 105 static int hme_tint(struct hme_softc *); 106 107 #if 0 108 /* Default buffer copy routines */ 109 static void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 110 static void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 111 #endif 112 113 void 114 hme_config(struct hme_softc *sc) 115 { 116 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 117 struct mii_data *mii = &sc->sc_mii; 118 struct mii_softc *child; 119 bus_dma_tag_t dmatag = sc->sc_dmatag; 120 bus_dma_segment_t seg; 121 bus_size_t size; 122 int rseg, error; 123 124 /* 125 * HME common initialization. 126 * 127 * hme_softc fields that must be initialized by the front-end: 128 * 129 * the bus tag: 130 * sc_bustag 131 * 132 * the DMA bus tag: 133 * sc_dmatag 134 * 135 * the bus handles: 136 * sc_seb (Shared Ethernet Block registers) 137 * sc_erx (Receiver Unit registers) 138 * sc_etx (Transmitter Unit registers) 139 * sc_mac (MAC registers) 140 * sc_mif (Management Interface registers) 141 * 142 * the maximum bus burst size: 143 * sc_burst 144 * 145 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 146 * rb_membase, rb_dmabase) 147 * 148 * the local Ethernet address: 149 * sc_enaddr 150 * 151 */ 152 153 /* Make sure the chip is stopped. */ 154 hme_chipreset(sc); 155 156 /* 157 * Allocate descriptors and buffers 158 * XXX - do all this differently.. and more configurably, 159 * eg. use things as `dma_load_mbuf()' on transmit, 160 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 161 * all the time) on the receiver side. 162 * 163 * Note: receive buffers must be 64-byte aligned. 164 * Also, apparently, the buffers must extend to a DMA burst 165 * boundary beyond the maximum packet size. 166 */ 167 #define _HME_NDESC 128 168 #define _HME_BUFSZ 1600 169 170 /* Note: the # of descriptors must be a multiple of 16 */ 171 sc->sc_rb.rb_ntbuf = _HME_NDESC; 172 sc->sc_rb.rb_nrbuf = _HME_NDESC; 173 174 /* 175 * Allocate DMA capable memory 176 * Buffer descriptors must be aligned on a 2048 byte boundary; 177 * take this into account when calculating the size. Note that 178 * the maximum number of descriptors (256) occupies 2048 bytes, 179 * so we allocate that much regardless of _HME_NDESC. 180 */ 181 size = 2048 + /* TX descriptors */ 182 2048 + /* RX descriptors */ 183 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 184 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 185 186 /* Allocate DMA buffer */ 187 if ((error = bus_dmamem_alloc(dmatag, size, 188 2048, 0, 189 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 190 aprint_error_dev(sc->sc_dev, "DMA buffer alloc error %d\n", 191 error); 192 return; 193 } 194 195 /* Map DMA memory in CPU addressable space */ 196 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 197 &sc->sc_rb.rb_membase, 198 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 199 aprint_error_dev(sc->sc_dev, "DMA buffer map error %d\n", 200 error); 201 bus_dmamap_unload(dmatag, sc->sc_dmamap); 202 bus_dmamem_free(dmatag, &seg, rseg); 203 return; 204 } 205 206 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 207 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 208 aprint_error_dev(sc->sc_dev, "DMA map create error %d\n", 209 error); 210 return; 211 } 212 213 /* Load the buffer */ 214 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 215 sc->sc_rb.rb_membase, size, NULL, 216 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 217 aprint_error_dev(sc->sc_dev, "DMA buffer map load error %d\n", 218 error); 219 bus_dmamem_free(dmatag, &seg, rseg); 220 return; 221 } 222 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 223 224 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 225 ether_sprintf(sc->sc_enaddr)); 226 227 /* Initialize ifnet structure. */ 228 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 229 ifp->if_softc = sc; 230 ifp->if_start = hme_start; 231 ifp->if_stop = hme_stop; 232 ifp->if_ioctl = hme_ioctl; 233 ifp->if_init = hme_init; 234 ifp->if_watchdog = hme_watchdog; 235 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 236 sc->sc_if_flags = ifp->if_flags; 237 ifp->if_capabilities |= 238 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 239 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 240 IFQ_SET_READY(&ifp->if_snd); 241 242 /* Initialize ifmedia structures and MII info */ 243 mii->mii_ifp = ifp; 244 mii->mii_readreg = hme_mii_readreg; 245 mii->mii_writereg = hme_mii_writereg; 246 mii->mii_statchg = hme_mii_statchg; 247 248 sc->sc_ethercom.ec_mii = mii; 249 ifmedia_init(&mii->mii_media, 0, hme_mediachange, ether_mediastatus); 250 251 hme_mifinit(sc); 252 253 mii_attach(sc->sc_dev, mii, 0xffffffff, 254 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 255 256 child = LIST_FIRST(&mii->mii_phys); 257 if (child == NULL) { 258 /* No PHY attached */ 259 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL); 260 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL); 261 } else { 262 /* 263 * Walk along the list of attached MII devices and 264 * establish an `MII instance' to `phy number' 265 * mapping. We'll use this mapping in media change 266 * requests to determine which phy to use to program 267 * the MIF configuration register. 268 */ 269 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 270 /* 271 * Note: we support just two PHYs: the built-in 272 * internal device and an external on the MII 273 * connector. 274 */ 275 if (child->mii_phy > 1 || child->mii_inst > 1) { 276 aprint_error_dev(sc->sc_dev, 277 "cannot accommodate MII device %s" 278 " at phy %d, instance %d\n", 279 device_xname(child->mii_dev), 280 child->mii_phy, child->mii_inst); 281 continue; 282 } 283 284 sc->sc_phys[child->mii_inst] = child->mii_phy; 285 } 286 287 /* 288 * Set the default media to auto negotiation if the phy has 289 * the auto negotiation capability. 290 * XXX; What to do otherwise? 291 */ 292 if (ifmedia_match(&mii->mii_media, IFM_ETHER | IFM_AUTO, 0)) 293 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 294 /* 295 else 296 ifmedia_set(&sc->sc_mii.mii_media, sc->sc_defaultmedia); 297 */ 298 } 299 300 /* claim 802.1q capability */ 301 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 302 303 /* Attach the interface. */ 304 if_attach(ifp); 305 if_deferred_start_init(ifp, NULL); 306 ether_ifattach(ifp, sc->sc_enaddr); 307 308 if (pmf_device_register1(sc->sc_dev, NULL, NULL, hme_shutdown)) 309 pmf_class_network_register(sc->sc_dev, ifp); 310 else 311 aprint_error_dev(sc->sc_dev, 312 "couldn't establish power handler\n"); 313 314 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 315 RND_TYPE_NET, RND_FLAG_DEFAULT); 316 317 callout_init(&sc->sc_tick_ch, 0); 318 callout_setfunc(&sc->sc_tick_ch, hme_tick, sc); 319 } 320 321 void 322 hme_tick(void *arg) 323 { 324 struct hme_softc *sc = arg; 325 int s; 326 327 s = splnet(); 328 mii_tick(&sc->sc_mii); 329 splx(s); 330 331 callout_schedule(&sc->sc_tick_ch, hz); 332 } 333 334 void 335 hme_reset(struct hme_softc *sc) 336 { 337 int s; 338 339 s = splnet(); 340 (void)hme_init(&sc->sc_ethercom.ec_if); 341 splx(s); 342 } 343 344 void 345 hme_chipreset(struct hme_softc *sc) 346 { 347 bus_space_tag_t t = sc->sc_bustag; 348 bus_space_handle_t seb = sc->sc_seb; 349 int n; 350 351 /* Mask all interrupts */ 352 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 353 354 /* Reset transmitter and receiver */ 355 bus_space_write_4(t, seb, HME_SEBI_RESET, 356 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 357 358 for (n = 0; n < 20; n++) { 359 uint32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 360 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 361 return; 362 DELAY(20); 363 } 364 365 printf("%s: %s: reset failed\n", device_xname(sc->sc_dev), __func__); 366 } 367 368 void 369 hme_stop(struct ifnet *ifp, int disable) 370 { 371 struct hme_softc *sc; 372 373 sc = ifp->if_softc; 374 375 ifp->if_timer = 0; 376 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 377 378 callout_stop(&sc->sc_tick_ch); 379 mii_down(&sc->sc_mii); 380 381 hme_chipreset(sc); 382 } 383 384 void 385 hme_meminit(struct hme_softc *sc) 386 { 387 bus_addr_t txbufdma, rxbufdma; 388 bus_addr_t dma; 389 char *p; 390 unsigned int ntbuf, nrbuf, i; 391 struct hme_ring *hr = &sc->sc_rb; 392 393 p = hr->rb_membase; 394 dma = hr->rb_dmabase; 395 396 ntbuf = hr->rb_ntbuf; 397 nrbuf = hr->rb_nrbuf; 398 399 /* 400 * Allocate transmit descriptors 401 */ 402 hr->rb_txd = p; 403 hr->rb_txddma = dma; 404 p += ntbuf * HME_XD_SIZE; 405 dma += ntbuf * HME_XD_SIZE; 406 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 407 dma = (bus_addr_t)roundup((u_long)dma, 2048); 408 p = (void *)roundup((u_long)p, 2048); 409 410 /* 411 * Allocate receive descriptors 412 */ 413 hr->rb_rxd = p; 414 hr->rb_rxddma = dma; 415 p += nrbuf * HME_XD_SIZE; 416 dma += nrbuf * HME_XD_SIZE; 417 /* Again move forward to the next 2048 byte boundary.*/ 418 dma = (bus_addr_t)roundup((u_long)dma, 2048); 419 p = (void *)roundup((u_long)p, 2048); 420 421 422 /* 423 * Allocate transmit buffers 424 */ 425 hr->rb_txbuf = p; 426 txbufdma = dma; 427 p += ntbuf * _HME_BUFSZ; 428 dma += ntbuf * _HME_BUFSZ; 429 430 /* 431 * Allocate receive buffers 432 */ 433 hr->rb_rxbuf = p; 434 rxbufdma = dma; 435 p += nrbuf * _HME_BUFSZ; 436 dma += nrbuf * _HME_BUFSZ; 437 438 /* 439 * Initialize transmit buffer descriptors 440 */ 441 for (i = 0; i < ntbuf; i++) { 442 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 443 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 444 } 445 446 /* 447 * Initialize receive buffer descriptors 448 */ 449 for (i = 0; i < nrbuf; i++) { 450 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 451 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 452 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 453 } 454 455 hr->rb_tdhead = hr->rb_tdtail = 0; 456 hr->rb_td_nbusy = 0; 457 hr->rb_rdtail = 0; 458 } 459 460 /* 461 * Initialization of interface; set up initialization block 462 * and transmit/receive descriptor rings. 463 */ 464 int 465 hme_init(struct ifnet *ifp) 466 { 467 struct hme_softc *sc = ifp->if_softc; 468 bus_space_tag_t t = sc->sc_bustag; 469 bus_space_handle_t seb = sc->sc_seb; 470 bus_space_handle_t etx = sc->sc_etx; 471 bus_space_handle_t erx = sc->sc_erx; 472 bus_space_handle_t mac = sc->sc_mac; 473 uint8_t *ea; 474 uint32_t v; 475 int rc; 476 477 /* 478 * Initialization sequence. The numbered steps below correspond 479 * to the sequence outlined in section 6.3.5.1 in the Ethernet 480 * Channel Engine manual (part of the PCIO manual). 481 * See also the STP2002-STQ document from Sun Microsystems. 482 */ 483 484 /* step 1 & 2. Reset the Ethernet Channel */ 485 hme_stop(ifp, 0); 486 487 /* Re-initialize the MIF */ 488 hme_mifinit(sc); 489 490 /* Call MI reset function if any */ 491 if (sc->sc_hwreset) 492 (*sc->sc_hwreset)(sc); 493 494 #if 0 495 /* Mask all MIF interrupts, just in case */ 496 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 497 #endif 498 499 /* step 3. Setup data structures in host memory */ 500 hme_meminit(sc); 501 502 /* step 4. TX MAC registers & counters */ 503 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 504 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 505 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 506 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 507 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 508 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 509 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 510 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 511 512 /* Load station MAC address */ 513 ea = sc->sc_enaddr; 514 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 515 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 516 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 517 518 /* 519 * Init seed for backoff 520 * (source suggested by manual: low 10 bits of MAC address) 521 */ 522 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 523 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 524 525 526 /* Note: Accepting power-on default for other MAC registers here.. */ 527 528 529 /* step 5. RX MAC registers & counters */ 530 hme_setladrf(sc); 531 532 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 533 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 534 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 535 536 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 537 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 538 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 539 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 540 541 /* step 8. Global Configuration & Interrupt Mask */ 542 bus_space_write_4(t, seb, HME_SEBI_IMASK, 543 ~( 544 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 545 HME_SEB_STAT_HOSTTOTX | 546 HME_SEB_STAT_RXTOHOST | 547 HME_SEB_STAT_TXALL | 548 HME_SEB_STAT_TXPERR | 549 HME_SEB_STAT_RCNTEXP | 550 HME_SEB_STAT_MIFIRQ | 551 HME_SEB_STAT_ALL_ERRORS )); 552 553 switch (sc->sc_burst) { 554 default: 555 v = 0; 556 break; 557 case 16: 558 v = HME_SEB_CFG_BURST16; 559 break; 560 case 32: 561 v = HME_SEB_CFG_BURST32; 562 break; 563 case 64: 564 v = HME_SEB_CFG_BURST64; 565 break; 566 } 567 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 568 569 /* step 9. ETX Configuration: use mostly default values */ 570 571 /* Enable DMA */ 572 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 573 v |= HME_ETX_CFG_DMAENABLE; 574 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 575 576 /* Transmit Descriptor ring size: in increments of 16 */ 577 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 578 579 580 /* step 10. ERX Configuration */ 581 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 582 583 /* Encode Receive Descriptor ring size: four possible values */ 584 switch (_HME_NDESC /*XXX*/) { 585 case 32: 586 v |= HME_ERX_CFG_RINGSIZE32; 587 break; 588 case 64: 589 v |= HME_ERX_CFG_RINGSIZE64; 590 break; 591 case 128: 592 v |= HME_ERX_CFG_RINGSIZE128; 593 break; 594 case 256: 595 v |= HME_ERX_CFG_RINGSIZE256; 596 break; 597 default: 598 printf("hme: invalid Receive Descriptor ring size\n"); 599 break; 600 } 601 602 /* Enable DMA */ 603 v |= HME_ERX_CFG_DMAENABLE; 604 605 /* set h/w rx checksum start offset (# of half-words) */ 606 #ifdef INET 607 v |= (((ETHER_HDR_LEN + sizeof(struct ip)) / sizeof(uint16_t)) 608 << HME_ERX_CFG_CSUMSHIFT) & 609 HME_ERX_CFG_CSUMSTART; 610 #endif 611 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 612 613 /* step 11. XIF Configuration */ 614 v = bus_space_read_4(t, mac, HME_MACI_XIF); 615 v |= HME_MAC_XIF_OE; 616 bus_space_write_4(t, mac, HME_MACI_XIF, v); 617 618 /* step 12. RX_MAC Configuration Register */ 619 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 620 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 621 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 622 623 /* step 13. TX_MAC Configuration Register */ 624 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 625 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 626 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 627 628 /* step 14. Issue Transmit Pending command */ 629 630 /* Call MI initialization function if any */ 631 if (sc->sc_hwinit) 632 (*sc->sc_hwinit)(sc); 633 634 /* Set the current media. */ 635 if ((rc = hme_mediachange(ifp)) != 0) 636 return rc; 637 638 /* Start the one second timer. */ 639 callout_schedule(&sc->sc_tick_ch, hz); 640 641 ifp->if_flags |= IFF_RUNNING; 642 ifp->if_flags &= ~IFF_OACTIVE; 643 sc->sc_if_flags = ifp->if_flags; 644 ifp->if_timer = 0; 645 hme_start(ifp); 646 return 0; 647 } 648 649 /* 650 * Routine to copy from mbuf chain to transmit buffer in 651 * network buffer memory. 652 * Returns the amount of data copied. 653 */ 654 int 655 hme_put(struct hme_softc *sc, int ri, struct mbuf *m) 656 /* ri: Ring index */ 657 { 658 struct mbuf *n; 659 int len, tlen = 0; 660 char *bp; 661 662 bp = (char *)sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 663 for (; m; m = n) { 664 len = m->m_len; 665 if (len == 0) { 666 n = m_free(m); 667 continue; 668 } 669 memcpy(bp, mtod(m, void *), len); 670 bp += len; 671 tlen += len; 672 n = m_free(m); 673 } 674 return (tlen); 675 } 676 677 /* 678 * Pull data off an interface. 679 * Len is length of data, with local net header stripped. 680 * We copy the data into mbufs. When full cluster sized units are present 681 * we copy into clusters. 682 */ 683 struct mbuf * 684 hme_get(struct hme_softc *sc, int ri, uint32_t flags) 685 { 686 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 687 struct mbuf *m, *m0, *newm; 688 char *bp; 689 int len, totlen; 690 #ifdef INET 691 int csum_flags; 692 #endif 693 694 totlen = HME_XD_DECODE_RSIZE(flags); 695 MGETHDR(m0, M_DONTWAIT, MT_DATA); 696 if (m0 == 0) 697 return (0); 698 MCLAIM(m0, &sc->sc_ethercom.ec_rx_mowner); 699 m_set_rcvif(m0, ifp); 700 m0->m_pkthdr.len = totlen; 701 len = MHLEN; 702 m = m0; 703 704 bp = (char *)sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 705 706 while (totlen > 0) { 707 if (totlen >= MINCLSIZE) { 708 MCLGET(m, M_DONTWAIT); 709 if ((m->m_flags & M_EXT) == 0) 710 goto bad; 711 len = MCLBYTES; 712 } 713 714 if (m == m0) { 715 char *newdata = (char *) 716 ALIGN(m->m_data + sizeof(struct ether_header)) - 717 sizeof(struct ether_header); 718 len -= newdata - m->m_data; 719 m->m_data = newdata; 720 } 721 722 m->m_len = len = uimin(totlen, len); 723 memcpy(mtod(m, void *), bp, len); 724 bp += len; 725 726 totlen -= len; 727 if (totlen > 0) { 728 MGET(newm, M_DONTWAIT, MT_DATA); 729 if (newm == 0) 730 goto bad; 731 len = MLEN; 732 m = m->m_next = newm; 733 } 734 } 735 736 #ifdef INET 737 /* hardware checksum */ 738 csum_flags = 0; 739 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 740 struct ether_header *eh; 741 struct ether_vlan_header *evh; 742 struct ip *ip; 743 struct udphdr *uh; 744 uint16_t *opts; 745 int32_t hlen, pktlen; 746 uint32_t csum_data; 747 748 eh = mtod(m0, struct ether_header *); 749 if (ntohs(eh->ether_type) == ETHERTYPE_IP) { 750 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN); 751 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 752 } else if (ntohs(eh->ether_type) == ETHERTYPE_VLAN) { 753 evh = (struct ether_vlan_header *)eh; 754 if (ntohs(evh->evl_proto) != ETHERTYPE_IP) 755 goto swcsum; 756 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN + 757 ETHER_VLAN_ENCAP_LEN); 758 pktlen = m0->m_pkthdr.len - 759 ETHER_HDR_LEN - ETHER_VLAN_ENCAP_LEN; 760 } else 761 goto swcsum; 762 763 /* IPv4 only */ 764 if (ip->ip_v != IPVERSION) 765 goto swcsum; 766 767 hlen = ip->ip_hl << 2; 768 if (hlen < sizeof(struct ip)) 769 goto swcsum; 770 771 /* 772 * bail if too short, has random trailing garbage, truncated, 773 * fragment, or has ethernet pad. 774 */ 775 if (ntohs(ip->ip_len) < hlen || 776 ntohs(ip->ip_len) != pktlen || 777 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 778 goto swcsum; 779 780 switch (ip->ip_p) { 781 case IPPROTO_TCP: 782 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0) 783 goto swcsum; 784 if (pktlen < (hlen + sizeof(struct tcphdr))) 785 goto swcsum; 786 csum_flags = 787 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 788 break; 789 case IPPROTO_UDP: 790 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0) 791 goto swcsum; 792 if (pktlen < (hlen + sizeof(struct udphdr))) 793 goto swcsum; 794 uh = (struct udphdr *)((char *)ip + hlen); 795 /* no checksum */ 796 if (uh->uh_sum == 0) 797 goto swcsum; 798 csum_flags = 799 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 800 break; 801 default: 802 goto swcsum; 803 } 804 805 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 806 csum_data = ~flags & HME_XD_RXCKSUM; 807 808 /* 809 * If data offset is different from RX cksum start offset, 810 * we have to deduct them. 811 */ 812 hlen = ((char *)ip + hlen) - 813 ((char *)eh + ETHER_HDR_LEN + sizeof(struct ip)); 814 if (hlen > 1) { 815 uint32_t optsum; 816 817 optsum = 0; 818 opts = (uint16_t *)((char *)eh + 819 ETHER_HDR_LEN + sizeof(struct ip)); 820 821 while (hlen > 1) { 822 optsum += ntohs(*opts++); 823 hlen -= 2; 824 } 825 while (optsum >> 16) 826 optsum = (optsum >> 16) + (optsum & 0xffff); 827 828 /* Deduct the ip opts sum from the hwsum. */ 829 csum_data += (uint16_t)~optsum; 830 831 while (csum_data >> 16) 832 csum_data = 833 (csum_data >> 16) + (csum_data & 0xffff); 834 } 835 m0->m_pkthdr.csum_data = csum_data; 836 } 837 swcsum: 838 m0->m_pkthdr.csum_flags = csum_flags; 839 #endif 840 841 return (m0); 842 843 bad: 844 m_freem(m0); 845 return (0); 846 } 847 848 /* 849 * Pass a packet to the higher levels. 850 */ 851 void 852 hme_read(struct hme_softc *sc, int ix, uint32_t flags) 853 { 854 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 855 struct mbuf *m; 856 int len; 857 858 len = HME_XD_DECODE_RSIZE(flags); 859 if (len <= sizeof(struct ether_header) || 860 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 861 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 862 ETHERMTU + sizeof(struct ether_header))) { 863 #ifdef HMEDEBUG 864 printf("%s: invalid packet size %d; dropping\n", 865 device_xname(sc->sc_dev), len); 866 #endif 867 if_statinc(ifp, if_ierrors); 868 return; 869 } 870 871 /* Pull packet off interface. */ 872 m = hme_get(sc, ix, flags); 873 if (m == 0) { 874 if_statinc(ifp, if_ierrors); 875 return; 876 } 877 878 /* Pass the packet up. */ 879 if_percpuq_enqueue(ifp->if_percpuq, m); 880 } 881 882 void 883 hme_start(struct ifnet *ifp) 884 { 885 struct hme_softc *sc = ifp->if_softc; 886 void *txd = sc->sc_rb.rb_txd; 887 struct mbuf *m; 888 unsigned int txflags; 889 unsigned int ri, len, obusy; 890 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 891 892 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 893 return; 894 895 ri = sc->sc_rb.rb_tdhead; 896 obusy = sc->sc_rb.rb_td_nbusy; 897 898 for (;;) { 899 IFQ_DEQUEUE(&ifp->if_snd, m); 900 if (m == 0) 901 break; 902 903 /* 904 * If BPF is listening on this interface, let it see the 905 * packet before we commit it to the wire. 906 */ 907 bpf_mtap(ifp, m, BPF_D_OUT); 908 909 #ifdef INET 910 /* collect bits for h/w csum, before hme_put frees the mbuf */ 911 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 912 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 913 struct ether_header *eh; 914 uint16_t offset, start; 915 916 eh = mtod(m, struct ether_header *); 917 switch (ntohs(eh->ether_type)) { 918 case ETHERTYPE_IP: 919 start = ETHER_HDR_LEN; 920 break; 921 case ETHERTYPE_VLAN: 922 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 923 break; 924 default: 925 /* unsupported, drop it */ 926 m_free(m); 927 continue; 928 } 929 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 930 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 931 + start; 932 txflags = HME_XD_TXCKSUM | 933 (offset << HME_XD_TXCSSTUFFSHIFT) | 934 (start << HME_XD_TXCSSTARTSHIFT); 935 } else 936 #endif 937 txflags = 0; 938 939 /* 940 * Copy the mbuf chain into the transmit buffer. 941 */ 942 len = hme_put(sc, ri, m); 943 944 /* 945 * Initialize transmit registers and start transmission 946 */ 947 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 948 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 949 HME_XD_ENCODE_TSIZE(len) | txflags); 950 951 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 952 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 953 HME_ETX_TP_DMAWAKEUP); 954 955 if (++ri == ntbuf) 956 ri = 0; 957 958 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 959 ifp->if_flags |= IFF_OACTIVE; 960 break; 961 } 962 } 963 964 if (obusy != sc->sc_rb.rb_td_nbusy) { 965 sc->sc_rb.rb_tdhead = ri; 966 ifp->if_timer = 5; 967 } 968 } 969 970 /* 971 * Transmit interrupt. 972 */ 973 int 974 hme_tint(struct hme_softc *sc) 975 { 976 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 977 bus_space_tag_t t = sc->sc_bustag; 978 bus_space_handle_t mac = sc->sc_mac; 979 unsigned int ri, txflags; 980 981 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 982 983 /* 984 * Unload collision counters 985 */ 986 if_statadd_ref(nsr, if_collisions, 987 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 988 bus_space_read_4(t, mac, HME_MACI_FCCNT)); 989 if_statadd_ref(nsr, if_oerrors, 990 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 991 bus_space_read_4(t, mac, HME_MACI_LTCNT)); 992 993 /* 994 * then clear the hardware counters. 995 */ 996 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 997 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 998 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 999 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 1000 1001 /* Fetch current position in the transmit ring */ 1002 ri = sc->sc_rb.rb_tdtail; 1003 1004 for (;;) { 1005 if (sc->sc_rb.rb_td_nbusy <= 0) 1006 break; 1007 1008 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 1009 1010 if (txflags & HME_XD_OWN) 1011 break; 1012 1013 ifp->if_flags &= ~IFF_OACTIVE; 1014 if_statinc_ref(nsr, if_opackets); 1015 1016 if (++ri == sc->sc_rb.rb_ntbuf) 1017 ri = 0; 1018 1019 --sc->sc_rb.rb_td_nbusy; 1020 } 1021 1022 IF_STAT_PUTREF(ifp); 1023 1024 /* Update ring */ 1025 sc->sc_rb.rb_tdtail = ri; 1026 1027 if_schedule_deferred_start(ifp); 1028 1029 if (sc->sc_rb.rb_td_nbusy == 0) 1030 ifp->if_timer = 0; 1031 1032 return (1); 1033 } 1034 1035 /* 1036 * Receive interrupt. 1037 */ 1038 int 1039 hme_rint(struct hme_softc *sc) 1040 { 1041 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1042 bus_space_tag_t t = sc->sc_bustag; 1043 bus_space_handle_t mac = sc->sc_mac; 1044 void *xdr = sc->sc_rb.rb_rxd; 1045 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1046 unsigned int ri; 1047 uint32_t flags; 1048 1049 ri = sc->sc_rb.rb_rdtail; 1050 1051 /* 1052 * Process all buffers with valid data. 1053 */ 1054 for (;;) { 1055 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1056 if (flags & HME_XD_OWN) 1057 break; 1058 1059 if (flags & HME_XD_OFL) { 1060 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1061 device_xname(sc->sc_dev), ri, flags); 1062 } else 1063 hme_read(sc, ri, flags); 1064 1065 /* This buffer can be used by the hardware again */ 1066 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1067 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1068 1069 if (++ri == nrbuf) 1070 ri = 0; 1071 } 1072 1073 sc->sc_rb.rb_rdtail = ri; 1074 1075 /* Read error counters ... */ 1076 if_statadd(ifp, if_ierrors, 1077 bus_space_read_4(t, mac, HME_MACI_STAT_LCNT) + 1078 bus_space_read_4(t, mac, HME_MACI_STAT_ACNT) + 1079 bus_space_read_4(t, mac, HME_MACI_STAT_CCNT) + 1080 bus_space_read_4(t, mac, HME_MACI_STAT_CVCNT)); 1081 1082 /* ... then clear the hardware counters. */ 1083 bus_space_write_4(t, mac, HME_MACI_STAT_LCNT, 0); 1084 bus_space_write_4(t, mac, HME_MACI_STAT_ACNT, 0); 1085 bus_space_write_4(t, mac, HME_MACI_STAT_CCNT, 0); 1086 bus_space_write_4(t, mac, HME_MACI_STAT_CVCNT, 0); 1087 return (1); 1088 } 1089 1090 int 1091 hme_eint(struct hme_softc *sc, u_int status) 1092 { 1093 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1094 char bits[128]; 1095 1096 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1097 bus_space_tag_t t = sc->sc_bustag; 1098 bus_space_handle_t mif = sc->sc_mif; 1099 uint32_t cf, st, sm; 1100 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1101 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1102 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1103 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1104 device_xname(sc->sc_dev), cf, st, sm); 1105 return (1); 1106 } 1107 1108 /* Receive error counters rolled over */ 1109 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1110 if (status & HME_SEB_STAT_ACNTEXP) 1111 if_statadd_ref(nsr, if_ierrors, 0xff); 1112 if (status & HME_SEB_STAT_CCNTEXP) 1113 if_statadd_ref(nsr, if_ierrors, 0xff); 1114 if (status & HME_SEB_STAT_LCNTEXP) 1115 if_statadd_ref(nsr, if_ierrors, 0xff); 1116 if (status & HME_SEB_STAT_CVCNTEXP) 1117 if_statadd_ref(nsr, if_ierrors, 0xff); 1118 IF_STAT_PUTREF(ifp); 1119 1120 /* RXTERR locks up the interface, so do a reset */ 1121 if (status & HME_SEB_STAT_RXTERR) 1122 hme_reset(sc); 1123 1124 snprintb(bits, sizeof(bits), HME_SEB_STAT_BITS, status); 1125 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1126 1127 return (1); 1128 } 1129 1130 int 1131 hme_intr(void *v) 1132 { 1133 struct hme_softc *sc = v; 1134 bus_space_tag_t t = sc->sc_bustag; 1135 bus_space_handle_t seb = sc->sc_seb; 1136 uint32_t status; 1137 int r = 0; 1138 1139 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1140 1141 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1142 r |= hme_eint(sc, status); 1143 1144 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1145 r |= hme_tint(sc); 1146 1147 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1148 r |= hme_rint(sc); 1149 1150 rnd_add_uint32(&sc->rnd_source, status); 1151 1152 return (r); 1153 } 1154 1155 1156 void 1157 hme_watchdog(struct ifnet *ifp) 1158 { 1159 struct hme_softc *sc = ifp->if_softc; 1160 1161 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1162 if_statinc(ifp, if_oerrors); 1163 1164 hme_reset(sc); 1165 } 1166 1167 /* 1168 * Initialize the MII Management Interface 1169 */ 1170 void 1171 hme_mifinit(struct hme_softc *sc) 1172 { 1173 bus_space_tag_t t = sc->sc_bustag; 1174 bus_space_handle_t mif = sc->sc_mif; 1175 bus_space_handle_t mac = sc->sc_mac; 1176 int instance, phy; 1177 uint32_t v; 1178 1179 if (sc->sc_mii.mii_media.ifm_cur != NULL) { 1180 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1181 phy = sc->sc_phys[instance]; 1182 } else 1183 /* No media set yet, pick phy arbitrarily.. */ 1184 phy = HME_PHYAD_EXTERNAL; 1185 1186 /* Configure the MIF in frame mode, no poll, current phy select */ 1187 v = 0; 1188 if (phy == HME_PHYAD_EXTERNAL) 1189 v |= HME_MIF_CFG_PHY; 1190 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1191 1192 /* If an external transceiver is selected, enable its MII drivers */ 1193 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1194 v &= ~HME_MAC_XIF_MIIENABLE; 1195 if (phy == HME_PHYAD_EXTERNAL) 1196 v |= HME_MAC_XIF_MIIENABLE; 1197 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1198 } 1199 1200 /* 1201 * MII interface 1202 */ 1203 static int 1204 hme_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1205 { 1206 struct hme_softc *sc = device_private(self); 1207 bus_space_tag_t t = sc->sc_bustag; 1208 bus_space_handle_t mif = sc->sc_mif; 1209 bus_space_handle_t mac = sc->sc_mac; 1210 uint32_t v, xif_cfg, mifi_cfg; 1211 int n, rv; 1212 1213 /* We can at most have two PHYs */ 1214 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1215 return -1; 1216 1217 /* Select the desired PHY in the MIF configuration register */ 1218 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1219 v &= ~HME_MIF_CFG_PHY; 1220 if (phy == HME_PHYAD_EXTERNAL) 1221 v |= HME_MIF_CFG_PHY; 1222 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1223 1224 /* Enable MII drivers on external transceiver */ 1225 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1226 if (phy == HME_PHYAD_EXTERNAL) 1227 v |= HME_MAC_XIF_MIIENABLE; 1228 else 1229 v &= ~HME_MAC_XIF_MIIENABLE; 1230 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1231 1232 #if 0 1233 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1234 /* 1235 * Check whether a transceiver is connected by testing 1236 * the MIF configuration register's MDI_X bits. Note that 1237 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1238 */ 1239 mif_mdi_bit = 1 << (8 + (1 - phy)); 1240 delay(100); 1241 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1242 if ((v & mif_mdi_bit) == 0) { 1243 rv = -1; 1244 goto out; 1245 } 1246 #endif 1247 1248 /* Construct the frame command */ 1249 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1250 HME_MIF_FO_TAMSB | 1251 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1252 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1253 (reg << HME_MIF_FO_REGAD_SHIFT); 1254 1255 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1256 for (n = 0; n < 100; n++) { 1257 DELAY(1); 1258 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1259 if (v & HME_MIF_FO_TALSB) { 1260 *val = v & HME_MIF_FO_DATA; 1261 rv = 0; 1262 goto out; 1263 } 1264 } 1265 1266 rv = ETIMEDOUT; 1267 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1268 1269 out: 1270 /* Restore MIFI_CFG register */ 1271 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1272 /* Restore XIF register */ 1273 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1274 return rv; 1275 } 1276 1277 static int 1278 hme_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1279 { 1280 struct hme_softc *sc = device_private(self); 1281 bus_space_tag_t t = sc->sc_bustag; 1282 bus_space_handle_t mif = sc->sc_mif; 1283 bus_space_handle_t mac = sc->sc_mac; 1284 uint32_t v, xif_cfg, mifi_cfg; 1285 int n, rv; 1286 1287 /* We can at most have two PHYs */ 1288 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1289 return -1; 1290 1291 /* Select the desired PHY in the MIF configuration register */ 1292 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1293 v &= ~HME_MIF_CFG_PHY; 1294 if (phy == HME_PHYAD_EXTERNAL) 1295 v |= HME_MIF_CFG_PHY; 1296 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1297 1298 /* Enable MII drivers on external transceiver */ 1299 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1300 if (phy == HME_PHYAD_EXTERNAL) 1301 v |= HME_MAC_XIF_MIIENABLE; 1302 else 1303 v &= ~HME_MAC_XIF_MIIENABLE; 1304 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1305 1306 #if 0 1307 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1308 /* 1309 * Check whether a transceiver is connected by testing 1310 * the MIF configuration register's MDI_X bits. Note that 1311 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1312 */ 1313 mif_mdi_bit = 1 << (8 + (1 - phy)); 1314 delay(100); 1315 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1316 if ((v & mif_mdi_bit) == 0) { 1317 rv = -1; 1318 goto out; 1319 } 1320 #endif 1321 1322 /* Construct the frame command */ 1323 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1324 HME_MIF_FO_TAMSB | 1325 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1326 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1327 (reg << HME_MIF_FO_REGAD_SHIFT) | 1328 (val & HME_MIF_FO_DATA); 1329 1330 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1331 for (n = 0; n < 100; n++) { 1332 DELAY(1); 1333 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1334 if (v & HME_MIF_FO_TALSB) { 1335 rv = 0; 1336 goto out; 1337 } 1338 } 1339 1340 rv = ETIMEDOUT; 1341 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1342 out: 1343 /* Restore MIFI_CFG register */ 1344 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1345 /* Restore XIF register */ 1346 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1347 1348 return rv; 1349 } 1350 1351 static void 1352 hme_mii_statchg(struct ifnet *ifp) 1353 { 1354 struct hme_softc *sc = ifp->if_softc; 1355 bus_space_tag_t t = sc->sc_bustag; 1356 bus_space_handle_t mac = sc->sc_mac; 1357 uint32_t v; 1358 1359 #ifdef HMEDEBUG 1360 if (sc->sc_debug) 1361 printf("hme_mii_statchg: status change\n"); 1362 #endif 1363 1364 /* Set the MAC Full Duplex bit appropriately */ 1365 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1366 but not otherwise. */ 1367 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1368 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1369 v |= HME_MAC_TXCFG_FULLDPLX; 1370 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1371 } else { 1372 v &= ~HME_MAC_TXCFG_FULLDPLX; 1373 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1374 } 1375 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1376 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1377 } 1378 1379 int 1380 hme_mediachange(struct ifnet *ifp) 1381 { 1382 struct hme_softc *sc = ifp->if_softc; 1383 bus_space_tag_t t = sc->sc_bustag; 1384 bus_space_handle_t mif = sc->sc_mif; 1385 bus_space_handle_t mac = sc->sc_mac; 1386 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1387 int phy = sc->sc_phys[instance]; 1388 int rc; 1389 uint32_t v; 1390 1391 #ifdef HMEDEBUG 1392 if (sc->sc_debug) 1393 printf("hme_mediachange: phy = %d\n", phy); 1394 #endif 1395 1396 /* Select the current PHY in the MIF configuration register */ 1397 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1398 v &= ~HME_MIF_CFG_PHY; 1399 if (phy == HME_PHYAD_EXTERNAL) 1400 v |= HME_MIF_CFG_PHY; 1401 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1402 1403 /* If an external transceiver is selected, enable its MII drivers */ 1404 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1405 v &= ~HME_MAC_XIF_MIIENABLE; 1406 if (phy == HME_PHYAD_EXTERNAL) 1407 v |= HME_MAC_XIF_MIIENABLE; 1408 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1409 1410 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 1411 return 0; 1412 return rc; 1413 } 1414 1415 /* 1416 * Process an ioctl request. 1417 */ 1418 int 1419 hme_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1420 { 1421 struct hme_softc *sc = ifp->if_softc; 1422 struct ifaddr *ifa = (struct ifaddr *)data; 1423 int s, error = 0; 1424 1425 s = splnet(); 1426 1427 switch (cmd) { 1428 1429 case SIOCINITIFADDR: 1430 switch (ifa->ifa_addr->sa_family) { 1431 #ifdef INET 1432 case AF_INET: 1433 if (ifp->if_flags & IFF_UP) 1434 hme_setladrf(sc); 1435 else { 1436 ifp->if_flags |= IFF_UP; 1437 error = hme_init(ifp); 1438 } 1439 arp_ifinit(ifp, ifa); 1440 break; 1441 #endif 1442 default: 1443 ifp->if_flags |= IFF_UP; 1444 error = hme_init(ifp); 1445 break; 1446 } 1447 break; 1448 1449 case SIOCSIFFLAGS: 1450 #ifdef HMEDEBUG 1451 { 1452 struct ifreq *ifr = data; 1453 sc->sc_debug = 1454 (ifr->ifr_flags & IFF_DEBUG) != 0 ? 1 : 0; 1455 } 1456 #endif 1457 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1458 break; 1459 1460 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { 1461 case IFF_RUNNING: 1462 /* 1463 * If interface is marked down and it is running, then 1464 * stop it. 1465 */ 1466 hme_stop(ifp, 0); 1467 ifp->if_flags &= ~IFF_RUNNING; 1468 break; 1469 case IFF_UP: 1470 /* 1471 * If interface is marked up and it is stopped, then 1472 * start it. 1473 */ 1474 error = hme_init(ifp); 1475 break; 1476 case IFF_UP | IFF_RUNNING: 1477 /* 1478 * If setting debug or promiscuous mode, do not reset 1479 * the chip; for everything else, call hme_init() 1480 * which will trigger a reset. 1481 */ 1482 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1483 if (ifp->if_flags != sc->sc_if_flags) { 1484 if ((ifp->if_flags & (~RESETIGN)) 1485 == (sc->sc_if_flags & (~RESETIGN))) 1486 hme_setladrf(sc); 1487 else 1488 error = hme_init(ifp); 1489 } 1490 #undef RESETIGN 1491 break; 1492 case 0: 1493 break; 1494 } 1495 1496 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1497 error = hme_init(ifp); 1498 1499 break; 1500 1501 default: 1502 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1503 break; 1504 1505 error = 0; 1506 1507 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1508 ; 1509 else if (ifp->if_flags & IFF_RUNNING) { 1510 /* 1511 * Multicast list has changed; set the hardware filter 1512 * accordingly. 1513 */ 1514 hme_setladrf(sc); 1515 } 1516 break; 1517 } 1518 1519 sc->sc_if_flags = ifp->if_flags; 1520 splx(s); 1521 return (error); 1522 } 1523 1524 bool 1525 hme_shutdown(device_t self, int howto) 1526 { 1527 struct hme_softc *sc; 1528 struct ifnet *ifp; 1529 1530 sc = device_private(self); 1531 ifp = &sc->sc_ethercom.ec_if; 1532 hme_stop(ifp, 1); 1533 1534 return true; 1535 } 1536 1537 /* 1538 * Set up the logical address filter. 1539 */ 1540 void 1541 hme_setladrf(struct hme_softc *sc) 1542 { 1543 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1544 struct ether_multi *enm; 1545 struct ether_multistep step; 1546 struct ethercom *ec = &sc->sc_ethercom; 1547 bus_space_tag_t t = sc->sc_bustag; 1548 bus_space_handle_t mac = sc->sc_mac; 1549 uint32_t v; 1550 uint32_t crc; 1551 uint32_t hash[4]; 1552 1553 /* Clear hash table */ 1554 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1555 1556 /* Get current RX configuration */ 1557 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1558 1559 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1560 /* Turn on promiscuous mode; turn off the hash filter */ 1561 v |= HME_MAC_RXCFG_PMISC; 1562 v &= ~HME_MAC_RXCFG_HENABLE; 1563 ifp->if_flags |= IFF_ALLMULTI; 1564 goto chipit; 1565 } 1566 1567 /* Turn off promiscuous mode; turn on the hash filter */ 1568 v &= ~HME_MAC_RXCFG_PMISC; 1569 v |= HME_MAC_RXCFG_HENABLE; 1570 1571 /* 1572 * Set up multicast address filter by passing all multicast addresses 1573 * through a crc generator, and then using the high order 6 bits as an 1574 * index into the 64 bit logical address filter. The high order bit 1575 * selects the word, while the rest of the bits select the bit within 1576 * the word. 1577 */ 1578 1579 ETHER_LOCK(ec); 1580 ETHER_FIRST_MULTI(step, ec, enm); 1581 while (enm != NULL) { 1582 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1583 /* 1584 * We must listen to a range of multicast addresses. 1585 * For now, just accept all multicasts, rather than 1586 * trying to set only those filter bits needed to match 1587 * the range. (At this time, the only use of address 1588 * ranges is for IP multicast routing, for which the 1589 * range is big enough to require all bits set.) 1590 */ 1591 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1592 ifp->if_flags |= IFF_ALLMULTI; 1593 ETHER_UNLOCK(ec); 1594 goto chipit; 1595 } 1596 1597 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1598 1599 /* Just want the 6 most significant bits. */ 1600 crc >>= 26; 1601 1602 /* Set the corresponding bit in the filter. */ 1603 hash[crc >> 4] |= 1 << (crc & 0xf); 1604 1605 ETHER_NEXT_MULTI(step, enm); 1606 } 1607 ETHER_UNLOCK(ec); 1608 1609 ifp->if_flags &= ~IFF_ALLMULTI; 1610 1611 chipit: 1612 /* Now load the hash table into the chip */ 1613 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1614 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1615 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1616 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1617 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1618 } 1619 1620 /* 1621 * Routines for accessing the transmit and receive buffers. 1622 * The various CPU and adapter configurations supported by this 1623 * driver require three different access methods for buffers 1624 * and descriptors: 1625 * (1) contig (contiguous data; no padding), 1626 * (2) gap2 (two bytes of data followed by two bytes of padding), 1627 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1628 */ 1629 1630 #if 0 1631 /* 1632 * contig: contiguous data with no padding. 1633 * 1634 * Buffers may have any alignment. 1635 */ 1636 1637 void 1638 hme_copytobuf_contig(struct hme_softc *sc, void *from, int ri, int len) 1639 { 1640 volatile void *buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1641 1642 /* 1643 * Just call memcpy() to do the work. 1644 */ 1645 memcpy(buf, from, len); 1646 } 1647 1648 void 1649 hme_copyfrombuf_contig(struct hme_softc *sc, void *to, int boff, int len) 1650 { 1651 volatile void *buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1652 1653 /* 1654 * Just call memcpy() to do the work. 1655 */ 1656 memcpy(to, buf, len); 1657 } 1658 #endif 1659