1*89b627d4Sriastradh /* $NetBSD: ubsecreg.h,v 1.5 2015/04/13 15:43:43 riastradh Exp $ */ 2d07a32c1Sbad /* $OpenBSD: ubsecreg.h,v 1.29 2009/03/25 12:17:30 reyk Exp $ */ 33d768ff8Sjonathan 43d768ff8Sjonathan /* 53d768ff8Sjonathan * Copyright (c) 2000 Theo de Raadt 63d768ff8Sjonathan * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 73d768ff8Sjonathan * 83d768ff8Sjonathan * Redistribution and use in source and binary forms, with or without 93d768ff8Sjonathan * modification, are permitted provided that the following conditions 103d768ff8Sjonathan * are met: 113d768ff8Sjonathan * 123d768ff8Sjonathan * 1. Redistributions of source code must retain the above copyright 133d768ff8Sjonathan * notice, this list of conditions and the following disclaimer. 143d768ff8Sjonathan * 2. Redistributions in binary form must reproduce the above copyright 153d768ff8Sjonathan * notice, this list of conditions and the following disclaimer in the 163d768ff8Sjonathan * documentation and/or other materials provided with the distribution. 173d768ff8Sjonathan * 183d768ff8Sjonathan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 193d768ff8Sjonathan * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 203d768ff8Sjonathan * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 213d768ff8Sjonathan * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 223d768ff8Sjonathan * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 233d768ff8Sjonathan * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 243d768ff8Sjonathan * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 253d768ff8Sjonathan * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 263d768ff8Sjonathan * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 273d768ff8Sjonathan * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 283d768ff8Sjonathan * 293d768ff8Sjonathan * Effort sponsored in part by the Defense Advanced Research Projects 303d768ff8Sjonathan * Agency (DARPA) and Air Force Research Laboratory, Air Force 313d768ff8Sjonathan * Materiel Command, USAF, under agreement number F30602-01-2-0537. 323d768ff8Sjonathan * 333d768ff8Sjonathan */ 343d768ff8Sjonathan 35*89b627d4Sriastradh #ifndef _DEV_PCI_UBSECREG_H 36*89b627d4Sriastradh #define _DEV_PCI_UBSECREG_H 37*89b627d4Sriastradh 383d768ff8Sjonathan /* 393d768ff8Sjonathan * Register definitions for 5601 BlueSteel Networks Ubiquitous Broadband 403d768ff8Sjonathan * Security "uBSec" chip. Definitions from revision 2.8 of the product 413d768ff8Sjonathan * datasheet. 423d768ff8Sjonathan */ 433d768ff8Sjonathan 443d768ff8Sjonathan #define BS_BAR 0x10 /* DMA base address register */ 453d768ff8Sjonathan #define BS_TRDY_TIMEOUT 0x40 /* TRDY timeout */ 463d768ff8Sjonathan #define BS_RETRY_TIMEOUT 0x41 /* DMA retry timeout */ 473d768ff8Sjonathan 483d768ff8Sjonathan #define UBS_PCI_RTY_SHIFT 8 493d768ff8Sjonathan #define UBS_PCI_RTY_MASK 0xff 503d768ff8Sjonathan #define UBS_PCI_RTY(misc) \ 513d768ff8Sjonathan (((misc) >> UBS_PCI_RTY_SHIFT) & UBS_PCI_RTY_MASK) 523d768ff8Sjonathan 533d768ff8Sjonathan #define UBS_PCI_TOUT_SHIFT 0 543d768ff8Sjonathan #define UBS_PCI_TOUT_MASK 0xff 553d768ff8Sjonathan #define UBS_PCI_TOUT(misc) \ 563d768ff8Sjonathan (((misc) >> PCI_TOUT_SHIFT) & PCI_TOUT_MASK) 573d768ff8Sjonathan 583d768ff8Sjonathan /* 593d768ff8Sjonathan * DMA Control & Status Registers (offset from BS_BAR) 603d768ff8Sjonathan */ 613d768ff8Sjonathan #define BS_MCR1 0x00 /* DMA Master Command Record 1 */ 623d768ff8Sjonathan #define BS_CTRL 0x04 /* DMA Control */ 633d768ff8Sjonathan #define BS_STAT 0x08 /* DMA Status */ 643d768ff8Sjonathan #define BS_ERR 0x0c /* DMA Error Address */ 653d768ff8Sjonathan #define BS_MCR2 0x10 /* DMA Master Command Record 2 */ 66fdd2e1a4Sbad #define BS_MCR3 0x0014 /* 5827+, DMA Master Command Record 3 */ 67fdd2e1a4Sbad #define BS_MCR4 0x001c /* 5827+, DMA Master Command Record 4 */ 68fdd2e1a4Sbad #define BS_CFG 0x0700 /* 5827+, Configuration Register */ 69fdd2e1a4Sbad #define BS_INT 0x0f00 /* 5827+, Interrupt Register */ 703d768ff8Sjonathan 713d768ff8Sjonathan /* BS_CTRL - DMA Control */ 723d768ff8Sjonathan #define BS_CTRL_RESET 0x80000000 /* hardware reset, 5805/5820 */ 733d768ff8Sjonathan #define BS_CTRL_MCR2INT 0x40000000 /* enable intr MCR for MCR2 */ 743d768ff8Sjonathan #define BS_CTRL_MCR1INT 0x20000000 /* enable intr MCR for MCR1 */ 753d768ff8Sjonathan #define BS_CTRL_OFM 0x10000000 /* Output fragment mode */ 763d768ff8Sjonathan #define BS_CTRL_BE32 0x08000000 /* big-endian, 32bit bytes */ 773d768ff8Sjonathan #define BS_CTRL_BE64 0x04000000 /* big-endian, 64bit bytes */ 783d768ff8Sjonathan #define BS_CTRL_DMAERR 0x02000000 /* enable intr DMA error */ 793d768ff8Sjonathan #define BS_CTRL_RNG_M 0x01800000 /* RNG mode */ 803d768ff8Sjonathan #define BS_CTRL_RNG_1 0x00000000 /* 1bit rn/one slow clock */ 813d768ff8Sjonathan #define BS_CTRL_RNG_4 0x00800000 /* 1bit rn/four slow clocks */ 823d768ff8Sjonathan #define BS_CTRL_RNG_8 0x01000000 /* 1bit rn/eight slow clocks */ 833d768ff8Sjonathan #define BS_CTRL_RNG_16 0x01800000 /* 1bit rn/16 slow clocks */ 843d768ff8Sjonathan #define BS_CTRL_SWNORM 0x00400000 /* 582[01], sw normalization */ 85fdd2e1a4Sbad #define BS_CTRL_MCR3INT 0x00400000 /* 5827+, intr for MCR3 */ 86fdd2e1a4Sbad #define BS_CTRL_MCR4INT 0x00200000 /* 5827+, intr for MCR4 */ 87fdd2e1a4Sbad #define BS_CTRL_BSIZE240 0x000f0000 /* 5827+, burst size 240 */ 883d768ff8Sjonathan #define BS_CTRL_FRAG_M 0x0000ffff /* output fragment size mask */ 893d768ff8Sjonathan #define BS_CTRL_LITTLE_ENDIAN (BS_CTRL_BE32 | BS_CTRL_BE64) 903d768ff8Sjonathan 913d768ff8Sjonathan /* BS_STAT - DMA Status */ 923d768ff8Sjonathan #define BS_STAT_MCR1_BUSY 0x80000000 /* MCR1 is busy */ 933d768ff8Sjonathan #define BS_STAT_MCR1_FULL 0x40000000 /* MCR1 is full */ 943d768ff8Sjonathan #define BS_STAT_MCR1_DONE 0x20000000 /* MCR1 is done */ 953d768ff8Sjonathan #define BS_STAT_DMAERR 0x10000000 /* DMA error */ 963d768ff8Sjonathan #define BS_STAT_MCR2_FULL 0x08000000 /* MCR2 is full */ 973d768ff8Sjonathan #define BS_STAT_MCR2_DONE 0x04000000 /* MCR2 is done */ 983d768ff8Sjonathan #define BS_STAT_MCR1_ALLEMPTY 0x02000000 /* 5821, MCR1 is empty */ 993d768ff8Sjonathan #define BS_STAT_MCR2_ALLEMPTY 0x01000000 /* 5821, MCR2 is empty */ 100fdd2e1a4Sbad #define BS_STAT_MCR3_ALLEMPTY 0x00800000 /* 5827+, MCR3 is empty */ 101fdd2e1a4Sbad #define BS_STAT_MCR4_ALLEMPTY 0x00400000 /* 5827+, MCR4 is empty */ 102fdd2e1a4Sbad #define BS_STAT_MCR3_FULL 0x00080000 /* 5827+, MCR3 is full */ 103fdd2e1a4Sbad #define BS_STAT_MCR3_DONE 0x00040000 /* 5827+, MCR3 is done */ 104fdd2e1a4Sbad #define BS_STAT_MCR4_FULL 0x00020000 /* 5827+, MCR4 is full */ 105fdd2e1a4Sbad #define BS_STAT_MCR4_DONE 0x00010000 /* 5827+, MCR4 is done */ 1063d768ff8Sjonathan 1073d768ff8Sjonathan /* BS_ERR - DMA Error Address */ 1083d768ff8Sjonathan #define BS_ERR_ADDR 0xfffffffc /* error address mask */ 1093d768ff8Sjonathan #define BS_ERR_READ 0x00000002 /* fault was on read */ 1103d768ff8Sjonathan 111fdd2e1a4Sbad /* BS_CFG */ 112fdd2e1a4Sbad #define BS_CFG_RNG 0x00000001 /* 5827+, enable RNG */ 113fdd2e1a4Sbad 114fdd2e1a4Sbad /* BS_INT */ 115fdd2e1a4Sbad #define BS_INT_DMAINT 0x80000000 /* 5827+, enable DMA intr */ 116fdd2e1a4Sbad 117d07a32c1Sbad /* DES/3DES */ 1183d768ff8Sjonathan struct ubsec_pktctx { 1193d768ff8Sjonathan u_int32_t pc_deskey[6]; /* 3DES key */ 1203d768ff8Sjonathan u_int32_t pc_hminner[5]; /* hmac inner state */ 1213d768ff8Sjonathan u_int32_t pc_hmouter[5]; /* hmac outer state */ 1223d768ff8Sjonathan u_int32_t pc_iv[2]; /* [3]DES iv */ 1233d768ff8Sjonathan u_int16_t pc_flags; /* flags, below */ 1243d768ff8Sjonathan u_int16_t pc_offset; /* crypto offset */ 1253d768ff8Sjonathan }; 1263d768ff8Sjonathan #define UBS_PKTCTX_ENC_3DES 0x8000 /* use 3des */ 1273d768ff8Sjonathan #define UBS_PKTCTX_ENC_NONE 0x0000 /* no encryption */ 1283d768ff8Sjonathan #define UBS_PKTCTX_INBOUND 0x4000 /* inbound packet */ 1293d768ff8Sjonathan #define UBS_PKTCTX_AUTH 0x3000 /* authentication mask */ 1303d768ff8Sjonathan #define UBS_PKTCTX_AUTH_NONE 0x0000 /* no authentication */ 1313d768ff8Sjonathan #define UBS_PKTCTX_AUTH_MD5 0x1000 /* use hmac-md5 */ 1323d768ff8Sjonathan #define UBS_PKTCTX_AUTH_SHA1 0x2000 /* use hmac-sha1 */ 1333d768ff8Sjonathan 134d07a32c1Sbad /* "Long" cryptographic operations on newer chipsets */ 135d07a32c1Sbad #define UBS_PKTCTX_TYPE_IPSEC_3DES 0x0000 136d07a32c1Sbad #define UBS_PKTCTX_TYPE_IPSEC_AES 0x0040 137d07a32c1Sbad 138d07a32c1Sbad struct ubsec_pktctx_hdr { 139d07a32c1Sbad volatile u_int16_t ph_len; /* length of ctx struct */ 140d07a32c1Sbad volatile u_int16_t ph_type; /* context type, 0 */ 141d07a32c1Sbad volatile u_int16_t ph_flags; /* flags, same as above */ 142d07a32c1Sbad volatile u_int16_t ph_offset; /* crypto/auth offset */ 143d07a32c1Sbad }; 144d07a32c1Sbad 145d07a32c1Sbad /* Long version of DES/3DES */ 146d07a32c1Sbad struct ubsec_pktctx_3des { 147d07a32c1Sbad struct ubsec_pktctx_hdr pc_hdr; /* Common header */ 1483d768ff8Sjonathan volatile u_int32_t pc_deskey[6]; /* 3DES key */ 1493d768ff8Sjonathan volatile u_int32_t pc_iv[2]; /* [3]DES iv */ 1503d768ff8Sjonathan volatile u_int32_t pc_hminner[5]; /* hmac inner state */ 1513d768ff8Sjonathan volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ 1523d768ff8Sjonathan }; 153d07a32c1Sbad 154d07a32c1Sbad /* AES uses different structures for each supported key size */ 155d07a32c1Sbad struct ubsec_pktctx_aes128 { 156d07a32c1Sbad struct ubsec_pktctx_hdr pc_hdr; /* Common header */ 157d07a32c1Sbad volatile u_int32_t pc_aeskey[4]; /* AES128 key */ 158d07a32c1Sbad volatile u_int32_t pc_iv[4]; /* AES iv/ucv */ 159d07a32c1Sbad volatile u_int32_t pc_hminner[5]; /* hmac inner state */ 160d07a32c1Sbad volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ 161d07a32c1Sbad }; 162d07a32c1Sbad 163d07a32c1Sbad struct ubsec_pktctx_aes192 { 164d07a32c1Sbad struct ubsec_pktctx_hdr pc_hdr; /* Common header */ 165d07a32c1Sbad volatile u_int32_t pc_aeskey[6]; /* AES192 key */ 166d07a32c1Sbad volatile u_int32_t pc_iv[4]; /* AES iv/icv */ 167d07a32c1Sbad volatile u_int32_t pc_hminner[5]; /* hmac inner state */ 168d07a32c1Sbad volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ 169d07a32c1Sbad }; 170d07a32c1Sbad 171d07a32c1Sbad struct ubsec_pktctx_aes256 { 172d07a32c1Sbad struct ubsec_pktctx_hdr pc_hdr; /* Common header */ 173d07a32c1Sbad volatile u_int32_t pc_aeskey[8]; /* AES256 key */ 174d07a32c1Sbad volatile u_int32_t pc_iv[4]; /* AES iv/icv */ 175d07a32c1Sbad volatile u_int32_t pc_hminner[5]; /* hmac inner state */ 176d07a32c1Sbad volatile u_int32_t pc_hmouter[5]; /* hmac outer state */ 177d07a32c1Sbad }; 178d07a32c1Sbad #define UBS_PKTCTX_ENC_AES 0x8000 /* use aes */ 179d07a32c1Sbad #define UBS_PKTCTX_MODE_CBC 0x0000 /* Cipher Block Chaining mode */ 180d07a32c1Sbad #define UBS_PKTCTX_MODE_CTR 0x0400 /* Counter mode */ 181d07a32c1Sbad #define UBS_PKTCTX_KEYSIZE_128 0x0000 /* AES128 */ 182d07a32c1Sbad #define UBS_PKTCTX_KEYSIZE_192 0x0100 /* AES192 */ 183d07a32c1Sbad #define UBS_PKTCTX_KEYSIZE_256 0x0200 /* AES256 */ 1843d768ff8Sjonathan 1853d768ff8Sjonathan struct ubsec_pktbuf { 1863d768ff8Sjonathan volatile u_int32_t pb_addr; /* address of buffer start */ 1873d768ff8Sjonathan volatile u_int32_t pb_next; /* pointer to next pktbuf */ 1883d768ff8Sjonathan volatile u_int32_t pb_len; /* packet length */ 1893d768ff8Sjonathan }; 1903d768ff8Sjonathan #define UBS_PKTBUF_LEN 0x0000ffff /* length mask */ 1913d768ff8Sjonathan 1923d768ff8Sjonathan struct ubsec_mcr { 1933d768ff8Sjonathan volatile u_int16_t mcr_pkts; /* #pkts in this mcr */ 1943d768ff8Sjonathan volatile u_int16_t mcr_flags; /* mcr flags (below) */ 1953d768ff8Sjonathan volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ 1963d768ff8Sjonathan struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ 1973d768ff8Sjonathan volatile u_int16_t mcr_reserved; 1983d768ff8Sjonathan volatile u_int16_t mcr_pktlen; 1993d768ff8Sjonathan struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ 2003d768ff8Sjonathan }; 2013d768ff8Sjonathan 2023d768ff8Sjonathan struct ubsec_mcr_add { 2033d768ff8Sjonathan volatile u_int32_t mcr_cmdctxp; /* command ctx pointer */ 2043d768ff8Sjonathan struct ubsec_pktbuf mcr_ipktbuf; /* input chain header */ 2053d768ff8Sjonathan volatile u_int16_t mcr_reserved; 2063d768ff8Sjonathan volatile u_int16_t mcr_pktlen; 2073d768ff8Sjonathan struct ubsec_pktbuf mcr_opktbuf; /* output chain header */ 2083d768ff8Sjonathan }; 2093d768ff8Sjonathan 2103d768ff8Sjonathan #define UBS_MCR_DONE 0x0001 /* mcr has been processed */ 2113d768ff8Sjonathan #define UBS_MCR_ERROR 0x0002 /* error in processing */ 2123d768ff8Sjonathan #define UBS_MCR_ERRORCODE 0xff00 /* error type */ 2133d768ff8Sjonathan 2143d768ff8Sjonathan struct ubsec_ctx_keyop { 2153d768ff8Sjonathan volatile u_int16_t ctx_len; /* command length */ 2163d768ff8Sjonathan volatile u_int16_t ctx_op; /* operation code */ 2173d768ff8Sjonathan volatile u_int8_t ctx_pad[60]; /* padding */ 2183d768ff8Sjonathan }; 2193d768ff8Sjonathan #define UBS_CTXOP_DHPKGEN 0x01 /* dh public key generation */ 2203d768ff8Sjonathan #define UBS_CTXOP_DHSSGEN 0x02 /* dh shared secret gen. */ 2213d768ff8Sjonathan #define UBS_CTXOP_RSAPUB 0x03 /* rsa public key op */ 2223d768ff8Sjonathan #define UBS_CTXOP_RSAPRIV 0x04 /* rsa private key op */ 2233d768ff8Sjonathan #define UBS_CTXOP_DSASIGN 0x05 /* dsa signing op */ 2243d768ff8Sjonathan #define UBS_CTXOP_DSAVRFY 0x06 /* dsa verification */ 2253d768ff8Sjonathan #define UBS_CTXOP_RNGBYPASS 0x41 /* rng direct test mode */ 2263d768ff8Sjonathan #define UBS_CTXOP_RNGSHA1 0x42 /* rng sha1 test mode */ 2273d768ff8Sjonathan #define UBS_CTXOP_MODADD 0x43 /* modular addition */ 2283d768ff8Sjonathan #define UBS_CTXOP_MODSUB 0x44 /* modular subtraction */ 2293d768ff8Sjonathan #define UBS_CTXOP_MODMUL 0x45 /* modular multiplication */ 2303d768ff8Sjonathan #define UBS_CTXOP_MODRED 0x46 /* modular reduction */ 2313d768ff8Sjonathan #define UBS_CTXOP_MODEXP 0x47 /* modular exponentiation */ 2323d768ff8Sjonathan #define UBS_CTXOP_MODINV 0x48 /* modular inverse */ 2333d768ff8Sjonathan 2343d768ff8Sjonathan struct ubsec_ctx_rngbypass { 2353d768ff8Sjonathan volatile u_int16_t rbp_len; /* command length, 64 */ 2363d768ff8Sjonathan volatile u_int16_t rbp_op; /* rng bypass, 0x41 */ 2373d768ff8Sjonathan volatile u_int8_t rbp_pad[60]; /* padding */ 2383d768ff8Sjonathan }; 2393d768ff8Sjonathan 2403d768ff8Sjonathan /* modexp: C = (M ^ E) mod N */ 2413d768ff8Sjonathan struct ubsec_ctx_modexp { 2423d768ff8Sjonathan volatile u_int16_t me_len; /* command length */ 2433d768ff8Sjonathan volatile u_int16_t me_op; /* modexp, 0x47 */ 2443d768ff8Sjonathan volatile u_int16_t me_E_len; /* E (bits) */ 2453d768ff8Sjonathan volatile u_int16_t me_N_len; /* N (bits) */ 2463d768ff8Sjonathan u_int8_t me_N[2048/8]; /* N */ 2473d768ff8Sjonathan }; 2483d768ff8Sjonathan 2493d768ff8Sjonathan struct ubsec_ctx_rsapriv { 2503d768ff8Sjonathan volatile u_int16_t rpr_len; /* command length */ 2513d768ff8Sjonathan volatile u_int16_t rpr_op; /* rsaprivate, 0x04 */ 2523d768ff8Sjonathan volatile u_int16_t rpr_q_len; /* q (bits) */ 2533d768ff8Sjonathan volatile u_int16_t rpr_p_len; /* p (bits) */ 2543d768ff8Sjonathan u_int8_t rpr_buf[5 * 1024 / 8]; /* parameters: */ 2553d768ff8Sjonathan /* p, q, dp, dq, pinv */ 2563d768ff8Sjonathan }; 257*89b627d4Sriastradh 258*89b627d4Sriastradh #endif /* _DEV_PCI_UBSECREG_H */ 259