1*677dec6eSriastradh /* $NetBSD: radeon_ucode.h,v 1.3 2021/12/18 23:45:43 riastradh Exp $ */ 2d350ecf5Sriastradh 3cb459498Sriastradh /* 4cb459498Sriastradh * Copyright 2012 Advanced Micro Devices, Inc. 5cb459498Sriastradh * 6cb459498Sriastradh * Permission is hereby granted, free of charge, to any person obtaining a 7cb459498Sriastradh * copy of this software and associated documentation files (the "Software"), 8cb459498Sriastradh * to deal in the Software without restriction, including without limitation 9cb459498Sriastradh * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10cb459498Sriastradh * and/or sell copies of the Software, and to permit persons to whom the 11cb459498Sriastradh * Software is furnished to do so, subject to the following conditions: 12cb459498Sriastradh * 13cb459498Sriastradh * The above copyright notice and this permission notice shall be included in 14cb459498Sriastradh * all copies or substantial portions of the Software. 15cb459498Sriastradh * 16cb459498Sriastradh * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17cb459498Sriastradh * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18cb459498Sriastradh * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19cb459498Sriastradh * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20cb459498Sriastradh * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21cb459498Sriastradh * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22cb459498Sriastradh * OTHER DEALINGS IN THE SOFTWARE. 23cb459498Sriastradh * 24cb459498Sriastradh */ 25cb459498Sriastradh #ifndef __RADEON_UCODE_H__ 26cb459498Sriastradh #define __RADEON_UCODE_H__ 27cb459498Sriastradh 28cb459498Sriastradh /* CP */ 29cb459498Sriastradh #define R600_PFP_UCODE_SIZE 576 30cb459498Sriastradh #define R600_PM4_UCODE_SIZE 1792 31cb459498Sriastradh #define R700_PFP_UCODE_SIZE 848 32cb459498Sriastradh #define R700_PM4_UCODE_SIZE 1360 33cb459498Sriastradh #define EVERGREEN_PFP_UCODE_SIZE 1120 34cb459498Sriastradh #define EVERGREEN_PM4_UCODE_SIZE 1376 35cb459498Sriastradh #define CAYMAN_PFP_UCODE_SIZE 2176 36cb459498Sriastradh #define CAYMAN_PM4_UCODE_SIZE 2176 37cb459498Sriastradh #define SI_PFP_UCODE_SIZE 2144 38cb459498Sriastradh #define SI_PM4_UCODE_SIZE 2144 39cb459498Sriastradh #define SI_CE_UCODE_SIZE 2144 40cb459498Sriastradh #define CIK_PFP_UCODE_SIZE 2144 41cb459498Sriastradh #define CIK_ME_UCODE_SIZE 2144 42cb459498Sriastradh #define CIK_CE_UCODE_SIZE 2144 43cb459498Sriastradh 44cb459498Sriastradh /* MEC */ 45cb459498Sriastradh #define CIK_MEC_UCODE_SIZE 4192 46cb459498Sriastradh 47cb459498Sriastradh /* RLC */ 48cb459498Sriastradh #define R600_RLC_UCODE_SIZE 768 49cb459498Sriastradh #define R700_RLC_UCODE_SIZE 1024 50cb459498Sriastradh #define EVERGREEN_RLC_UCODE_SIZE 768 51cb459498Sriastradh #define CAYMAN_RLC_UCODE_SIZE 1024 52cb459498Sriastradh #define ARUBA_RLC_UCODE_SIZE 1536 53cb459498Sriastradh #define SI_RLC_UCODE_SIZE 2048 54cb459498Sriastradh #define BONAIRE_RLC_UCODE_SIZE 2048 55cb459498Sriastradh #define KB_RLC_UCODE_SIZE 2560 56cb459498Sriastradh #define KV_RLC_UCODE_SIZE 2560 57cb459498Sriastradh #define ML_RLC_UCODE_SIZE 2560 58cb459498Sriastradh 59cb459498Sriastradh /* MC */ 60cb459498Sriastradh #define BTC_MC_UCODE_SIZE 6024 61cb459498Sriastradh #define CAYMAN_MC_UCODE_SIZE 6037 62cb459498Sriastradh #define SI_MC_UCODE_SIZE 7769 63cb459498Sriastradh #define TAHITI_MC_UCODE_SIZE 7808 64cb459498Sriastradh #define PITCAIRN_MC_UCODE_SIZE 7775 65cb459498Sriastradh #define VERDE_MC_UCODE_SIZE 7875 66cb459498Sriastradh #define OLAND_MC_UCODE_SIZE 7863 67cb459498Sriastradh #define BONAIRE_MC_UCODE_SIZE 7866 68cb459498Sriastradh #define BONAIRE_MC2_UCODE_SIZE 7948 69cb459498Sriastradh #define HAWAII_MC_UCODE_SIZE 7933 70cb459498Sriastradh #define HAWAII_MC2_UCODE_SIZE 8091 71cb459498Sriastradh 72cb459498Sriastradh /* SDMA */ 73cb459498Sriastradh #define CIK_SDMA_UCODE_SIZE 1050 74cb459498Sriastradh #define CIK_SDMA_UCODE_VERSION 64 75cb459498Sriastradh 76cb459498Sriastradh /* SMC */ 77cb459498Sriastradh #define RV770_SMC_UCODE_START 0x0100 78cb459498Sriastradh #define RV770_SMC_UCODE_SIZE 0x410d 79cb459498Sriastradh #define RV770_SMC_INT_VECTOR_START 0xffc0 80cb459498Sriastradh #define RV770_SMC_INT_VECTOR_SIZE 0x0040 81cb459498Sriastradh 82cb459498Sriastradh #define RV730_SMC_UCODE_START 0x0100 83cb459498Sriastradh #define RV730_SMC_UCODE_SIZE 0x412c 84cb459498Sriastradh #define RV730_SMC_INT_VECTOR_START 0xffc0 85cb459498Sriastradh #define RV730_SMC_INT_VECTOR_SIZE 0x0040 86cb459498Sriastradh 87cb459498Sriastradh #define RV710_SMC_UCODE_START 0x0100 88cb459498Sriastradh #define RV710_SMC_UCODE_SIZE 0x3f1f 89cb459498Sriastradh #define RV710_SMC_INT_VECTOR_START 0xffc0 90cb459498Sriastradh #define RV710_SMC_INT_VECTOR_SIZE 0x0040 91cb459498Sriastradh 92cb459498Sriastradh #define RV740_SMC_UCODE_START 0x0100 93cb459498Sriastradh #define RV740_SMC_UCODE_SIZE 0x41c5 94cb459498Sriastradh #define RV740_SMC_INT_VECTOR_START 0xffc0 95cb459498Sriastradh #define RV740_SMC_INT_VECTOR_SIZE 0x0040 96cb459498Sriastradh 97cb459498Sriastradh #define CEDAR_SMC_UCODE_START 0x0100 98cb459498Sriastradh #define CEDAR_SMC_UCODE_SIZE 0x5d50 99cb459498Sriastradh #define CEDAR_SMC_INT_VECTOR_START 0xffc0 100cb459498Sriastradh #define CEDAR_SMC_INT_VECTOR_SIZE 0x0040 101cb459498Sriastradh 102cb459498Sriastradh #define REDWOOD_SMC_UCODE_START 0x0100 103cb459498Sriastradh #define REDWOOD_SMC_UCODE_SIZE 0x5f0a 104cb459498Sriastradh #define REDWOOD_SMC_INT_VECTOR_START 0xffc0 105cb459498Sriastradh #define REDWOOD_SMC_INT_VECTOR_SIZE 0x0040 106cb459498Sriastradh 107cb459498Sriastradh #define JUNIPER_SMC_UCODE_START 0x0100 108cb459498Sriastradh #define JUNIPER_SMC_UCODE_SIZE 0x5f1f 109cb459498Sriastradh #define JUNIPER_SMC_INT_VECTOR_START 0xffc0 110cb459498Sriastradh #define JUNIPER_SMC_INT_VECTOR_SIZE 0x0040 111cb459498Sriastradh 112cb459498Sriastradh #define CYPRESS_SMC_UCODE_START 0x0100 113cb459498Sriastradh #define CYPRESS_SMC_UCODE_SIZE 0x61f7 114cb459498Sriastradh #define CYPRESS_SMC_INT_VECTOR_START 0xffc0 115cb459498Sriastradh #define CYPRESS_SMC_INT_VECTOR_SIZE 0x0040 116cb459498Sriastradh 117cb459498Sriastradh #define BARTS_SMC_UCODE_START 0x0100 118cb459498Sriastradh #define BARTS_SMC_UCODE_SIZE 0x6107 119cb459498Sriastradh #define BARTS_SMC_INT_VECTOR_START 0xffc0 120cb459498Sriastradh #define BARTS_SMC_INT_VECTOR_SIZE 0x0040 121cb459498Sriastradh 122cb459498Sriastradh #define TURKS_SMC_UCODE_START 0x0100 123cb459498Sriastradh #define TURKS_SMC_UCODE_SIZE 0x605b 124cb459498Sriastradh #define TURKS_SMC_INT_VECTOR_START 0xffc0 125cb459498Sriastradh #define TURKS_SMC_INT_VECTOR_SIZE 0x0040 126cb459498Sriastradh 127cb459498Sriastradh #define CAICOS_SMC_UCODE_START 0x0100 128cb459498Sriastradh #define CAICOS_SMC_UCODE_SIZE 0x5fbd 129cb459498Sriastradh #define CAICOS_SMC_INT_VECTOR_START 0xffc0 130cb459498Sriastradh #define CAICOS_SMC_INT_VECTOR_SIZE 0x0040 131cb459498Sriastradh 132cb459498Sriastradh #define CAYMAN_SMC_UCODE_START 0x0100 133cb459498Sriastradh #define CAYMAN_SMC_UCODE_SIZE 0x79ec 134cb459498Sriastradh #define CAYMAN_SMC_INT_VECTOR_START 0xffc0 135cb459498Sriastradh #define CAYMAN_SMC_INT_VECTOR_SIZE 0x0040 136cb459498Sriastradh 137cb459498Sriastradh #define TAHITI_SMC_UCODE_START 0x10000 138cb459498Sriastradh #define TAHITI_SMC_UCODE_SIZE 0xf458 139cb459498Sriastradh 140cb459498Sriastradh #define PITCAIRN_SMC_UCODE_START 0x10000 141cb459498Sriastradh #define PITCAIRN_SMC_UCODE_SIZE 0xe9f4 142cb459498Sriastradh 143cb459498Sriastradh #define VERDE_SMC_UCODE_START 0x10000 144cb459498Sriastradh #define VERDE_SMC_UCODE_SIZE 0xebe4 145cb459498Sriastradh 146cb459498Sriastradh #define OLAND_SMC_UCODE_START 0x10000 147cb459498Sriastradh #define OLAND_SMC_UCODE_SIZE 0xe7b4 148cb459498Sriastradh 149cb459498Sriastradh #define HAINAN_SMC_UCODE_START 0x10000 150cb459498Sriastradh #define HAINAN_SMC_UCODE_SIZE 0xe67C 151cb459498Sriastradh 152cb459498Sriastradh #define BONAIRE_SMC_UCODE_START 0x20000 153cb459498Sriastradh #define BONAIRE_SMC_UCODE_SIZE 0x1FDEC 154cb459498Sriastradh 155cb459498Sriastradh #define HAWAII_SMC_UCODE_START 0x20000 156cb459498Sriastradh #define HAWAII_SMC_UCODE_SIZE 0x1FDEC 157cb459498Sriastradh 158d350ecf5Sriastradh struct common_firmware_header { 159d350ecf5Sriastradh uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 160d350ecf5Sriastradh uint32_t header_size_bytes; /* size of just the header in bytes */ 161d350ecf5Sriastradh uint16_t header_version_major; /* header version */ 162d350ecf5Sriastradh uint16_t header_version_minor; /* header version */ 163d350ecf5Sriastradh uint16_t ip_version_major; /* IP version */ 164d350ecf5Sriastradh uint16_t ip_version_minor; /* IP version */ 165d350ecf5Sriastradh uint32_t ucode_version; 166d350ecf5Sriastradh uint32_t ucode_size_bytes; /* size of ucode in bytes */ 167d350ecf5Sriastradh uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 168d350ecf5Sriastradh uint32_t crc32; /* crc32 checksum of the payload */ 169d350ecf5Sriastradh }; 170d350ecf5Sriastradh 171d350ecf5Sriastradh /* version_major=1, version_minor=0 */ 172d350ecf5Sriastradh struct mc_firmware_header_v1_0 { 173d350ecf5Sriastradh struct common_firmware_header header; 174d350ecf5Sriastradh uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 175d350ecf5Sriastradh uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 176d350ecf5Sriastradh }; 177d350ecf5Sriastradh 178d350ecf5Sriastradh /* version_major=1, version_minor=0 */ 179d350ecf5Sriastradh struct smc_firmware_header_v1_0 { 180d350ecf5Sriastradh struct common_firmware_header header; 181d350ecf5Sriastradh uint32_t ucode_start_addr; 182d350ecf5Sriastradh }; 183d350ecf5Sriastradh 184d350ecf5Sriastradh /* version_major=1, version_minor=0 */ 185d350ecf5Sriastradh struct gfx_firmware_header_v1_0 { 186d350ecf5Sriastradh struct common_firmware_header header; 187d350ecf5Sriastradh uint32_t ucode_feature_version; 188d350ecf5Sriastradh uint32_t jt_offset; /* jt location */ 189d350ecf5Sriastradh uint32_t jt_size; /* size of jt */ 190d350ecf5Sriastradh }; 191d350ecf5Sriastradh 192d350ecf5Sriastradh /* version_major=1, version_minor=0 */ 193d350ecf5Sriastradh struct rlc_firmware_header_v1_0 { 194d350ecf5Sriastradh struct common_firmware_header header; 195d350ecf5Sriastradh uint32_t ucode_feature_version; 196d350ecf5Sriastradh uint32_t save_and_restore_offset; 197d350ecf5Sriastradh uint32_t clear_state_descriptor_offset; 198d350ecf5Sriastradh uint32_t avail_scratch_ram_locations; 199d350ecf5Sriastradh uint32_t master_pkt_description_offset; 200d350ecf5Sriastradh }; 201d350ecf5Sriastradh 202d350ecf5Sriastradh /* version_major=1, version_minor=0 */ 203d350ecf5Sriastradh struct sdma_firmware_header_v1_0 { 204d350ecf5Sriastradh struct common_firmware_header header; 205d350ecf5Sriastradh uint32_t ucode_feature_version; 206d350ecf5Sriastradh uint32_t ucode_change_version; 207d350ecf5Sriastradh uint32_t jt_offset; /* jt location */ 208d350ecf5Sriastradh uint32_t jt_size; /* size of jt */ 209d350ecf5Sriastradh }; 210d350ecf5Sriastradh 211d350ecf5Sriastradh /* header is fixed size */ 212d350ecf5Sriastradh union radeon_firmware_header { 213d350ecf5Sriastradh struct common_firmware_header common; 214d350ecf5Sriastradh struct mc_firmware_header_v1_0 mc; 215d350ecf5Sriastradh struct smc_firmware_header_v1_0 smc; 216d350ecf5Sriastradh struct gfx_firmware_header_v1_0 gfx; 217d350ecf5Sriastradh struct rlc_firmware_header_v1_0 rlc; 218d350ecf5Sriastradh struct sdma_firmware_header_v1_0 sdma; 219d350ecf5Sriastradh uint8_t raw[0x100]; 220d350ecf5Sriastradh }; 221d350ecf5Sriastradh 222d350ecf5Sriastradh void radeon_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 223d350ecf5Sriastradh void radeon_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 224d350ecf5Sriastradh void radeon_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 225d350ecf5Sriastradh void radeon_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 226d350ecf5Sriastradh void radeon_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 227d350ecf5Sriastradh int radeon_ucode_validate(const struct firmware *fw); 228d350ecf5Sriastradh 229cb459498Sriastradh #endif 230