1*0cc12ebdSjmcneill/*
2*0cc12ebdSjmcneill * ARM Ltd.
3*0cc12ebdSjmcneill *
4*0cc12ebdSjmcneill * ARMv8 Foundation model DTS (spin table configuration)
5*0cc12ebdSjmcneill */
6*0cc12ebdSjmcneill
7*0cc12ebdSjmcneill&cpu0 {
8*0cc12ebdSjmcneill	enable-method = "spin-table";
9*0cc12ebdSjmcneill	cpu-release-addr = <0x0 0x8000fff8>;
10*0cc12ebdSjmcneill};
11*0cc12ebdSjmcneill
12*0cc12ebdSjmcneill&cpu1 {
13*0cc12ebdSjmcneill	enable-method = "spin-table";
14*0cc12ebdSjmcneill	cpu-release-addr = <0x0 0x8000fff8>;
15*0cc12ebdSjmcneill};
16*0cc12ebdSjmcneill
17*0cc12ebdSjmcneill&cpu2 {
18*0cc12ebdSjmcneill	enable-method = "spin-table";
19*0cc12ebdSjmcneill	cpu-release-addr = <0x0 0x8000fff8>;
20*0cc12ebdSjmcneill};
21*0cc12ebdSjmcneill
22*0cc12ebdSjmcneill&cpu3 {
23*0cc12ebdSjmcneill	enable-method = "spin-table";
24*0cc12ebdSjmcneill	cpu-release-addr = <0x0 0x8000fff8>;
25*0cc12ebdSjmcneill};
26