1f46c7ed4Sjmcneill/* 2f46c7ed4Sjmcneill * ARM Ltd. Juno Platform 3f46c7ed4Sjmcneill * 4f46c7ed4Sjmcneill * Copyright (c) 2015 ARM Ltd. 5f46c7ed4Sjmcneill * 6f46c7ed4Sjmcneill * This file is licensed under a dual GPLv2 or BSD license. 7f46c7ed4Sjmcneill */ 8f46c7ed4Sjmcneill 9f46c7ed4Sjmcneill/dts-v1/; 10f46c7ed4Sjmcneill 11f46c7ed4Sjmcneill#include <dt-bindings/interrupt-controller/arm-gic.h> 12f46c7ed4Sjmcneill#include "juno-base.dtsi" 13f46c7ed4Sjmcneill#include "juno-cs-r1r2.dtsi" 14f46c7ed4Sjmcneill 15f46c7ed4Sjmcneill/ { 16f46c7ed4Sjmcneill model = "ARM Juno development board (r1)"; 17f46c7ed4Sjmcneill compatible = "arm,juno-r1", "arm,juno", "arm,vexpress"; 18f46c7ed4Sjmcneill interrupt-parent = <&gic>; 19f46c7ed4Sjmcneill #address-cells = <2>; 20f46c7ed4Sjmcneill #size-cells = <2>; 21f46c7ed4Sjmcneill 22f46c7ed4Sjmcneill aliases { 23f46c7ed4Sjmcneill serial0 = &soc_uart0; 24f46c7ed4Sjmcneill }; 25f46c7ed4Sjmcneill 26f46c7ed4Sjmcneill chosen { 27f46c7ed4Sjmcneill stdout-path = "serial0:115200n8"; 28f46c7ed4Sjmcneill }; 29f46c7ed4Sjmcneill 30f46c7ed4Sjmcneill psci { 31f46c7ed4Sjmcneill compatible = "arm,psci-0.2"; 32f46c7ed4Sjmcneill method = "smc"; 33f46c7ed4Sjmcneill }; 34f46c7ed4Sjmcneill 35f46c7ed4Sjmcneill cpus { 36f46c7ed4Sjmcneill #address-cells = <2>; 37f46c7ed4Sjmcneill #size-cells = <0>; 38f46c7ed4Sjmcneill 39f46c7ed4Sjmcneill cpu-map { 40f46c7ed4Sjmcneill cluster0 { 41f46c7ed4Sjmcneill core0 { 42f46c7ed4Sjmcneill cpu = <&A57_0>; 43f46c7ed4Sjmcneill }; 44f46c7ed4Sjmcneill core1 { 45f46c7ed4Sjmcneill cpu = <&A57_1>; 46f46c7ed4Sjmcneill }; 47f46c7ed4Sjmcneill }; 48f46c7ed4Sjmcneill 49f46c7ed4Sjmcneill cluster1 { 50f46c7ed4Sjmcneill core0 { 51f46c7ed4Sjmcneill cpu = <&A53_0>; 52f46c7ed4Sjmcneill }; 53f46c7ed4Sjmcneill core1 { 54f46c7ed4Sjmcneill cpu = <&A53_1>; 55f46c7ed4Sjmcneill }; 56f46c7ed4Sjmcneill core2 { 57f46c7ed4Sjmcneill cpu = <&A53_2>; 58f46c7ed4Sjmcneill }; 59f46c7ed4Sjmcneill core3 { 60f46c7ed4Sjmcneill cpu = <&A53_3>; 61f46c7ed4Sjmcneill }; 62f46c7ed4Sjmcneill }; 63f46c7ed4Sjmcneill }; 64f46c7ed4Sjmcneill 65f46c7ed4Sjmcneill idle-states { 66182157ecSjmcneill entry-method = "psci"; 67f46c7ed4Sjmcneill 68f46c7ed4Sjmcneill CPU_SLEEP_0: cpu-sleep-0 { 69f46c7ed4Sjmcneill compatible = "arm,idle-state"; 70f46c7ed4Sjmcneill arm,psci-suspend-param = <0x0010000>; 71f46c7ed4Sjmcneill local-timer-stop; 72f46c7ed4Sjmcneill entry-latency-us = <300>; 73f46c7ed4Sjmcneill exit-latency-us = <1200>; 74f46c7ed4Sjmcneill min-residency-us = <2000>; 75f46c7ed4Sjmcneill }; 76f46c7ed4Sjmcneill 77f46c7ed4Sjmcneill CLUSTER_SLEEP_0: cluster-sleep-0 { 78f46c7ed4Sjmcneill compatible = "arm,idle-state"; 79f46c7ed4Sjmcneill arm,psci-suspend-param = <0x1010000>; 80f46c7ed4Sjmcneill local-timer-stop; 81f46c7ed4Sjmcneill entry-latency-us = <400>; 82f46c7ed4Sjmcneill exit-latency-us = <1200>; 83f46c7ed4Sjmcneill min-residency-us = <2500>; 84f46c7ed4Sjmcneill }; 85f46c7ed4Sjmcneill }; 86f46c7ed4Sjmcneill 87f46c7ed4Sjmcneill A57_0: cpu@0 { 88*84c8294dSjmcneill compatible = "arm,cortex-a57"; 89f46c7ed4Sjmcneill reg = <0x0 0x0>; 90f46c7ed4Sjmcneill device_type = "cpu"; 91f46c7ed4Sjmcneill enable-method = "psci"; 928fb04b9bSjmcneill i-cache-size = <0xc000>; 938fb04b9bSjmcneill i-cache-line-size = <64>; 948fb04b9bSjmcneill i-cache-sets = <256>; 958fb04b9bSjmcneill d-cache-size = <0x8000>; 968fb04b9bSjmcneill d-cache-line-size = <64>; 978fb04b9bSjmcneill d-cache-sets = <256>; 98f46c7ed4Sjmcneill next-level-cache = <&A57_L2>; 99f46c7ed4Sjmcneill clocks = <&scpi_dvfs 0>; 100f46c7ed4Sjmcneill cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 101f46c7ed4Sjmcneill capacity-dmips-mhz = <1024>; 102f46c7ed4Sjmcneill }; 103f46c7ed4Sjmcneill 104f46c7ed4Sjmcneill A57_1: cpu@1 { 105*84c8294dSjmcneill compatible = "arm,cortex-a57"; 106f46c7ed4Sjmcneill reg = <0x0 0x1>; 107f46c7ed4Sjmcneill device_type = "cpu"; 108f46c7ed4Sjmcneill enable-method = "psci"; 1098fb04b9bSjmcneill i-cache-size = <0xc000>; 1108fb04b9bSjmcneill i-cache-line-size = <64>; 1118fb04b9bSjmcneill i-cache-sets = <256>; 1128fb04b9bSjmcneill d-cache-size = <0x8000>; 1138fb04b9bSjmcneill d-cache-line-size = <64>; 1148fb04b9bSjmcneill d-cache-sets = <256>; 115f46c7ed4Sjmcneill next-level-cache = <&A57_L2>; 116f46c7ed4Sjmcneill clocks = <&scpi_dvfs 0>; 117f46c7ed4Sjmcneill cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 118f46c7ed4Sjmcneill capacity-dmips-mhz = <1024>; 119f46c7ed4Sjmcneill }; 120f46c7ed4Sjmcneill 121f46c7ed4Sjmcneill A53_0: cpu@100 { 122*84c8294dSjmcneill compatible = "arm,cortex-a53"; 123f46c7ed4Sjmcneill reg = <0x0 0x100>; 124f46c7ed4Sjmcneill device_type = "cpu"; 125f46c7ed4Sjmcneill enable-method = "psci"; 1268fb04b9bSjmcneill i-cache-size = <0x8000>; 1278fb04b9bSjmcneill i-cache-line-size = <64>; 1288fb04b9bSjmcneill i-cache-sets = <256>; 1298fb04b9bSjmcneill d-cache-size = <0x8000>; 1308fb04b9bSjmcneill d-cache-line-size = <64>; 1318fb04b9bSjmcneill d-cache-sets = <128>; 132f46c7ed4Sjmcneill next-level-cache = <&A53_L2>; 133f46c7ed4Sjmcneill clocks = <&scpi_dvfs 1>; 134f46c7ed4Sjmcneill cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 135f46c7ed4Sjmcneill capacity-dmips-mhz = <578>; 136f46c7ed4Sjmcneill }; 137f46c7ed4Sjmcneill 138f46c7ed4Sjmcneill A53_1: cpu@101 { 139*84c8294dSjmcneill compatible = "arm,cortex-a53"; 140f46c7ed4Sjmcneill reg = <0x0 0x101>; 141f46c7ed4Sjmcneill device_type = "cpu"; 142f46c7ed4Sjmcneill enable-method = "psci"; 1438fb04b9bSjmcneill i-cache-size = <0x8000>; 1448fb04b9bSjmcneill i-cache-line-size = <64>; 1458fb04b9bSjmcneill i-cache-sets = <256>; 1468fb04b9bSjmcneill d-cache-size = <0x8000>; 1478fb04b9bSjmcneill d-cache-line-size = <64>; 1488fb04b9bSjmcneill d-cache-sets = <128>; 149f46c7ed4Sjmcneill next-level-cache = <&A53_L2>; 150f46c7ed4Sjmcneill clocks = <&scpi_dvfs 1>; 151f46c7ed4Sjmcneill cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 152f46c7ed4Sjmcneill capacity-dmips-mhz = <578>; 153f46c7ed4Sjmcneill }; 154f46c7ed4Sjmcneill 155f46c7ed4Sjmcneill A53_2: cpu@102 { 156*84c8294dSjmcneill compatible = "arm,cortex-a53"; 157f46c7ed4Sjmcneill reg = <0x0 0x102>; 158f46c7ed4Sjmcneill device_type = "cpu"; 159f46c7ed4Sjmcneill enable-method = "psci"; 1608fb04b9bSjmcneill i-cache-size = <0x8000>; 1618fb04b9bSjmcneill i-cache-line-size = <64>; 1628fb04b9bSjmcneill i-cache-sets = <256>; 1638fb04b9bSjmcneill d-cache-size = <0x8000>; 1648fb04b9bSjmcneill d-cache-line-size = <64>; 1658fb04b9bSjmcneill d-cache-sets = <128>; 166f46c7ed4Sjmcneill next-level-cache = <&A53_L2>; 167f46c7ed4Sjmcneill clocks = <&scpi_dvfs 1>; 168f46c7ed4Sjmcneill cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 169f46c7ed4Sjmcneill capacity-dmips-mhz = <578>; 170f46c7ed4Sjmcneill }; 171f46c7ed4Sjmcneill 172f46c7ed4Sjmcneill A53_3: cpu@103 { 173*84c8294dSjmcneill compatible = "arm,cortex-a53"; 174f46c7ed4Sjmcneill reg = <0x0 0x103>; 175f46c7ed4Sjmcneill device_type = "cpu"; 176f46c7ed4Sjmcneill enable-method = "psci"; 1778fb04b9bSjmcneill i-cache-size = <0x8000>; 1788fb04b9bSjmcneill i-cache-line-size = <64>; 1798fb04b9bSjmcneill i-cache-sets = <256>; 1808fb04b9bSjmcneill d-cache-size = <0x8000>; 1818fb04b9bSjmcneill d-cache-line-size = <64>; 1828fb04b9bSjmcneill d-cache-sets = <128>; 183f46c7ed4Sjmcneill next-level-cache = <&A53_L2>; 184f46c7ed4Sjmcneill clocks = <&scpi_dvfs 1>; 185f46c7ed4Sjmcneill cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 186f46c7ed4Sjmcneill capacity-dmips-mhz = <578>; 187f46c7ed4Sjmcneill }; 188f46c7ed4Sjmcneill 189f46c7ed4Sjmcneill A57_L2: l2-cache0 { 190f46c7ed4Sjmcneill compatible = "cache"; 1918fb04b9bSjmcneill cache-size = <0x200000>; 1928fb04b9bSjmcneill cache-line-size = <64>; 1938fb04b9bSjmcneill cache-sets = <2048>; 194f46c7ed4Sjmcneill }; 195f46c7ed4Sjmcneill 196f46c7ed4Sjmcneill A53_L2: l2-cache1 { 197f46c7ed4Sjmcneill compatible = "cache"; 1988fb04b9bSjmcneill cache-size = <0x100000>; 1998fb04b9bSjmcneill cache-line-size = <64>; 2008fb04b9bSjmcneill cache-sets = <1024>; 201f46c7ed4Sjmcneill }; 202f46c7ed4Sjmcneill }; 203f46c7ed4Sjmcneill 204a27cda6cSjmcneill pmu-a57 { 205f46c7ed4Sjmcneill compatible = "arm,cortex-a57-pmu"; 206f46c7ed4Sjmcneill interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>, 207f46c7ed4Sjmcneill <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>; 208f46c7ed4Sjmcneill interrupt-affinity = <&A57_0>, 209f46c7ed4Sjmcneill <&A57_1>; 210f46c7ed4Sjmcneill }; 211f46c7ed4Sjmcneill 212a27cda6cSjmcneill pmu-a53 { 213f46c7ed4Sjmcneill compatible = "arm,cortex-a53-pmu"; 214f46c7ed4Sjmcneill interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 215f46c7ed4Sjmcneill <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 216f46c7ed4Sjmcneill <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 217f46c7ed4Sjmcneill <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 218f46c7ed4Sjmcneill interrupt-affinity = <&A53_0>, 219f46c7ed4Sjmcneill <&A53_1>, 220f46c7ed4Sjmcneill <&A53_2>, 221f46c7ed4Sjmcneill <&A53_3>; 222f46c7ed4Sjmcneill }; 223f46c7ed4Sjmcneill}; 224f46c7ed4Sjmcneill 225f46c7ed4Sjmcneill&memtimer { 226f46c7ed4Sjmcneill status = "okay"; 227f46c7ed4Sjmcneill}; 228f46c7ed4Sjmcneill 229f46c7ed4Sjmcneill&pcie_ctlr { 230f46c7ed4Sjmcneill status = "okay"; 231f46c7ed4Sjmcneill}; 232f46c7ed4Sjmcneill 233f46c7ed4Sjmcneill&etm0 { 234f46c7ed4Sjmcneill cpu = <&A57_0>; 235f46c7ed4Sjmcneill}; 236f46c7ed4Sjmcneill 237f46c7ed4Sjmcneill&etm1 { 238f46c7ed4Sjmcneill cpu = <&A57_1>; 239f46c7ed4Sjmcneill}; 240f46c7ed4Sjmcneill 241f46c7ed4Sjmcneill&etm2 { 242f46c7ed4Sjmcneill cpu = <&A53_0>; 243f46c7ed4Sjmcneill}; 244f46c7ed4Sjmcneill 245f46c7ed4Sjmcneill&etm3 { 246f46c7ed4Sjmcneill cpu = <&A53_1>; 247f46c7ed4Sjmcneill}; 248f46c7ed4Sjmcneill 249f46c7ed4Sjmcneill&etm4 { 250f46c7ed4Sjmcneill cpu = <&A53_2>; 251f46c7ed4Sjmcneill}; 252f46c7ed4Sjmcneill 253f46c7ed4Sjmcneill&etm5 { 254f46c7ed4Sjmcneill cpu = <&A53_3>; 255f46c7ed4Sjmcneill}; 256f46c7ed4Sjmcneill 257f46c7ed4Sjmcneill&big_cluster_thermal_zone { 258f46c7ed4Sjmcneill status = "okay"; 259f46c7ed4Sjmcneill}; 260f46c7ed4Sjmcneill 261f46c7ed4Sjmcneill&little_cluster_thermal_zone { 262f46c7ed4Sjmcneill status = "okay"; 263f46c7ed4Sjmcneill}; 264f46c7ed4Sjmcneill 265f46c7ed4Sjmcneill&gpu0_thermal_zone { 266f46c7ed4Sjmcneill status = "okay"; 267f46c7ed4Sjmcneill}; 268f46c7ed4Sjmcneill 269f46c7ed4Sjmcneill&gpu1_thermal_zone { 270f46c7ed4Sjmcneill status = "okay"; 271f46c7ed4Sjmcneill}; 272f46c7ed4Sjmcneill 273f46c7ed4Sjmcneill&etf0_out_port { 274f46c7ed4Sjmcneill remote-endpoint = <&csys2_funnel_in_port0>; 275f46c7ed4Sjmcneill}; 276f46c7ed4Sjmcneill 277f46c7ed4Sjmcneill&replicator_in_port0 { 278f46c7ed4Sjmcneill remote-endpoint = <&csys2_funnel_out_port>; 279f46c7ed4Sjmcneill}; 280f46c7ed4Sjmcneill 281a27cda6cSjmcneill&csys1_funnel_in_port0 { 282a27cda6cSjmcneill remote-endpoint = <&stm_out_port>; 283a27cda6cSjmcneill}; 284a27cda6cSjmcneill 285f46c7ed4Sjmcneill&stm_out_port { 286f46c7ed4Sjmcneill remote-endpoint = <&csys1_funnel_in_port0>; 287f46c7ed4Sjmcneill}; 28805c11c73Sjmcneill 28905c11c73Sjmcneill&cpu_debug0 { 29005c11c73Sjmcneill cpu = <&A57_0>; 29105c11c73Sjmcneill}; 29205c11c73Sjmcneill 29305c11c73Sjmcneill&cpu_debug1 { 29405c11c73Sjmcneill cpu = <&A57_1>; 29505c11c73Sjmcneill}; 29605c11c73Sjmcneill 29705c11c73Sjmcneill&cpu_debug2 { 29805c11c73Sjmcneill cpu = <&A53_0>; 29905c11c73Sjmcneill}; 30005c11c73Sjmcneill 30105c11c73Sjmcneill&cpu_debug3 { 30205c11c73Sjmcneill cpu = <&A53_1>; 30305c11c73Sjmcneill}; 30405c11c73Sjmcneill 30505c11c73Sjmcneill&cpu_debug4 { 30605c11c73Sjmcneill cpu = <&A53_2>; 30705c11c73Sjmcneill}; 30805c11c73Sjmcneill 30905c11c73Sjmcneill&cpu_debug5 { 31005c11c73Sjmcneill cpu = <&A53_3>; 31105c11c73Sjmcneill}; 312