1182157ecSjmcneill// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 28fb04b9bSjmcneill/* 38fb04b9bSjmcneill * Device Tree Include file for NXP Layerscape-1088A family SoC. 48fb04b9bSjmcneill * 5*9ed2a30eSjmcneill * Copyright 2017-2020 NXP 68fb04b9bSjmcneill * 78fb04b9bSjmcneill * Harninder Rai <harninder.rai@nxp.com> 88fb04b9bSjmcneill * 98fb04b9bSjmcneill */ 10*9ed2a30eSjmcneill#include <dt-bindings/clock/fsl,qoriq-clockgen.h> 118fb04b9bSjmcneill#include <dt-bindings/interrupt-controller/arm-gic.h> 1205c11c73Sjmcneill#include <dt-bindings/thermal/thermal.h> 138fb04b9bSjmcneill 148fb04b9bSjmcneill/ { 158fb04b9bSjmcneill compatible = "fsl,ls1088a"; 168fb04b9bSjmcneill interrupt-parent = <&gic>; 178fb04b9bSjmcneill #address-cells = <2>; 188fb04b9bSjmcneill #size-cells = <2>; 198fb04b9bSjmcneill 2005c11c73Sjmcneill aliases { 2105c11c73Sjmcneill crypto = &crypto; 22*9ed2a30eSjmcneill rtc1 = &ftm_alarm0; 2305c11c73Sjmcneill }; 2405c11c73Sjmcneill 258fb04b9bSjmcneill cpus { 268fb04b9bSjmcneill #address-cells = <1>; 278fb04b9bSjmcneill #size-cells = <0>; 288fb04b9bSjmcneill 298fb04b9bSjmcneill /* We have 2 clusters having 4 Cortex-A53 cores each */ 308fb04b9bSjmcneill cpu0: cpu@0 { 318fb04b9bSjmcneill device_type = "cpu"; 328fb04b9bSjmcneill compatible = "arm,cortex-a53"; 338fb04b9bSjmcneill reg = <0x0>; 34*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_CMUX 0>; 3505c11c73Sjmcneill cpu-idle-states = <&CPU_PH20>; 3605c11c73Sjmcneill #cooling-cells = <2>; 378fb04b9bSjmcneill }; 388fb04b9bSjmcneill 398fb04b9bSjmcneill cpu1: cpu@1 { 408fb04b9bSjmcneill device_type = "cpu"; 418fb04b9bSjmcneill compatible = "arm,cortex-a53"; 428fb04b9bSjmcneill reg = <0x1>; 43*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_CMUX 0>; 4405c11c73Sjmcneill cpu-idle-states = <&CPU_PH20>; 45182157ecSjmcneill #cooling-cells = <2>; 468fb04b9bSjmcneill }; 478fb04b9bSjmcneill 488fb04b9bSjmcneill cpu2: cpu@2 { 498fb04b9bSjmcneill device_type = "cpu"; 508fb04b9bSjmcneill compatible = "arm,cortex-a53"; 518fb04b9bSjmcneill reg = <0x2>; 52*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_CMUX 0>; 5305c11c73Sjmcneill cpu-idle-states = <&CPU_PH20>; 54182157ecSjmcneill #cooling-cells = <2>; 558fb04b9bSjmcneill }; 568fb04b9bSjmcneill 578fb04b9bSjmcneill cpu3: cpu@3 { 588fb04b9bSjmcneill device_type = "cpu"; 598fb04b9bSjmcneill compatible = "arm,cortex-a53"; 608fb04b9bSjmcneill reg = <0x3>; 61*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_CMUX 0>; 6205c11c73Sjmcneill cpu-idle-states = <&CPU_PH20>; 63182157ecSjmcneill #cooling-cells = <2>; 648fb04b9bSjmcneill }; 658fb04b9bSjmcneill 668fb04b9bSjmcneill cpu4: cpu@100 { 678fb04b9bSjmcneill device_type = "cpu"; 688fb04b9bSjmcneill compatible = "arm,cortex-a53"; 698fb04b9bSjmcneill reg = <0x100>; 70*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_CMUX 1>; 7105c11c73Sjmcneill cpu-idle-states = <&CPU_PH20>; 7205c11c73Sjmcneill #cooling-cells = <2>; 738fb04b9bSjmcneill }; 748fb04b9bSjmcneill 758fb04b9bSjmcneill cpu5: cpu@101 { 768fb04b9bSjmcneill device_type = "cpu"; 778fb04b9bSjmcneill compatible = "arm,cortex-a53"; 788fb04b9bSjmcneill reg = <0x101>; 79*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_CMUX 1>; 8005c11c73Sjmcneill cpu-idle-states = <&CPU_PH20>; 81182157ecSjmcneill #cooling-cells = <2>; 828fb04b9bSjmcneill }; 838fb04b9bSjmcneill 848fb04b9bSjmcneill cpu6: cpu@102 { 858fb04b9bSjmcneill device_type = "cpu"; 868fb04b9bSjmcneill compatible = "arm,cortex-a53"; 878fb04b9bSjmcneill reg = <0x102>; 88*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_CMUX 1>; 8905c11c73Sjmcneill cpu-idle-states = <&CPU_PH20>; 90182157ecSjmcneill #cooling-cells = <2>; 918fb04b9bSjmcneill }; 928fb04b9bSjmcneill 938fb04b9bSjmcneill cpu7: cpu@103 { 948fb04b9bSjmcneill device_type = "cpu"; 958fb04b9bSjmcneill compatible = "arm,cortex-a53"; 968fb04b9bSjmcneill reg = <0x103>; 97*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_CMUX 1>; 9805c11c73Sjmcneill cpu-idle-states = <&CPU_PH20>; 99182157ecSjmcneill #cooling-cells = <2>; 10005c11c73Sjmcneill }; 10105c11c73Sjmcneill 10205c11c73Sjmcneill CPU_PH20: cpu-ph20 { 10305c11c73Sjmcneill compatible = "arm,idle-state"; 10405c11c73Sjmcneill idle-state-name = "PH20"; 105cf2d964bSjmcneill arm,psci-suspend-param = <0x0>; 10605c11c73Sjmcneill entry-latency-us = <1000>; 10705c11c73Sjmcneill exit-latency-us = <1000>; 10805c11c73Sjmcneill min-residency-us = <3000>; 1098fb04b9bSjmcneill }; 1108fb04b9bSjmcneill }; 1118fb04b9bSjmcneill 1128fb04b9bSjmcneill gic: interrupt-controller@6000000 { 1138fb04b9bSjmcneill compatible = "arm,gic-v3"; 1148fb04b9bSjmcneill #interrupt-cells = <3>; 1158fb04b9bSjmcneill interrupt-controller; 1168fb04b9bSjmcneill reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 1178fb04b9bSjmcneill <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ 1188fb04b9bSjmcneill <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 1198fb04b9bSjmcneill <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 1208fb04b9bSjmcneill <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 1218fb04b9bSjmcneill interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; 1220cc12ebdSjmcneill #address-cells = <2>; 1230cc12ebdSjmcneill #size-cells = <2>; 1240cc12ebdSjmcneill ranges; 1250cc12ebdSjmcneill 1260cc12ebdSjmcneill its: gic-its@6020000 { 1270cc12ebdSjmcneill compatible = "arm,gic-v3-its"; 1280cc12ebdSjmcneill msi-controller; 1290cc12ebdSjmcneill reg = <0x0 0x6020000 0 0x20000>; 1300cc12ebdSjmcneill }; 1318fb04b9bSjmcneill }; 1328fb04b9bSjmcneill 133cf2d964bSjmcneill thermal-zones { 134*9ed2a30eSjmcneill core-cluster { 135cf2d964bSjmcneill polling-delay-passive = <1000>; 136cf2d964bSjmcneill polling-delay = <5000>; 137cf2d964bSjmcneill thermal-sensors = <&tmu 0>; 138cf2d964bSjmcneill 139cf2d964bSjmcneill trips { 140*9ed2a30eSjmcneill core_cluster_alert: core-cluster-alert { 141cf2d964bSjmcneill temperature = <85000>; 142cf2d964bSjmcneill hysteresis = <2000>; 143cf2d964bSjmcneill type = "passive"; 144cf2d964bSjmcneill }; 145cf2d964bSjmcneill 146*9ed2a30eSjmcneill core-cluster-crit { 147cf2d964bSjmcneill temperature = <95000>; 148cf2d964bSjmcneill hysteresis = <2000>; 149cf2d964bSjmcneill type = "critical"; 150cf2d964bSjmcneill }; 151cf2d964bSjmcneill }; 152cf2d964bSjmcneill 153cf2d964bSjmcneill cooling-maps { 154cf2d964bSjmcneill map0 { 155*9ed2a30eSjmcneill trip = <&core_cluster_alert>; 156cf2d964bSjmcneill cooling-device = 15784c8294dSjmcneill <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 15884c8294dSjmcneill <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 15984c8294dSjmcneill <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 16084c8294dSjmcneill <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 16184c8294dSjmcneill <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 16284c8294dSjmcneill <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 16384c8294dSjmcneill <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 16484c8294dSjmcneill <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 165cf2d964bSjmcneill }; 166cf2d964bSjmcneill }; 167cf2d964bSjmcneill }; 168*9ed2a30eSjmcneill 169*9ed2a30eSjmcneill soc { 170*9ed2a30eSjmcneill polling-delay-passive = <1000>; 171*9ed2a30eSjmcneill polling-delay = <5000>; 172*9ed2a30eSjmcneill thermal-sensors = <&tmu 1>; 173*9ed2a30eSjmcneill 174*9ed2a30eSjmcneill trips { 175*9ed2a30eSjmcneill soc-crit { 176*9ed2a30eSjmcneill temperature = <95000>; 177*9ed2a30eSjmcneill hysteresis = <2000>; 178*9ed2a30eSjmcneill type = "critical"; 179*9ed2a30eSjmcneill }; 180*9ed2a30eSjmcneill }; 181*9ed2a30eSjmcneill }; 182cf2d964bSjmcneill }; 183cf2d964bSjmcneill 1848fb04b9bSjmcneill timer { 1858fb04b9bSjmcneill compatible = "arm,armv8-timer"; 1868fb04b9bSjmcneill interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 1878fb04b9bSjmcneill <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 1888fb04b9bSjmcneill <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 1898fb04b9bSjmcneill <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 1908fb04b9bSjmcneill }; 1918fb04b9bSjmcneill 192*9ed2a30eSjmcneill pmu { 193*9ed2a30eSjmcneill compatible = "arm,cortex-a53-pmu"; 194*9ed2a30eSjmcneill interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 195*9ed2a30eSjmcneill }; 196*9ed2a30eSjmcneill 19705c11c73Sjmcneill psci { 19805c11c73Sjmcneill compatible = "arm,psci-0.2"; 19905c11c73Sjmcneill method = "smc"; 20005c11c73Sjmcneill }; 20105c11c73Sjmcneill 2028fb04b9bSjmcneill sysclk: sysclk { 2038fb04b9bSjmcneill compatible = "fixed-clock"; 2048fb04b9bSjmcneill #clock-cells = <0>; 2058fb04b9bSjmcneill clock-frequency = <100000000>; 2068fb04b9bSjmcneill clock-output-names = "sysclk"; 2078fb04b9bSjmcneill }; 2088fb04b9bSjmcneill 2098fb04b9bSjmcneill soc { 2108fb04b9bSjmcneill compatible = "simple-bus"; 2118fb04b9bSjmcneill #address-cells = <2>; 2128fb04b9bSjmcneill #size-cells = <2>; 2138fb04b9bSjmcneill ranges; 21484c8294dSjmcneill dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 2158fb04b9bSjmcneill 2168fb04b9bSjmcneill clockgen: clocking@1300000 { 2178fb04b9bSjmcneill compatible = "fsl,ls1088a-clockgen"; 2188fb04b9bSjmcneill reg = <0 0x1300000 0 0xa0000>; 2198fb04b9bSjmcneill #clock-cells = <2>; 2208fb04b9bSjmcneill clocks = <&sysclk>; 2218fb04b9bSjmcneill }; 2228fb04b9bSjmcneill 223cf2d964bSjmcneill dcfg: dcfg@1e00000 { 224cf2d964bSjmcneill compatible = "fsl,ls1088a-dcfg", "syscon"; 225cf2d964bSjmcneill reg = <0x0 0x1e00000 0x0 0x10000>; 226cf2d964bSjmcneill little-endian; 227cf2d964bSjmcneill }; 228cf2d964bSjmcneill 229*9ed2a30eSjmcneill isc: syscon@1f70000 { 230*9ed2a30eSjmcneill compatible = "fsl,ls1088a-isc", "syscon"; 231*9ed2a30eSjmcneill reg = <0x0 0x1f70000 0x0 0x10000>; 232*9ed2a30eSjmcneill little-endian; 233*9ed2a30eSjmcneill #address-cells = <1>; 234*9ed2a30eSjmcneill #size-cells = <1>; 235*9ed2a30eSjmcneill ranges = <0x0 0x0 0x1f70000 0x10000>; 236*9ed2a30eSjmcneill 237*9ed2a30eSjmcneill extirq: interrupt-controller@14 { 238*9ed2a30eSjmcneill compatible = "fsl,ls1088a-extirq"; 239*9ed2a30eSjmcneill #interrupt-cells = <2>; 240*9ed2a30eSjmcneill #address-cells = <0>; 241*9ed2a30eSjmcneill interrupt-controller; 242*9ed2a30eSjmcneill reg = <0x14 4>; 243*9ed2a30eSjmcneill interrupt-map = 244*9ed2a30eSjmcneill <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 245*9ed2a30eSjmcneill <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 246*9ed2a30eSjmcneill <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 247*9ed2a30eSjmcneill <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 248*9ed2a30eSjmcneill <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 249*9ed2a30eSjmcneill <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 250*9ed2a30eSjmcneill <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 251*9ed2a30eSjmcneill <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 252*9ed2a30eSjmcneill <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 253*9ed2a30eSjmcneill <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 254*9ed2a30eSjmcneill <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 255*9ed2a30eSjmcneill <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 256*9ed2a30eSjmcneill interrupt-map-mask = <0xffffffff 0x0>; 257*9ed2a30eSjmcneill }; 258*9ed2a30eSjmcneill }; 259*9ed2a30eSjmcneill 26005c11c73Sjmcneill tmu: tmu@1f80000 { 26105c11c73Sjmcneill compatible = "fsl,qoriq-tmu"; 26205c11c73Sjmcneill reg = <0x0 0x1f80000 0x0 0x10000>; 26305c11c73Sjmcneill interrupts = <0 23 0x4>; 264*9ed2a30eSjmcneill fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 26505c11c73Sjmcneill fsl,tmu-calibration = 26605c11c73Sjmcneill /* Calibration data group 1 */ 267*9ed2a30eSjmcneill <0x00000000 0x00000023 268*9ed2a30eSjmcneill 0x00000001 0x0000002a 269*9ed2a30eSjmcneill 0x00000002 0x00000030 270*9ed2a30eSjmcneill 0x00000003 0x00000037 271*9ed2a30eSjmcneill 0x00000004 0x0000003d 272*9ed2a30eSjmcneill 0x00000005 0x00000044 273*9ed2a30eSjmcneill 0x00000006 0x0000004a 274*9ed2a30eSjmcneill 0x00000007 0x00000051 275*9ed2a30eSjmcneill 0x00000008 0x00000057 276*9ed2a30eSjmcneill 0x00000009 0x0000005e 277*9ed2a30eSjmcneill 0x0000000a 0x00000064 278*9ed2a30eSjmcneill 0x0000000b 0x0000006b 27905c11c73Sjmcneill /* Calibration data group 2 */ 280*9ed2a30eSjmcneill 0x00010000 0x00000022 281*9ed2a30eSjmcneill 0x00010001 0x0000002a 282*9ed2a30eSjmcneill 0x00010002 0x00000032 283*9ed2a30eSjmcneill 0x00010003 0x0000003a 284*9ed2a30eSjmcneill 0x00010004 0x00000042 285*9ed2a30eSjmcneill 0x00010005 0x0000004a 286*9ed2a30eSjmcneill 0x00010006 0x00000052 287*9ed2a30eSjmcneill 0x00010007 0x0000005a 288*9ed2a30eSjmcneill 0x00010008 0x00000062 289*9ed2a30eSjmcneill 0x00010009 0x0000006a 29005c11c73Sjmcneill /* Calibration data group 3 */ 291*9ed2a30eSjmcneill 0x00020000 0x00000021 292*9ed2a30eSjmcneill 0x00020001 0x0000002b 293*9ed2a30eSjmcneill 0x00020002 0x00000035 294*9ed2a30eSjmcneill 0x00020003 0x00000040 295*9ed2a30eSjmcneill 0x00020004 0x0000004a 296*9ed2a30eSjmcneill 0x00020005 0x00000054 297*9ed2a30eSjmcneill 0x00020006 0x0000005e 29805c11c73Sjmcneill /* Calibration data group 4 */ 299*9ed2a30eSjmcneill 0x00030000 0x00000010 300*9ed2a30eSjmcneill 0x00030001 0x0000001c 301*9ed2a30eSjmcneill 0x00030002 0x00000027 302*9ed2a30eSjmcneill 0x00030003 0x00000032 303*9ed2a30eSjmcneill 0x00030004 0x0000003e 304*9ed2a30eSjmcneill 0x00030005 0x00000049 305*9ed2a30eSjmcneill 0x00030006 0x00000054 306*9ed2a30eSjmcneill 0x00030007 0x00000060>; 30705c11c73Sjmcneill little-endian; 30805c11c73Sjmcneill #thermal-sensor-cells = <1>; 30905c11c73Sjmcneill }; 31005c11c73Sjmcneill 31109fa6529Sskrll dspi: spi@2100000 { 31209fa6529Sskrll compatible = "fsl,ls1088a-dspi", 31309fa6529Sskrll "fsl,ls1021a-v1.0-dspi"; 31409fa6529Sskrll #address-cells = <1>; 31509fa6529Sskrll #size-cells = <0>; 31609fa6529Sskrll reg = <0x0 0x2100000 0x0 0x10000>; 31709fa6529Sskrll interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 31809fa6529Sskrll clock-names = "dspi"; 319*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 320*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(2)>; 32109fa6529Sskrll spi-num-chipselects = <6>; 32209fa6529Sskrll status = "disabled"; 32309fa6529Sskrll }; 32409fa6529Sskrll 3258fb04b9bSjmcneill duart0: serial@21c0500 { 3268fb04b9bSjmcneill compatible = "fsl,ns16550", "ns16550a"; 3278fb04b9bSjmcneill reg = <0x0 0x21c0500 0x0 0x100>; 328*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 329*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(4)>; 3308fb04b9bSjmcneill interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 3318fb04b9bSjmcneill status = "disabled"; 3328fb04b9bSjmcneill }; 3338fb04b9bSjmcneill 3348fb04b9bSjmcneill duart1: serial@21c0600 { 3358fb04b9bSjmcneill compatible = "fsl,ns16550", "ns16550a"; 3368fb04b9bSjmcneill reg = <0x0 0x21c0600 0x0 0x100>; 337*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 338*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(4)>; 3398fb04b9bSjmcneill interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 3408fb04b9bSjmcneill status = "disabled"; 3418fb04b9bSjmcneill }; 3428fb04b9bSjmcneill 3438fb04b9bSjmcneill gpio0: gpio@2300000 { 34409fa6529Sskrll compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 3458fb04b9bSjmcneill reg = <0x0 0x2300000 0x0 0x10000>; 3468fb04b9bSjmcneill interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 34709fa6529Sskrll little-endian; 3488fb04b9bSjmcneill gpio-controller; 3498fb04b9bSjmcneill #gpio-cells = <2>; 3508fb04b9bSjmcneill interrupt-controller; 3518fb04b9bSjmcneill #interrupt-cells = <2>; 3528fb04b9bSjmcneill }; 3538fb04b9bSjmcneill 3548fb04b9bSjmcneill gpio1: gpio@2310000 { 35509fa6529Sskrll compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 3568fb04b9bSjmcneill reg = <0x0 0x2310000 0x0 0x10000>; 3578fb04b9bSjmcneill interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 35809fa6529Sskrll little-endian; 3598fb04b9bSjmcneill gpio-controller; 3608fb04b9bSjmcneill #gpio-cells = <2>; 3618fb04b9bSjmcneill interrupt-controller; 3628fb04b9bSjmcneill #interrupt-cells = <2>; 3638fb04b9bSjmcneill }; 3648fb04b9bSjmcneill 3658fb04b9bSjmcneill gpio2: gpio@2320000 { 36609fa6529Sskrll compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 3678fb04b9bSjmcneill reg = <0x0 0x2320000 0x0 0x10000>; 3688fb04b9bSjmcneill interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 36909fa6529Sskrll little-endian; 3708fb04b9bSjmcneill gpio-controller; 3718fb04b9bSjmcneill #gpio-cells = <2>; 3728fb04b9bSjmcneill interrupt-controller; 3738fb04b9bSjmcneill #interrupt-cells = <2>; 3748fb04b9bSjmcneill }; 3758fb04b9bSjmcneill 3768fb04b9bSjmcneill gpio3: gpio@2330000 { 37709fa6529Sskrll compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 3788fb04b9bSjmcneill reg = <0x0 0x2330000 0x0 0x10000>; 3798fb04b9bSjmcneill interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 38009fa6529Sskrll little-endian; 3818fb04b9bSjmcneill gpio-controller; 3828fb04b9bSjmcneill #gpio-cells = <2>; 3838fb04b9bSjmcneill interrupt-controller; 3848fb04b9bSjmcneill #interrupt-cells = <2>; 3858fb04b9bSjmcneill }; 3868fb04b9bSjmcneill 3878fb04b9bSjmcneill ifc: ifc@2240000 { 3888fb04b9bSjmcneill compatible = "fsl,ifc", "simple-bus"; 3898fb04b9bSjmcneill reg = <0x0 0x2240000 0x0 0x20000>; 3908fb04b9bSjmcneill interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 3918fb04b9bSjmcneill little-endian; 3928fb04b9bSjmcneill #address-cells = <2>; 3938fb04b9bSjmcneill #size-cells = <1>; 3948fb04b9bSjmcneill status = "disabled"; 3958fb04b9bSjmcneill }; 3968fb04b9bSjmcneill 3978fb04b9bSjmcneill i2c0: i2c@2000000 { 3988fb04b9bSjmcneill compatible = "fsl,vf610-i2c"; 3998fb04b9bSjmcneill #address-cells = <1>; 4008fb04b9bSjmcneill #size-cells = <0>; 4018fb04b9bSjmcneill reg = <0x0 0x2000000 0x0 0x10000>; 4028fb04b9bSjmcneill interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 403*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 404*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(8)>; 4058fb04b9bSjmcneill status = "disabled"; 4068fb04b9bSjmcneill }; 4078fb04b9bSjmcneill 4088fb04b9bSjmcneill i2c1: i2c@2010000 { 4098fb04b9bSjmcneill compatible = "fsl,vf610-i2c"; 4108fb04b9bSjmcneill #address-cells = <1>; 4118fb04b9bSjmcneill #size-cells = <0>; 4128fb04b9bSjmcneill reg = <0x0 0x2010000 0x0 0x10000>; 4138fb04b9bSjmcneill interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 414*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 415*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(8)>; 4168fb04b9bSjmcneill status = "disabled"; 4178fb04b9bSjmcneill }; 4188fb04b9bSjmcneill 4198fb04b9bSjmcneill i2c2: i2c@2020000 { 4208fb04b9bSjmcneill compatible = "fsl,vf610-i2c"; 4218fb04b9bSjmcneill #address-cells = <1>; 4228fb04b9bSjmcneill #size-cells = <0>; 4238fb04b9bSjmcneill reg = <0x0 0x2020000 0x0 0x10000>; 4248fb04b9bSjmcneill interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 425*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 426*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(8)>; 4278fb04b9bSjmcneill status = "disabled"; 4288fb04b9bSjmcneill }; 4298fb04b9bSjmcneill 4308fb04b9bSjmcneill i2c3: i2c@2030000 { 4318fb04b9bSjmcneill compatible = "fsl,vf610-i2c"; 4328fb04b9bSjmcneill #address-cells = <1>; 4338fb04b9bSjmcneill #size-cells = <0>; 4348fb04b9bSjmcneill reg = <0x0 0x2030000 0x0 0x10000>; 4358fb04b9bSjmcneill interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 436*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 437*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(8)>; 438*9ed2a30eSjmcneill status = "disabled"; 439*9ed2a30eSjmcneill }; 440*9ed2a30eSjmcneill 441*9ed2a30eSjmcneill qspi: spi@20c0000 { 442*9ed2a30eSjmcneill compatible = "fsl,ls2080a-qspi"; 443*9ed2a30eSjmcneill #address-cells = <1>; 444*9ed2a30eSjmcneill #size-cells = <0>; 445*9ed2a30eSjmcneill reg = <0x0 0x20c0000 0x0 0x10000>, 446*9ed2a30eSjmcneill <0x0 0x20000000 0x0 0x10000000>; 447*9ed2a30eSjmcneill reg-names = "QuadSPI", "QuadSPI-memory"; 448*9ed2a30eSjmcneill interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 449*9ed2a30eSjmcneill clock-names = "qspi_en", "qspi"; 450*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 451*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(4)>, 452*9ed2a30eSjmcneill <&clockgen QORIQ_CLK_PLATFORM_PLL 453*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(4)>; 4548fb04b9bSjmcneill status = "disabled"; 4558fb04b9bSjmcneill }; 4568fb04b9bSjmcneill 45705c11c73Sjmcneill esdhc: esdhc@2140000 { 45805c11c73Sjmcneill compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; 45905c11c73Sjmcneill reg = <0x0 0x2140000 0x0 0x10000>; 46005c11c73Sjmcneill interrupts = <0 28 0x4>; /* Level high type */ 46105c11c73Sjmcneill clock-frequency = <0>; 462*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 46305c11c73Sjmcneill voltage-ranges = <1800 1800 3300 3300>; 46405c11c73Sjmcneill sdhci,auto-cmd12; 46505c11c73Sjmcneill little-endian; 46605c11c73Sjmcneill bus-width = <4>; 46705c11c73Sjmcneill status = "disabled"; 46805c11c73Sjmcneill }; 46905c11c73Sjmcneill 470*9ed2a30eSjmcneill usb0: usb@3100000 { 471cf2d964bSjmcneill compatible = "snps,dwc3"; 472cf2d964bSjmcneill reg = <0x0 0x3100000 0x0 0x10000>; 473cf2d964bSjmcneill interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 474cf2d964bSjmcneill dr_mode = "host"; 475cf2d964bSjmcneill snps,quirk-frame-length-adjustment = <0x20>; 476cf2d964bSjmcneill snps,dis_rxdet_inp3_quirk; 47784c8294dSjmcneill snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 478cf2d964bSjmcneill status = "disabled"; 479cf2d964bSjmcneill }; 480cf2d964bSjmcneill 481*9ed2a30eSjmcneill usb1: usb@3110000 { 482cf2d964bSjmcneill compatible = "snps,dwc3"; 483cf2d964bSjmcneill reg = <0x0 0x3110000 0x0 0x10000>; 484cf2d964bSjmcneill interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 485cf2d964bSjmcneill dr_mode = "host"; 486cf2d964bSjmcneill snps,quirk-frame-length-adjustment = <0x20>; 487cf2d964bSjmcneill snps,dis_rxdet_inp3_quirk; 488cf2d964bSjmcneill status = "disabled"; 489cf2d964bSjmcneill }; 490cf2d964bSjmcneill 4918fb04b9bSjmcneill sata: sata@3200000 { 49205c11c73Sjmcneill compatible = "fsl,ls1088a-ahci"; 49305c11c73Sjmcneill reg = <0x0 0x3200000 0x0 0x10000>, 49405c11c73Sjmcneill <0x7 0x100520 0x0 0x4>; 49505c11c73Sjmcneill reg-names = "ahci", "sata-ecc"; 4968fb04b9bSjmcneill interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; 497*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 498*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(4)>; 49905c11c73Sjmcneill dma-coherent; 5008fb04b9bSjmcneill status = "disabled"; 5018fb04b9bSjmcneill }; 50205c11c73Sjmcneill 50305c11c73Sjmcneill crypto: crypto@8000000 { 50405c11c73Sjmcneill compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 50505c11c73Sjmcneill fsl,sec-era = <8>; 50605c11c73Sjmcneill #address-cells = <1>; 50705c11c73Sjmcneill #size-cells = <1>; 50805c11c73Sjmcneill ranges = <0x0 0x00 0x8000000 0x100000>; 50905c11c73Sjmcneill reg = <0x00 0x8000000 0x0 0x100000>; 51005c11c73Sjmcneill interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 51105c11c73Sjmcneill dma-coherent; 51205c11c73Sjmcneill 51305c11c73Sjmcneill sec_jr0: jr@10000 { 51405c11c73Sjmcneill compatible = "fsl,sec-v5.0-job-ring", 51505c11c73Sjmcneill "fsl,sec-v4.0-job-ring"; 51605c11c73Sjmcneill reg = <0x10000 0x10000>; 51705c11c73Sjmcneill interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 51805c11c73Sjmcneill }; 51905c11c73Sjmcneill 52005c11c73Sjmcneill sec_jr1: jr@20000 { 52105c11c73Sjmcneill compatible = "fsl,sec-v5.0-job-ring", 52205c11c73Sjmcneill "fsl,sec-v4.0-job-ring"; 52305c11c73Sjmcneill reg = <0x20000 0x10000>; 52405c11c73Sjmcneill interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 52505c11c73Sjmcneill }; 52605c11c73Sjmcneill 52705c11c73Sjmcneill sec_jr2: jr@30000 { 52805c11c73Sjmcneill compatible = "fsl,sec-v5.0-job-ring", 52905c11c73Sjmcneill "fsl,sec-v4.0-job-ring"; 53005c11c73Sjmcneill reg = <0x30000 0x10000>; 53105c11c73Sjmcneill interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 53205c11c73Sjmcneill }; 53305c11c73Sjmcneill 53405c11c73Sjmcneill sec_jr3: jr@40000 { 53505c11c73Sjmcneill compatible = "fsl,sec-v5.0-job-ring", 53605c11c73Sjmcneill "fsl,sec-v4.0-job-ring"; 53705c11c73Sjmcneill reg = <0x40000 0x10000>; 53805c11c73Sjmcneill interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 53905c11c73Sjmcneill }; 54005c11c73Sjmcneill }; 5410cc12ebdSjmcneill 542*9ed2a30eSjmcneill pcie1: pcie@3400000 { 54384c8294dSjmcneill compatible = "fsl,ls1088a-pcie"; 544*9ed2a30eSjmcneill reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 545*9ed2a30eSjmcneill <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 5460cc12ebdSjmcneill reg-names = "regs", "config"; 5470cc12ebdSjmcneill interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 5480cc12ebdSjmcneill interrupt-names = "aer"; 5490cc12ebdSjmcneill #address-cells = <3>; 5500cc12ebdSjmcneill #size-cells = <2>; 5510cc12ebdSjmcneill device_type = "pci"; 5520cc12ebdSjmcneill dma-coherent; 55384c8294dSjmcneill num-viewport = <256>; 5540cc12ebdSjmcneill bus-range = <0x0 0xff>; 5550cc12ebdSjmcneill ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ 5560cc12ebdSjmcneill 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 5570cc12ebdSjmcneill msi-parent = <&its>; 5580cc12ebdSjmcneill #interrupt-cells = <1>; 5590cc12ebdSjmcneill interrupt-map-mask = <0 0 0 7>; 5600cc12ebdSjmcneill interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, 5610cc12ebdSjmcneill <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, 5620cc12ebdSjmcneill <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, 5630cc12ebdSjmcneill <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; 564*9ed2a30eSjmcneill iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 56584c8294dSjmcneill status = "disabled"; 5660cc12ebdSjmcneill }; 5670cc12ebdSjmcneill 568*9ed2a30eSjmcneill pcie_ep1: pcie-ep@3400000 { 569*9ed2a30eSjmcneill compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; 570*9ed2a30eSjmcneill reg = <0x00 0x03400000 0x0 0x00100000>, 571*9ed2a30eSjmcneill <0x20 0x00000000 0x8 0x00000000>; 572*9ed2a30eSjmcneill reg-names = "regs", "addr_space"; 573*9ed2a30eSjmcneill num-ib-windows = <24>; 574*9ed2a30eSjmcneill num-ob-windows = <256>; 575*9ed2a30eSjmcneill max-functions = /bits/ 8 <2>; 576*9ed2a30eSjmcneill status = "disabled"; 577*9ed2a30eSjmcneill }; 578*9ed2a30eSjmcneill 579*9ed2a30eSjmcneill pcie2: pcie@3500000 { 58084c8294dSjmcneill compatible = "fsl,ls1088a-pcie"; 581*9ed2a30eSjmcneill reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 582*9ed2a30eSjmcneill <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 5830cc12ebdSjmcneill reg-names = "regs", "config"; 5840cc12ebdSjmcneill interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 5850cc12ebdSjmcneill interrupt-names = "aer"; 5860cc12ebdSjmcneill #address-cells = <3>; 5870cc12ebdSjmcneill #size-cells = <2>; 5880cc12ebdSjmcneill device_type = "pci"; 5890cc12ebdSjmcneill dma-coherent; 59084c8294dSjmcneill num-viewport = <6>; 5910cc12ebdSjmcneill bus-range = <0x0 0xff>; 5920cc12ebdSjmcneill ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ 5930cc12ebdSjmcneill 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 5940cc12ebdSjmcneill msi-parent = <&its>; 5950cc12ebdSjmcneill #interrupt-cells = <1>; 5960cc12ebdSjmcneill interrupt-map-mask = <0 0 0 7>; 5970cc12ebdSjmcneill interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, 5980cc12ebdSjmcneill <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, 5990cc12ebdSjmcneill <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, 6000cc12ebdSjmcneill <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; 601*9ed2a30eSjmcneill iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 60284c8294dSjmcneill status = "disabled"; 6030cc12ebdSjmcneill }; 6040cc12ebdSjmcneill 605*9ed2a30eSjmcneill pcie_ep2: pcie-ep@3500000 { 606*9ed2a30eSjmcneill compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; 607*9ed2a30eSjmcneill reg = <0x00 0x03500000 0x0 0x00100000>, 608*9ed2a30eSjmcneill <0x28 0x00000000 0x8 0x00000000>; 609*9ed2a30eSjmcneill reg-names = "regs", "addr_space"; 610*9ed2a30eSjmcneill num-ib-windows = <6>; 611*9ed2a30eSjmcneill num-ob-windows = <6>; 612*9ed2a30eSjmcneill status = "disabled"; 613*9ed2a30eSjmcneill }; 614*9ed2a30eSjmcneill 615*9ed2a30eSjmcneill pcie3: pcie@3600000 { 61684c8294dSjmcneill compatible = "fsl,ls1088a-pcie"; 617*9ed2a30eSjmcneill reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 618*9ed2a30eSjmcneill <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 6190cc12ebdSjmcneill reg-names = "regs", "config"; 6200cc12ebdSjmcneill interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 6210cc12ebdSjmcneill interrupt-names = "aer"; 6220cc12ebdSjmcneill #address-cells = <3>; 6230cc12ebdSjmcneill #size-cells = <2>; 6240cc12ebdSjmcneill device_type = "pci"; 6250cc12ebdSjmcneill dma-coherent; 62684c8294dSjmcneill num-viewport = <6>; 6270cc12ebdSjmcneill bus-range = <0x0 0xff>; 6280cc12ebdSjmcneill ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ 6290cc12ebdSjmcneill 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 6300cc12ebdSjmcneill msi-parent = <&its>; 6310cc12ebdSjmcneill #interrupt-cells = <1>; 6320cc12ebdSjmcneill interrupt-map-mask = <0 0 0 7>; 6330cc12ebdSjmcneill interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, 6340cc12ebdSjmcneill <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, 6350cc12ebdSjmcneill <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, 6360cc12ebdSjmcneill <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; 637*9ed2a30eSjmcneill iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ 638*9ed2a30eSjmcneill status = "disabled"; 639*9ed2a30eSjmcneill }; 640*9ed2a30eSjmcneill 641*9ed2a30eSjmcneill pcie_ep3: pcie-ep@3600000 { 642*9ed2a30eSjmcneill compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"; 643*9ed2a30eSjmcneill reg = <0x00 0x03600000 0x0 0x00100000>, 644*9ed2a30eSjmcneill <0x30 0x00000000 0x8 0x00000000>; 645*9ed2a30eSjmcneill reg-names = "regs", "addr_space"; 646*9ed2a30eSjmcneill num-ib-windows = <6>; 647*9ed2a30eSjmcneill num-ob-windows = <6>; 64884c8294dSjmcneill status = "disabled"; 64984c8294dSjmcneill }; 65084c8294dSjmcneill 65184c8294dSjmcneill smmu: iommu@5000000 { 65284c8294dSjmcneill compatible = "arm,mmu-500"; 65384c8294dSjmcneill reg = <0 0x5000000 0 0x800000>; 65484c8294dSjmcneill #iommu-cells = <1>; 65584c8294dSjmcneill stream-match-mask = <0x7C00>; 65684c8294dSjmcneill #global-interrupts = <12>; 65784c8294dSjmcneill // global secure fault 65884c8294dSjmcneill interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 65984c8294dSjmcneill // combined secure 66084c8294dSjmcneill <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 66184c8294dSjmcneill // global non-secure fault 66284c8294dSjmcneill <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 66384c8294dSjmcneill // combined non-secure 66484c8294dSjmcneill <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 66584c8294dSjmcneill // performance counter interrupts 0-7 66684c8294dSjmcneill <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 66784c8294dSjmcneill <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 66884c8294dSjmcneill <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 66984c8294dSjmcneill <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 67084c8294dSjmcneill <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 67184c8294dSjmcneill <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 67284c8294dSjmcneill <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 67384c8294dSjmcneill <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 67484c8294dSjmcneill // per context interrupt, 64 interrupts 67584c8294dSjmcneill <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 67684c8294dSjmcneill <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 67784c8294dSjmcneill <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 67884c8294dSjmcneill <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 67984c8294dSjmcneill <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 68084c8294dSjmcneill <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 68184c8294dSjmcneill <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 68284c8294dSjmcneill <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 68384c8294dSjmcneill <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 68484c8294dSjmcneill <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 68584c8294dSjmcneill <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 68684c8294dSjmcneill <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 68784c8294dSjmcneill <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 68884c8294dSjmcneill <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 68984c8294dSjmcneill <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 69084c8294dSjmcneill <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 69184c8294dSjmcneill <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 69284c8294dSjmcneill <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 69384c8294dSjmcneill <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 69484c8294dSjmcneill <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 69584c8294dSjmcneill <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 69684c8294dSjmcneill <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 69784c8294dSjmcneill <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 69884c8294dSjmcneill <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 69984c8294dSjmcneill <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 70084c8294dSjmcneill <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 70184c8294dSjmcneill <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 70284c8294dSjmcneill <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 70384c8294dSjmcneill <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 70484c8294dSjmcneill <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 70584c8294dSjmcneill <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 70684c8294dSjmcneill <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 70784c8294dSjmcneill <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 70884c8294dSjmcneill <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 70984c8294dSjmcneill <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 71084c8294dSjmcneill <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 71184c8294dSjmcneill <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 71284c8294dSjmcneill <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 71384c8294dSjmcneill <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 71484c8294dSjmcneill <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 71584c8294dSjmcneill <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 71684c8294dSjmcneill <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 71784c8294dSjmcneill <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 71884c8294dSjmcneill <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 71984c8294dSjmcneill <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 72084c8294dSjmcneill <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 72184c8294dSjmcneill <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 72284c8294dSjmcneill <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 72384c8294dSjmcneill <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 72484c8294dSjmcneill <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 72584c8294dSjmcneill <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 72684c8294dSjmcneill <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 72784c8294dSjmcneill <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 72884c8294dSjmcneill <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 72984c8294dSjmcneill <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 73084c8294dSjmcneill <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 73184c8294dSjmcneill <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 73284c8294dSjmcneill <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 73384c8294dSjmcneill <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 73484c8294dSjmcneill <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 73584c8294dSjmcneill <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 73684c8294dSjmcneill <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 73784c8294dSjmcneill <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 73884c8294dSjmcneill <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 7390cc12ebdSjmcneill }; 740cf2d964bSjmcneill 74109fa6529Sskrll console@8340020 { 74209fa6529Sskrll compatible = "fsl,dpaa2-console"; 74309fa6529Sskrll reg = <0x00000000 0x08340020 0 0x2>; 74409fa6529Sskrll }; 74509fa6529Sskrll 74609fa6529Sskrll ptp-timer@8b95000 { 74709fa6529Sskrll compatible = "fsl,dpaa2-ptp"; 74809fa6529Sskrll reg = <0x0 0x8b95000 0x0 0x100>; 749*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 750*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(1)>; 75109fa6529Sskrll little-endian; 75209fa6529Sskrll fsl,extts-fifo; 75309fa6529Sskrll }; 75409fa6529Sskrll 755*9ed2a30eSjmcneill emdio1: mdio@8b96000 { 756*9ed2a30eSjmcneill compatible = "fsl,fman-memac-mdio"; 757*9ed2a30eSjmcneill reg = <0x0 0x8b96000 0x0 0x1000>; 758*9ed2a30eSjmcneill little-endian; 759*9ed2a30eSjmcneill #address-cells = <1>; 760*9ed2a30eSjmcneill #size-cells = <0>; 761*9ed2a30eSjmcneill status = "disabled"; 762*9ed2a30eSjmcneill }; 763*9ed2a30eSjmcneill 764*9ed2a30eSjmcneill emdio2: mdio@8b97000 { 765*9ed2a30eSjmcneill compatible = "fsl,fman-memac-mdio"; 766*9ed2a30eSjmcneill reg = <0x0 0x8b97000 0x0 0x1000>; 767*9ed2a30eSjmcneill little-endian; 768*9ed2a30eSjmcneill #address-cells = <1>; 769*9ed2a30eSjmcneill #size-cells = <0>; 770*9ed2a30eSjmcneill status = "disabled"; 771*9ed2a30eSjmcneill }; 772*9ed2a30eSjmcneill 773*9ed2a30eSjmcneill pcs_mdio1: mdio@8c07000 { 774*9ed2a30eSjmcneill compatible = "fsl,fman-memac-mdio"; 775*9ed2a30eSjmcneill reg = <0x0 0x8c07000 0x0 0x1000>; 776*9ed2a30eSjmcneill little-endian; 777*9ed2a30eSjmcneill #address-cells = <1>; 778*9ed2a30eSjmcneill #size-cells = <0>; 779*9ed2a30eSjmcneill status = "disabled"; 780*9ed2a30eSjmcneill 781*9ed2a30eSjmcneill pcs1: ethernet-phy@0 { 782*9ed2a30eSjmcneill reg = <0>; 783*9ed2a30eSjmcneill }; 784*9ed2a30eSjmcneill }; 785*9ed2a30eSjmcneill 786*9ed2a30eSjmcneill pcs_mdio2: mdio@8c0b000 { 787*9ed2a30eSjmcneill compatible = "fsl,fman-memac-mdio"; 788*9ed2a30eSjmcneill reg = <0x0 0x8c0b000 0x0 0x1000>; 789*9ed2a30eSjmcneill little-endian; 790*9ed2a30eSjmcneill #address-cells = <1>; 791*9ed2a30eSjmcneill #size-cells = <0>; 792*9ed2a30eSjmcneill status = "disabled"; 793*9ed2a30eSjmcneill 794*9ed2a30eSjmcneill pcs2: ethernet-phy@0 { 795*9ed2a30eSjmcneill reg = <0>; 796*9ed2a30eSjmcneill }; 797*9ed2a30eSjmcneill }; 798*9ed2a30eSjmcneill 799*9ed2a30eSjmcneill pcs_mdio3: mdio@8c0f000 { 800*9ed2a30eSjmcneill compatible = "fsl,fman-memac-mdio"; 801*9ed2a30eSjmcneill reg = <0x0 0x8c0f000 0x0 0x1000>; 802*9ed2a30eSjmcneill little-endian; 803*9ed2a30eSjmcneill #address-cells = <1>; 804*9ed2a30eSjmcneill #size-cells = <0>; 805*9ed2a30eSjmcneill status = "disabled"; 806*9ed2a30eSjmcneill 807*9ed2a30eSjmcneill pcs3_0: ethernet-phy@0 { 808*9ed2a30eSjmcneill reg = <0>; 809*9ed2a30eSjmcneill }; 810*9ed2a30eSjmcneill 811*9ed2a30eSjmcneill pcs3_1: ethernet-phy@1 { 812*9ed2a30eSjmcneill reg = <1>; 813*9ed2a30eSjmcneill }; 814*9ed2a30eSjmcneill 815*9ed2a30eSjmcneill pcs3_2: ethernet-phy@2 { 816*9ed2a30eSjmcneill reg = <2>; 817*9ed2a30eSjmcneill }; 818*9ed2a30eSjmcneill 819*9ed2a30eSjmcneill pcs3_3: ethernet-phy@3 { 820*9ed2a30eSjmcneill reg = <3>; 821*9ed2a30eSjmcneill }; 822*9ed2a30eSjmcneill }; 823*9ed2a30eSjmcneill 824*9ed2a30eSjmcneill pcs_mdio7: mdio@8c1f000 { 825*9ed2a30eSjmcneill compatible = "fsl,fman-memac-mdio"; 826*9ed2a30eSjmcneill reg = <0x0 0x8c1f000 0x0 0x1000>; 827*9ed2a30eSjmcneill little-endian; 828*9ed2a30eSjmcneill #address-cells = <1>; 829*9ed2a30eSjmcneill #size-cells = <0>; 830*9ed2a30eSjmcneill status = "disabled"; 831*9ed2a30eSjmcneill 832*9ed2a30eSjmcneill pcs7_0: ethernet-phy@0 { 833*9ed2a30eSjmcneill reg = <0>; 834*9ed2a30eSjmcneill }; 835*9ed2a30eSjmcneill 836*9ed2a30eSjmcneill pcs7_1: ethernet-phy@1 { 837*9ed2a30eSjmcneill reg = <1>; 838*9ed2a30eSjmcneill }; 839*9ed2a30eSjmcneill 840*9ed2a30eSjmcneill pcs7_2: ethernet-phy@2 { 841*9ed2a30eSjmcneill reg = <2>; 842*9ed2a30eSjmcneill }; 843*9ed2a30eSjmcneill 844*9ed2a30eSjmcneill pcs7_3: ethernet-phy@3 { 845*9ed2a30eSjmcneill reg = <3>; 846*9ed2a30eSjmcneill }; 847*9ed2a30eSjmcneill }; 848*9ed2a30eSjmcneill 849cf2d964bSjmcneill cluster1_core0_watchdog: wdt@c000000 { 850cf2d964bSjmcneill compatible = "arm,sp805-wdt", "arm,primecell"; 851cf2d964bSjmcneill reg = <0x0 0xc000000 0x0 0x1000>; 852*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 853*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>, 854*9ed2a30eSjmcneill <&clockgen QORIQ_CLK_PLATFORM_PLL 855*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>; 856*9ed2a30eSjmcneill clock-names = "wdog_clk", "apb_pclk"; 857cf2d964bSjmcneill }; 858cf2d964bSjmcneill 859cf2d964bSjmcneill cluster1_core1_watchdog: wdt@c010000 { 860cf2d964bSjmcneill compatible = "arm,sp805-wdt", "arm,primecell"; 861cf2d964bSjmcneill reg = <0x0 0xc010000 0x0 0x1000>; 862*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 863*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>, 864*9ed2a30eSjmcneill <&clockgen QORIQ_CLK_PLATFORM_PLL 865*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>; 866*9ed2a30eSjmcneill clock-names = "wdog_clk", "apb_pclk"; 867cf2d964bSjmcneill }; 868cf2d964bSjmcneill 869cf2d964bSjmcneill cluster1_core2_watchdog: wdt@c020000 { 870cf2d964bSjmcneill compatible = "arm,sp805-wdt", "arm,primecell"; 871cf2d964bSjmcneill reg = <0x0 0xc020000 0x0 0x1000>; 872*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 873*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>, 874*9ed2a30eSjmcneill <&clockgen QORIQ_CLK_PLATFORM_PLL 875*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>; 876*9ed2a30eSjmcneill clock-names = "wdog_clk", "apb_pclk"; 877cf2d964bSjmcneill }; 878cf2d964bSjmcneill 879cf2d964bSjmcneill cluster1_core3_watchdog: wdt@c030000 { 880cf2d964bSjmcneill compatible = "arm,sp805-wdt", "arm,primecell"; 881cf2d964bSjmcneill reg = <0x0 0xc030000 0x0 0x1000>; 882*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 883*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>, 884*9ed2a30eSjmcneill <&clockgen QORIQ_CLK_PLATFORM_PLL 885*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>; 886*9ed2a30eSjmcneill clock-names = "wdog_clk", "apb_pclk"; 887cf2d964bSjmcneill }; 888cf2d964bSjmcneill 889cf2d964bSjmcneill cluster2_core0_watchdog: wdt@c100000 { 890cf2d964bSjmcneill compatible = "arm,sp805-wdt", "arm,primecell"; 891cf2d964bSjmcneill reg = <0x0 0xc100000 0x0 0x1000>; 892*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 893*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>, 894*9ed2a30eSjmcneill <&clockgen QORIQ_CLK_PLATFORM_PLL 895*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>; 896*9ed2a30eSjmcneill clock-names = "wdog_clk", "apb_pclk"; 897cf2d964bSjmcneill }; 898cf2d964bSjmcneill 899cf2d964bSjmcneill cluster2_core1_watchdog: wdt@c110000 { 900cf2d964bSjmcneill compatible = "arm,sp805-wdt", "arm,primecell"; 901cf2d964bSjmcneill reg = <0x0 0xc110000 0x0 0x1000>; 902*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 903*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>, 904*9ed2a30eSjmcneill <&clockgen QORIQ_CLK_PLATFORM_PLL 905*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>; 906*9ed2a30eSjmcneill clock-names = "wdog_clk", "apb_pclk"; 907cf2d964bSjmcneill }; 908cf2d964bSjmcneill 909cf2d964bSjmcneill cluster2_core2_watchdog: wdt@c120000 { 910cf2d964bSjmcneill compatible = "arm,sp805-wdt", "arm,primecell"; 911cf2d964bSjmcneill reg = <0x0 0xc120000 0x0 0x1000>; 912*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 913*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>, 914*9ed2a30eSjmcneill <&clockgen QORIQ_CLK_PLATFORM_PLL 915*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>; 916*9ed2a30eSjmcneill clock-names = "wdog_clk", "apb_pclk"; 917cf2d964bSjmcneill }; 918cf2d964bSjmcneill 919cf2d964bSjmcneill cluster2_core3_watchdog: wdt@c130000 { 920cf2d964bSjmcneill compatible = "arm,sp805-wdt", "arm,primecell"; 921cf2d964bSjmcneill reg = <0x0 0xc130000 0x0 0x1000>; 922*9ed2a30eSjmcneill clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 923*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>, 924*9ed2a30eSjmcneill <&clockgen QORIQ_CLK_PLATFORM_PLL 925*9ed2a30eSjmcneill QORIQ_CLK_PLL_DIV(16)>; 926*9ed2a30eSjmcneill clock-names = "wdog_clk", "apb_pclk"; 927cf2d964bSjmcneill }; 92884c8294dSjmcneill 92984c8294dSjmcneill fsl_mc: fsl-mc@80c000000 { 93084c8294dSjmcneill compatible = "fsl,qoriq-mc"; 93184c8294dSjmcneill reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ 93284c8294dSjmcneill <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ 93384c8294dSjmcneill msi-parent = <&its>; 93484c8294dSjmcneill iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ 93584c8294dSjmcneill dma-coherent; 93684c8294dSjmcneill #address-cells = <3>; 93784c8294dSjmcneill #size-cells = <1>; 93884c8294dSjmcneill 93984c8294dSjmcneill /* 94084c8294dSjmcneill * Region type 0x0 - MC portals 94184c8294dSjmcneill * Region type 0x1 - QBMAN portals 94284c8294dSjmcneill */ 94384c8294dSjmcneill ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 94484c8294dSjmcneill 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 94584c8294dSjmcneill 94684c8294dSjmcneill dpmacs { 94784c8294dSjmcneill #address-cells = <1>; 94884c8294dSjmcneill #size-cells = <0>; 94984c8294dSjmcneill 950*9ed2a30eSjmcneill dpmac1: ethernet@1 { 95184c8294dSjmcneill compatible = "fsl,qoriq-mc-dpmac"; 95284c8294dSjmcneill reg = <1>; 95384c8294dSjmcneill }; 95484c8294dSjmcneill 955*9ed2a30eSjmcneill dpmac2: ethernet@2 { 95684c8294dSjmcneill compatible = "fsl,qoriq-mc-dpmac"; 95784c8294dSjmcneill reg = <2>; 95884c8294dSjmcneill }; 95984c8294dSjmcneill 960*9ed2a30eSjmcneill dpmac3: ethernet@3 { 96184c8294dSjmcneill compatible = "fsl,qoriq-mc-dpmac"; 96284c8294dSjmcneill reg = <3>; 96384c8294dSjmcneill }; 96484c8294dSjmcneill 965*9ed2a30eSjmcneill dpmac4: ethernet@4 { 96684c8294dSjmcneill compatible = "fsl,qoriq-mc-dpmac"; 96784c8294dSjmcneill reg = <4>; 96884c8294dSjmcneill }; 96984c8294dSjmcneill 970*9ed2a30eSjmcneill dpmac5: ethernet@5 { 97184c8294dSjmcneill compatible = "fsl,qoriq-mc-dpmac"; 97284c8294dSjmcneill reg = <5>; 97384c8294dSjmcneill }; 97484c8294dSjmcneill 975*9ed2a30eSjmcneill dpmac6: ethernet@6 { 97684c8294dSjmcneill compatible = "fsl,qoriq-mc-dpmac"; 97784c8294dSjmcneill reg = <6>; 97884c8294dSjmcneill }; 97984c8294dSjmcneill 980*9ed2a30eSjmcneill dpmac7: ethernet@7 { 98184c8294dSjmcneill compatible = "fsl,qoriq-mc-dpmac"; 98284c8294dSjmcneill reg = <7>; 98384c8294dSjmcneill }; 98484c8294dSjmcneill 985*9ed2a30eSjmcneill dpmac8: ethernet@8 { 98684c8294dSjmcneill compatible = "fsl,qoriq-mc-dpmac"; 98784c8294dSjmcneill reg = <8>; 98884c8294dSjmcneill }; 98984c8294dSjmcneill 990*9ed2a30eSjmcneill dpmac9: ethernet@9 { 99184c8294dSjmcneill compatible = "fsl,qoriq-mc-dpmac"; 99284c8294dSjmcneill reg = <9>; 99384c8294dSjmcneill }; 99484c8294dSjmcneill 995*9ed2a30eSjmcneill dpmac10: ethernet@a { 99684c8294dSjmcneill compatible = "fsl,qoriq-mc-dpmac"; 99784c8294dSjmcneill reg = <0xa>; 99884c8294dSjmcneill }; 99984c8294dSjmcneill }; 100084c8294dSjmcneill }; 1001*9ed2a30eSjmcneill 1002*9ed2a30eSjmcneill rcpm: power-controller@1e34040 { 1003*9ed2a30eSjmcneill compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+"; 1004*9ed2a30eSjmcneill reg = <0x0 0x1e34040 0x0 0x18>; 1005*9ed2a30eSjmcneill #fsl,rcpm-wakeup-cells = <6>; 1006*9ed2a30eSjmcneill little-endian; 1007*9ed2a30eSjmcneill }; 1008*9ed2a30eSjmcneill 1009*9ed2a30eSjmcneill ftm_alarm0: timer@2800000 { 1010*9ed2a30eSjmcneill compatible = "fsl,ls1088a-ftm-alarm"; 1011*9ed2a30eSjmcneill reg = <0x0 0x2800000 0x0 0x10000>; 1012*9ed2a30eSjmcneill fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; 1013*9ed2a30eSjmcneill interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1014*9ed2a30eSjmcneill }; 10150cc12ebdSjmcneill }; 10160cc12ebdSjmcneill 10170cc12ebdSjmcneill firmware { 10180cc12ebdSjmcneill optee { 10190cc12ebdSjmcneill compatible = "linaro,optee-tz"; 10200cc12ebdSjmcneill method = "smc"; 10210cc12ebdSjmcneill }; 10228fb04b9bSjmcneill }; 10238fb04b9bSjmcneill}; 1024