1cf2d964bSjmcneill// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2f46c7ed4Sjmcneill/* 3f46c7ed4Sjmcneill * Copyright (C) 2016 Marvell Technology Group Ltd. 4f46c7ed4Sjmcneill * 5f46c7ed4Sjmcneill * Device Tree file for Marvell Armada AP806. 6f46c7ed4Sjmcneill */ 7f46c7ed4Sjmcneill 8f46c7ed4Sjmcneill#include "armada-ap806.dtsi" 9f46c7ed4Sjmcneill 10f46c7ed4Sjmcneill/ { 11f46c7ed4Sjmcneill model = "Marvell Armada AP806 Quad"; 12f46c7ed4Sjmcneill compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; 13f46c7ed4Sjmcneill 14f46c7ed4Sjmcneill cpus { 15f46c7ed4Sjmcneill #address-cells = <1>; 16f46c7ed4Sjmcneill #size-cells = <0>; 17f46c7ed4Sjmcneill 18182157ecSjmcneill cpu0: cpu@0 { 19f46c7ed4Sjmcneill device_type = "cpu"; 2084c8294dSjmcneill compatible = "arm,cortex-a72"; 21f46c7ed4Sjmcneill reg = <0x000>; 22f46c7ed4Sjmcneill enable-method = "psci"; 23*09fa6529Sskrll #cooling-cells = <2>; 24*09fa6529Sskrll clocks = <&cpu_clk 0>; 25*09fa6529Sskrll i-cache-size = <0xc000>; 26*09fa6529Sskrll i-cache-line-size = <64>; 27*09fa6529Sskrll i-cache-sets = <256>; 28*09fa6529Sskrll d-cache-size = <0x8000>; 29*09fa6529Sskrll d-cache-line-size = <64>; 30*09fa6529Sskrll d-cache-sets = <256>; 31*09fa6529Sskrll next-level-cache = <&l2_0>; 32f46c7ed4Sjmcneill }; 33182157ecSjmcneill cpu1: cpu@1 { 34f46c7ed4Sjmcneill device_type = "cpu"; 3584c8294dSjmcneill compatible = "arm,cortex-a72"; 36f46c7ed4Sjmcneill reg = <0x001>; 37f46c7ed4Sjmcneill enable-method = "psci"; 38*09fa6529Sskrll #cooling-cells = <2>; 39*09fa6529Sskrll clocks = <&cpu_clk 0>; 40*09fa6529Sskrll i-cache-size = <0xc000>; 41*09fa6529Sskrll i-cache-line-size = <64>; 42*09fa6529Sskrll i-cache-sets = <256>; 43*09fa6529Sskrll d-cache-size = <0x8000>; 44*09fa6529Sskrll d-cache-line-size = <64>; 45*09fa6529Sskrll d-cache-sets = <256>; 46*09fa6529Sskrll next-level-cache = <&l2_0>; 47f46c7ed4Sjmcneill }; 48182157ecSjmcneill cpu2: cpu@100 { 49f46c7ed4Sjmcneill device_type = "cpu"; 5084c8294dSjmcneill compatible = "arm,cortex-a72"; 51f46c7ed4Sjmcneill reg = <0x100>; 52f46c7ed4Sjmcneill enable-method = "psci"; 53*09fa6529Sskrll #cooling-cells = <2>; 54*09fa6529Sskrll clocks = <&cpu_clk 1>; 55*09fa6529Sskrll i-cache-size = <0xc000>; 56*09fa6529Sskrll i-cache-line-size = <64>; 57*09fa6529Sskrll i-cache-sets = <256>; 58*09fa6529Sskrll d-cache-size = <0x8000>; 59*09fa6529Sskrll d-cache-line-size = <64>; 60*09fa6529Sskrll d-cache-sets = <256>; 61*09fa6529Sskrll next-level-cache = <&l2_1>; 62f46c7ed4Sjmcneill }; 63182157ecSjmcneill cpu3: cpu@101 { 64f46c7ed4Sjmcneill device_type = "cpu"; 6584c8294dSjmcneill compatible = "arm,cortex-a72"; 66f46c7ed4Sjmcneill reg = <0x101>; 67f46c7ed4Sjmcneill enable-method = "psci"; 68*09fa6529Sskrll #cooling-cells = <2>; 69*09fa6529Sskrll clocks = <&cpu_clk 1>; 70*09fa6529Sskrll i-cache-size = <0xc000>; 71*09fa6529Sskrll i-cache-line-size = <64>; 72*09fa6529Sskrll i-cache-sets = <256>; 73*09fa6529Sskrll d-cache-size = <0x8000>; 74*09fa6529Sskrll d-cache-line-size = <64>; 75*09fa6529Sskrll d-cache-sets = <256>; 76*09fa6529Sskrll next-level-cache = <&l2_1>; 77*09fa6529Sskrll }; 78*09fa6529Sskrll 79*09fa6529Sskrll l2_0: l2-cache0 { 80*09fa6529Sskrll compatible = "cache"; 81*09fa6529Sskrll cache-size = <0x80000>; 82*09fa6529Sskrll cache-line-size = <64>; 83*09fa6529Sskrll cache-sets = <512>; 84*09fa6529Sskrll }; 85*09fa6529Sskrll 86*09fa6529Sskrll l2_1: l2-cache1 { 87*09fa6529Sskrll compatible = "cache"; 88*09fa6529Sskrll cache-size = <0x80000>; 89*09fa6529Sskrll cache-line-size = <64>; 90*09fa6529Sskrll cache-sets = <512>; 91f46c7ed4Sjmcneill }; 92f46c7ed4Sjmcneill }; 93f46c7ed4Sjmcneill}; 94