1;; Predicate definitions for Renesas H8/300. 2;; Copyright (C) 2005 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 2, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING. If not, write to 18;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 19;; Boston, MA 02110-1301, USA. 20 21;; Return true if OP is a valid source operand for an integer move 22;; instruction. 23 24(define_predicate "general_operand_src" 25 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem") 26{ 27 if (GET_MODE (op) == mode 28 && GET_CODE (op) == MEM 29 && GET_CODE (XEXP (op, 0)) == POST_INC) 30 return 1; 31 return general_operand (op, mode); 32}) 33 34;; Return true if OP is a valid destination operand for an integer 35;; move instruction. 36 37(define_predicate "general_operand_dst" 38 (match_code "subreg,reg,mem") 39{ 40 if (GET_MODE (op) == mode 41 && GET_CODE (op) == MEM 42 && GET_CODE (XEXP (op, 0)) == PRE_DEC) 43 return 1; 44 return general_operand (op, mode); 45}) 46 47;; Likewise the second operand. 48 49(define_predicate "h8300_src_operand" 50 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem") 51{ 52 if (TARGET_H8300SX) 53 return general_operand (op, mode); 54 return nonmemory_operand (op, mode); 55}) 56 57;; Return true if OP is a suitable first operand for a general 58;; arithmetic insn such as "add". 59 60(define_predicate "h8300_dst_operand" 61 (match_code "subreg,reg,mem") 62{ 63 if (TARGET_H8300SX) 64 return nonimmediate_operand (op, mode); 65 return register_operand (op, mode); 66}) 67 68;; Check that an operand is either a register or an unsigned 4-bit 69;; constant. 70 71(define_predicate "nibble_operand" 72 (match_code "const_int") 73{ 74 return (GET_CODE (op) == CONST_INT && TARGET_H8300SX 75 && INTVAL (op) >= 0 && INTVAL (op) <= 15); 76}) 77 78;; Check that an operand is either a register or an unsigned 4-bit 79;; constant. 80 81(define_predicate "reg_or_nibble_operand" 82 (match_code "const_int,subreg,reg") 83{ 84 return (nibble_operand (op, mode) || register_operand (op, mode)); 85}) 86 87;; Return true if X is a shift operation of type H8SX_SHIFT_UNARY. 88 89(define_predicate "h8sx_unary_shift_operator" 90 (match_code "ashiftrt,lshiftrt,ashift,rotate") 91{ 92 return (BINARY_P (op) && NON_COMMUTATIVE_P (op) 93 && (h8sx_classify_shift (GET_MODE (op), GET_CODE (op), XEXP (op, 1)) 94 == H8SX_SHIFT_UNARY)); 95}) 96 97;; Likewise H8SX_SHIFT_BINARY. 98 99(define_predicate "h8sx_binary_shift_operator" 100 (match_code "ashiftrt,lshiftrt,ashift") 101{ 102 return (BINARY_P (op) && NON_COMMUTATIVE_P (op) 103 && (h8sx_classify_shift (GET_MODE (op), GET_CODE (op), XEXP (op, 1)) 104 == H8SX_SHIFT_BINARY)); 105}) 106 107;; Return true if OP is a binary operator in which it would be safe to 108;; replace register operands with memory operands. 109 110(define_predicate "h8sx_binary_memory_operator" 111 (match_code "plus,minus,and,ior,xor,ashift,ashiftrt,lshiftrt,rotate") 112{ 113 if (!TARGET_H8300SX) 114 return false; 115 116 if (GET_MODE (op) != QImode 117 && GET_MODE (op) != HImode 118 && GET_MODE (op) != SImode) 119 return false; 120 121 switch (GET_CODE (op)) 122 { 123 case PLUS: 124 case MINUS: 125 case AND: 126 case IOR: 127 case XOR: 128 return true; 129 130 default: 131 return h8sx_unary_shift_operator (op, mode); 132 } 133}) 134 135;; Like h8sx_binary_memory_operator, but applies to unary operators. 136 137(define_predicate "h8sx_unary_memory_operator" 138 (match_code "neg,not") 139{ 140 if (!TARGET_H8300SX) 141 return false; 142 143 if (GET_MODE (op) != QImode 144 && GET_MODE (op) != HImode 145 && GET_MODE (op) != SImode) 146 return false; 147 148 switch (GET_CODE (op)) 149 { 150 case NEG: 151 case NOT: 152 return true; 153 154 default: 155 return false; 156 } 157}) 158 159;; Return true if X is an ldm.l pattern. X is known to be parallel. 160 161(define_predicate "h8300_ldm_parallel" 162 (match_code "parallel") 163{ 164 return h8300_ldm_stm_parallel (XVEC (op, 0), 1, 0); 165}) 166 167;; Likewise stm.l. 168 169(define_predicate "h8300_stm_parallel" 170 (match_code "parallel") 171{ 172 return h8300_ldm_stm_parallel (XVEC (op, 0), 0, 0); 173}) 174 175;; Likewise rts/l and rte/l. Note that the .md pattern will check for 176;; the return so there's no need to do that here. 177 178(define_predicate "h8300_return_parallel" 179 (match_code "parallel") 180{ 181 return h8300_ldm_stm_parallel (XVEC (op, 0), 1, 1); 182}) 183 184;; Return true if OP is a constant that contains only one 1 in its 185;; binary representation. 186 187(define_predicate "single_one_operand" 188 (match_code "const_int") 189{ 190 if (GET_CODE (op) == CONST_INT) 191 { 192 /* We really need to do this masking because 0x80 in QImode is 193 represented as -128 for example. */ 194 if (exact_log2 (INTVAL (op) & GET_MODE_MASK (mode)) >= 0) 195 return 1; 196 } 197 198 return 0; 199}) 200 201;; Return true if OP is a constant that contains only one 0 in its 202;; binary representation. 203 204(define_predicate "single_zero_operand" 205 (match_code "const_int") 206{ 207 if (GET_CODE (op) == CONST_INT) 208 { 209 /* We really need to do this masking because 0x80 in QImode is 210 represented as -128 for example. */ 211 if (exact_log2 (~INTVAL (op) & GET_MODE_MASK (mode)) >= 0) 212 return 1; 213 } 214 215 return 0; 216}) 217 218;; Return true if OP is a valid call operand. 219 220(define_predicate "call_insn_operand" 221 (match_code "mem") 222{ 223 if (GET_CODE (op) == MEM) 224 { 225 rtx inside = XEXP (op, 0); 226 if (register_operand (inside, Pmode)) 227 return 1; 228 if (CONSTANT_ADDRESS_P (inside)) 229 return 1; 230 } 231 return 0; 232}) 233 234;; Return true if OP is a valid call operand, and OP represents an 235;; operand for a small call (4 bytes instead of 6 bytes). 236 237(define_predicate "small_call_insn_operand" 238 (match_code "mem") 239{ 240 if (GET_CODE (op) == MEM) 241 { 242 rtx inside = XEXP (op, 0); 243 244 /* Register indirect is a small call. */ 245 if (register_operand (inside, Pmode)) 246 return 1; 247 248 /* A call through the function vector is a small call too. */ 249 if (GET_CODE (inside) == SYMBOL_REF 250 && (SYMBOL_REF_FLAGS (inside) & SYMBOL_FLAG_FUNCVEC_FUNCTION)) 251 return 1; 252 } 253 /* Otherwise it's a large call. */ 254 return 0; 255}) 256 257;; Return true if OP is a valid jump operand. 258 259(define_predicate "jump_address_operand" 260 (match_code "reg,mem") 261{ 262 if (GET_CODE (op) == REG) 263 return mode == Pmode; 264 265 if (GET_CODE (op) == MEM) 266 { 267 rtx inside = XEXP (op, 0); 268 if (register_operand (inside, Pmode)) 269 return 1; 270 if (CONSTANT_ADDRESS_P (inside)) 271 return 1; 272 } 273 return 0; 274}) 275 276;; Return 1 if an addition/subtraction of a constant integer can be 277;; transformed into two consecutive adds/subs that are faster than the 278;; straightforward way. Otherwise, return 0. 279 280(define_predicate "two_insn_adds_subs_operand" 281 (match_code "const_int") 282{ 283 if (TARGET_H8300SX) 284 return 0; 285 286 if (GET_CODE (op) == CONST_INT) 287 { 288 HOST_WIDE_INT value = INTVAL (op); 289 290 /* Force VALUE to be positive so that we do not have to consider 291 the negative case. */ 292 if (value < 0) 293 value = -value; 294 if (TARGET_H8300H || TARGET_H8300S) 295 { 296 /* A constant addition/subtraction takes 2 states in QImode, 297 4 states in HImode, and 6 states in SImode. Thus, the 298 only case we can win is when SImode is used, in which 299 case, two adds/subs are used, taking 4 states. */ 300 if (mode == SImode 301 && (value == 2 + 1 302 || value == 4 + 1 303 || value == 4 + 2 304 || value == 4 + 4)) 305 return 1; 306 } 307 else 308 { 309 /* We do not profit directly by splitting addition or 310 subtraction of 3 and 4. However, since these are 311 implemented as a sequence of adds or subs, they do not 312 clobber (cc0) unlike a sequence of add.b and add.x. */ 313 if (mode == HImode 314 && (value == 2 + 1 315 || value == 2 + 2)) 316 return 1; 317 } 318 } 319 320 return 0; 321}) 322 323;; Recognize valid operands for bit-field instructions. 324 325(define_predicate "bit_operand" 326 (match_code "reg,subreg,mem") 327{ 328 /* We can accept any nonimmediate operand, except that MEM operands must 329 be limited to those that use addresses valid for the 'U' constraint. */ 330 if (!nonimmediate_operand (op, mode)) 331 return 0; 332 333 /* H8SX accepts pretty much anything here. */ 334 if (TARGET_H8300SX) 335 return 1; 336 337 /* Accept any mem during RTL generation. Otherwise, the code that does 338 insv and extzv will think that we cannot handle memory. However, 339 to avoid reload problems, we only accept 'U' MEM operands after RTL 340 generation. This means that any named pattern which uses this predicate 341 must force its operands to match 'U' before emitting RTL. */ 342 343 if (GET_CODE (op) == REG) 344 return 1; 345 if (GET_CODE (op) == SUBREG) 346 return 1; 347 return (GET_CODE (op) == MEM 348 && OK_FOR_U (op)); 349}) 350 351;; Return nonzero if OP is a MEM suitable for bit manipulation insns. 352 353(define_predicate "bit_memory_operand" 354 (match_code "mem") 355{ 356 return (GET_CODE (op) == MEM 357 && OK_FOR_U (op)); 358}) 359 360;; Return nonzero if X is a stack pointer. 361 362(define_predicate "stack_pointer_operand" 363 (match_code "reg") 364{ 365 return op == stack_pointer_rtx; 366}) 367 368;; Return nonzero if X is a constant whose absolute value is greater 369;; than 2. 370 371(define_predicate "const_int_gt_2_operand" 372 (match_code "const_int") 373{ 374 return (GET_CODE (op) == CONST_INT 375 && abs (INTVAL (op)) > 2); 376}) 377 378;; Return nonzero if X is a constant whose absolute value is no 379;; smaller than 8. 380 381(define_predicate "const_int_ge_8_operand" 382 (match_code "const_int") 383{ 384 return (GET_CODE (op) == CONST_INT 385 && abs (INTVAL (op)) >= 8); 386}) 387 388;; Return nonzero if X is a constant expressible in QImode. 389 390(define_predicate "const_int_qi_operand" 391 (match_code "const_int") 392{ 393 return (GET_CODE (op) == CONST_INT 394 && (INTVAL (op) & 0xff) == INTVAL (op)); 395}) 396 397;; Return nonzero if X is a constant expressible in HImode. 398 399(define_predicate "const_int_hi_operand" 400 (match_code "const_int") 401{ 402 return (GET_CODE (op) == CONST_INT 403 && (INTVAL (op) & 0xffff) == INTVAL (op)); 404}) 405 406;; Return nonzero if X is a constant suitable for inc/dec. 407 408(define_predicate "incdec_operand" 409 (match_code "const_int") 410{ 411 return (GET_CODE (op) == CONST_INT 412 && (CONST_OK_FOR_M (INTVAL (op)) 413 || CONST_OK_FOR_O (INTVAL (op)))); 414}) 415 416;; Recognize valid operators for bit instructions. 417 418(define_predicate "bit_operator" 419 (match_code "xor,and,ior") 420{ 421 enum rtx_code code = GET_CODE (op); 422 423 return (code == XOR 424 || code == AND 425 || code == IOR); 426}) 427 428;; Return nonzero if OP is a shift operator. 429 430(define_predicate "nshift_operator" 431 (match_code "ashiftrt,lshiftrt,ashift") 432{ 433 switch (GET_CODE (op)) 434 { 435 case ASHIFTRT: 436 case LSHIFTRT: 437 case ASHIFT: 438 return 1; 439 440 default: 441 return 0; 442 } 443}) 444 445;; Return nonzero if X is either EQ or NE. 446 447(define_predicate "eqne_operator" 448 (match_code "eq,ne") 449{ 450 enum rtx_code code = GET_CODE (op); 451 452 return (code == EQ || code == NE); 453}) 454 455;; Return nonzero if X is either GT or LE. 456 457(define_predicate "gtle_operator" 458 (match_code "gt,le,gtu,leu") 459{ 460 enum rtx_code code = GET_CODE (op); 461 462 return (code == GT || code == LE); 463}) 464 465;; Return nonzero if X is either GTU or LEU. 466 467(define_predicate "gtuleu_operator" 468 (match_code "gtu,leu") 469{ 470 enum rtx_code code = GET_CODE (op); 471 472 return (code == GTU || code == LEU); 473}) 474 475;; Return nonzero if X is either IOR or XOR. 476 477(define_predicate "iorxor_operator" 478 (match_code "ior,xor") 479{ 480 enum rtx_code code = GET_CODE (op); 481 482 return (code == IOR || code == XOR); 483}) 484