1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire. 2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING. If not, write to 19 the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20 Boston, MA 02110-1301, USA. */ 21 22 /* We need to have MOTOROLA always defined (either 0 or 1) because we use 23 if-statements and ?: on it. This way we have compile-time error checking 24 for both the MOTOROLA and MIT code paths. We do rely on the host compiler 25 to optimize away all constant tests. */ 26 #ifdef MOTOROLA 27 # undef MOTOROLA 28 # define MOTOROLA 1 /* Use the Motorola assembly syntax. */ 29 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)") 30 #else 31 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)") 32 # define MOTOROLA 0 /* Use the MIT assembly syntax. */ 33 #endif 34 35 /* Note that some other tm.h files include this one and then override 36 many of the definitions that relate to assembler syntax. */ 37 38 #define TARGET_CPU_CPP_BUILTINS() \ 39 do \ 40 { \ 41 builtin_define ("__m68k__"); \ 42 builtin_define_std ("mc68000"); \ 43 if (TARGET_68040_ONLY) \ 44 { \ 45 if (TARGET_68060) \ 46 builtin_define_std ("mc68060"); \ 47 else \ 48 builtin_define_std ("mc68040"); \ 49 } \ 50 else if (TARGET_68060) /* -m68020-60 */ \ 51 { \ 52 builtin_define_std ("mc68060"); \ 53 builtin_define_std ("mc68040"); \ 54 builtin_define_std ("mc68030"); \ 55 builtin_define_std ("mc68020"); \ 56 } \ 57 else if (TARGET_68040) /* -m68020-40 */ \ 58 { \ 59 builtin_define_std ("mc68040"); \ 60 builtin_define_std ("mc68030"); \ 61 builtin_define_std ("mc68020"); \ 62 } \ 63 else if (TARGET_68030) \ 64 builtin_define_std ("mc68030"); \ 65 else if (TARGET_68020) \ 66 builtin_define_std ("mc68020"); \ 67 if (TARGET_68881) \ 68 builtin_define ("__HAVE_68881__"); \ 69 if (TARGET_CPU32) \ 70 { \ 71 builtin_define_std ("mc68332"); \ 72 builtin_define_std ("mcpu32"); \ 73 } \ 74 if (TARGET_COLDFIRE) \ 75 builtin_define ("__mcoldfire__"); \ 76 if (TARGET_5200) \ 77 builtin_define ("__mcf5200__"); \ 78 if (TARGET_528x) \ 79 { \ 80 builtin_define ("__mcf528x__"); \ 81 builtin_define ("__mcf5200__"); \ 82 } \ 83 if (TARGET_CFV3) \ 84 { \ 85 builtin_define ("__mcf5300__"); \ 86 builtin_define ("__mcf5307__"); \ 87 } \ 88 if (TARGET_CFV4) \ 89 { \ 90 builtin_define ("__mcf5400__"); \ 91 builtin_define ("__mcf5407__"); \ 92 } \ 93 if (TARGET_CFV4E) \ 94 { \ 95 builtin_define ("__mcfv4e__"); \ 96 } \ 97 if (TARGET_CF_HWDIV) \ 98 builtin_define ("__mcfhwdiv__"); \ 99 builtin_assert ("cpu=m68k"); \ 100 builtin_assert ("machine=m68k"); \ 101 } \ 102 while (0) 103 104 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI 105 quantities. */ 106 #define INT_OP_STANDARD 0 /* .byte, .short, .long */ 107 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */ 108 #define INT_OP_NO_DOT 2 /* byte, short, long */ 109 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */ 110 111 /* Set the default. */ 112 #define INT_OP_GROUP INT_OP_DOT_WORD 113 114 /* Compile for a CPU32. A 68020 without bitfields is a good 115 heuristic for a CPU32. */ 116 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD) 117 118 /* Is the target a ColdFire? */ 119 #define MASK_COLDFIRE \ 120 (MASK_5200 | MASK_528x | MASK_CFV3 | MASK_CFV4 | MASK_CFV4E) 121 #define TARGET_COLDFIRE ((target_flags & MASK_COLDFIRE) != 0) 122 123 #define TARGET_COLDFIRE_FPU TARGET_CFV4E 124 125 #define TARGET_HARD_FLOAT (TARGET_68881 || TARGET_COLDFIRE_FPU) 126 /* Size (in bytes) of FPU registers. */ 127 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12) 128 129 130 #define OVERRIDE_OPTIONS override_options() 131 132 /* These are meant to be redefined in the host dependent files */ 133 #define SUBTARGET_OVERRIDE_OPTIONS 134 135 /* target machine storage layout */ 136 137 #define LONG_DOUBLE_TYPE_SIZE 80 138 139 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp 140 instructions, we get proper intermediate rounding, otherwise we 141 get extended precision results. */ 142 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040_ONLY || ! TARGET_68881) ? 0 : 2) 143 144 #define BITS_BIG_ENDIAN 1 145 #define BYTES_BIG_ENDIAN 1 146 #define WORDS_BIG_ENDIAN 1 147 148 #define UNITS_PER_WORD 4 149 150 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) 151 #define STACK_BOUNDARY 16 152 #define FUNCTION_BOUNDARY 16 153 #define EMPTY_FIELD_BOUNDARY 16 154 155 /* No data type wants to be aligned rounder than this. 156 Most published ABIs say that ints should be aligned on 16 bit 157 boundaries, but CPUs with 32-bit busses get better performance 158 aligned on 32-bit boundaries. ColdFires without a misalignment 159 module require 32-bit alignment. */ 160 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16) 161 162 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT) 163 164 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) 165 166 /* Define these to avoid dependence on meaning of `int'. */ 167 #define WCHAR_TYPE "long int" 168 #define WCHAR_TYPE_SIZE 32 169 170 /* Maximum number of library IDs we permit with -mid-shared-library. */ 171 #define MAX_LIBRARY_ID 255 172 173 174 /* Standard register usage. */ 175 176 /* For the m68k, we give the data registers numbers 0-7, 177 the address registers numbers 010-017 (8-15), 178 and the 68881 floating point registers numbers 020-027 (16-24). 179 We also have a fake `arg-pointer' register 030 (25) used for 180 register elimination. */ 181 #define FIRST_PSEUDO_REGISTER 25 182 183 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */ 184 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM) 185 186 /* 1 for registers that have pervasive standard uses 187 and are not available for the register allocator. 188 On the m68k, only the stack pointer is such. 189 Our fake arg-pointer is obviously fixed as well. */ 190 #define FIXED_REGISTERS \ 191 {/* Data registers. */ \ 192 0, 0, 0, 0, 0, 0, 0, 0, \ 193 \ 194 /* Address registers. */ \ 195 0, 0, 0, 0, 0, 0, 0, 1, \ 196 \ 197 /* Floating point registers \ 198 (if available). */ \ 199 0, 0, 0, 0, 0, 0, 0, 0, \ 200 \ 201 /* Arg pointer. */ \ 202 1 } 203 204 /* 1 for registers not available across function calls. 205 These must include the FIXED_REGISTERS and also any 206 registers that can be used without being saved. 207 The latter must include the registers where values are returned 208 and the register where structure-value addresses are passed. 209 Aside from that, you can include as many other registers as you like. */ 210 #define CALL_USED_REGISTERS \ 211 {/* Data registers. */ \ 212 1, 1, 0, 0, 0, 0, 0, 0, \ 213 \ 214 /* Address registers. */ \ 215 1, 1, 0, 0, 0, 0, 0, 1, \ 216 \ 217 /* Floating point registers \ 218 (if available). */ \ 219 1, 1, 0, 0, 0, 0, 0, 0, \ 220 \ 221 /* Arg pointer. */ \ 222 1 } 223 224 #define REG_ALLOC_ORDER \ 225 { /* d0/d1/a0/a1 */ \ 226 0, 1, 8, 9, \ 227 /* d2-d7 */ \ 228 2, 3, 4, 5, 6, 7, \ 229 /* a2-a7/arg */ \ 230 10, 11, 12, 13, 14, 15, 24, \ 231 /* fp0-fp7 */ \ 232 16, 17, 18, 19, 20, 21, 22, 23\ 233 } 234 235 236 /* Make sure everything's fine if we *don't* have a given processor. 237 This assumes that putting a register in fixed_regs will keep the 238 compiler's mitts completely off it. We don't bother to zero it out 239 of register classes. */ 240 #define CONDITIONAL_REGISTER_USAGE \ 241 { \ 242 int i; \ 243 HARD_REG_SET x; \ 244 if (!TARGET_HARD_FLOAT) \ 245 { \ 246 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ 247 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 248 if (TEST_HARD_REG_BIT (x, i)) \ 249 fixed_regs[i] = call_used_regs[i] = 1; \ 250 } \ 251 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 252 fixed_regs[PIC_OFFSET_TABLE_REGNUM] \ 253 = call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 254 } 255 256 /* On the m68k, ordinary registers hold 32 bits worth; 257 for the 68881 registers, a single register is always enough for 258 anything that can be stored in them at all. */ 259 #define HARD_REGNO_NREGS(REGNO, MODE) \ 260 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ 261 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 262 263 /* A C expression that is nonzero if hard register NEW_REG can be 264 considered for use as a rename register for OLD_REG register. */ 265 266 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ 267 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG) 268 269 /* Value is true if hard register REGNO can hold a value of machine-mode MODE. 270 On the 68000, the cpu registers can hold any mode except bytes in 271 address registers, the 68881 registers can hold only SFmode or DFmode. */ 272 273 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 274 m68k_regno_mode_ok ((REGNO), (MODE)) 275 276 #define MODES_TIEABLE_P(MODE1, MODE2) \ 277 (! TARGET_HARD_FLOAT \ 278 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ 279 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 280 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ 281 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))) 282 283 /* Specify the registers used for certain standard purposes. 284 The values of these macros are register numbers. */ 285 286 #define STACK_POINTER_REGNUM 15 287 288 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS 289 ABI uses %a6 for shared library calls, therefore the frame 290 pointer is shifted to %a5 on this target. */ 291 #define FRAME_POINTER_REGNUM 14 292 293 #define FRAME_POINTER_REQUIRED 0 294 295 /* Base register for access to arguments of the function. 296 * This isn't a hardware register. It will be eliminated to the 297 * stack pointer or frame pointer. 298 */ 299 #define ARG_POINTER_REGNUM 24 300 301 #define STATIC_CHAIN_REGNUM 8 302 303 /* Register in which address to store a structure value 304 is passed to a function. */ 305 #define M68K_STRUCT_VALUE_REGNUM 9 306 307 308 309 /* The m68k has three kinds of registers, so eight classes would be 310 a complete set. One of them is not needed. */ 311 enum reg_class { 312 NO_REGS, DATA_REGS, 313 ADDR_REGS, FP_REGS, 314 GENERAL_REGS, DATA_OR_FP_REGS, 315 ADDR_OR_FP_REGS, ALL_REGS, 316 LIM_REG_CLASSES }; 317 318 #define N_REG_CLASSES (int) LIM_REG_CLASSES 319 320 #define REG_CLASS_NAMES \ 321 { "NO_REGS", "DATA_REGS", \ 322 "ADDR_REGS", "FP_REGS", \ 323 "GENERAL_REGS", "DATA_OR_FP_REGS", \ 324 "ADDR_OR_FP_REGS", "ALL_REGS" } 325 326 #define REG_CLASS_CONTENTS \ 327 { \ 328 {0x00000000}, /* NO_REGS */ \ 329 {0x000000ff}, /* DATA_REGS */ \ 330 {0x0100ff00}, /* ADDR_REGS */ \ 331 {0x00ff0000}, /* FP_REGS */ \ 332 {0x0100ffff}, /* GENERAL_REGS */ \ 333 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \ 334 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \ 335 {0x01ffffff}, /* ALL_REGS */ \ 336 } 337 338 extern enum reg_class regno_reg_class[]; 339 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)]) 340 #define INDEX_REG_CLASS GENERAL_REGS 341 #define BASE_REG_CLASS ADDR_REGS 342 343 /* We do a trick here to modify the effective constraints on the 344 machine description; we zorch the constraint letters that aren't 345 appropriate for a specific target. This allows us to guarantee 346 that a specific kind of register will not be used for a given target 347 without fiddling with the register classes above. */ 348 #define REG_CLASS_FROM_LETTER(C) \ 349 ((C) == 'a' ? ADDR_REGS : \ 350 ((C) == 'd' ? DATA_REGS : \ 351 ((C) == 'f' ? (TARGET_HARD_FLOAT ? \ 352 FP_REGS : NO_REGS) : \ 353 NO_REGS))) 354 355 /* For the m68k, `I' is used for the range 1 to 8 356 allowed as immediate shift counts and in addq. 357 `J' is used for the range of signed numbers that fit in 16 bits. 358 `K' is for numbers that moveq can't handle. 359 `L' is for range -8 to -1, range of values that can be added with subq. 360 `M' is for numbers that moveq+notb can't handle. 361 'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate. 362 'O' is for 16 (for rotate using swap). 363 'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */ 364 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 365 ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ 366 (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ 367 (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \ 368 (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \ 369 (C) == 'M' ? (VALUE) < -0x100 || (VALUE) >= 0x100 : \ 370 (C) == 'N' ? (VALUE) >= 24 && (VALUE) <= 31 : \ 371 (C) == 'O' ? (VALUE) == 16 : \ 372 (C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0) 373 374 /* "G" defines all of the floating constants that are *NOT* 68881 375 constants. This is so 68881 constants get reloaded and the 376 fpmovecr is used. */ 377 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 378 ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 ) 379 380 /* `Q' means address register indirect addressing mode. 381 `S' is for operands that satisfy 'm' when -mpcrel is in effect. 382 `T' is for operands that satisfy 's' when -mpcrel is not in effect. 383 `U' is for register offset addressing. */ 384 #define EXTRA_CONSTRAINT(OP,CODE) \ 385 (((CODE) == 'S') \ 386 ? (TARGET_PCREL \ 387 && GET_CODE (OP) == MEM \ 388 && (GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ 389 || GET_CODE (XEXP (OP, 0)) == LABEL_REF \ 390 || GET_CODE (XEXP (OP, 0)) == CONST)) \ 391 : \ 392 (((CODE) == 'T') \ 393 ? ( !TARGET_PCREL \ 394 && (GET_CODE (OP) == SYMBOL_REF \ 395 || GET_CODE (OP) == LABEL_REF \ 396 || GET_CODE (OP) == CONST)) \ 397 : \ 398 (((CODE) == 'Q') \ 399 ? (GET_CODE (OP) == MEM \ 400 && GET_CODE (XEXP (OP, 0)) == REG) \ 401 : \ 402 (((CODE) == 'U') \ 403 ? (GET_CODE (OP) == MEM \ 404 && GET_CODE (XEXP (OP, 0)) == PLUS \ 405 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \ 406 && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \ 407 : \ 408 0)))) 409 410 /* On the m68k, use a data reg if possible when the 411 value is a constant in the range where moveq could be used 412 and we ensure that QImodes are reloaded into data regs. */ 413 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 414 ((GET_CODE (X) == CONST_INT \ 415 && (unsigned) (INTVAL (X) + 0x80) < 0x100 \ 416 && (CLASS) != ADDR_REGS) \ 417 ? DATA_REGS \ 418 : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \ 419 ? DATA_REGS \ 420 : (GET_CODE (X) == CONST_DOUBLE \ 421 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ 422 ? (TARGET_HARD_FLOAT && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \ 423 ? FP_REGS : NO_REGS) \ 424 : (TARGET_PCREL \ 425 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \ 426 || GET_CODE (X) == LABEL_REF)) \ 427 ? ADDR_REGS \ 428 : (CLASS)) 429 430 /* Force QImode output reloads from subregs to be allocated to data regs, 431 since QImode stores from address regs are not supported. We make the 432 assumption that if the class is not ADDR_REGS, then it must be a superset 433 of DATA_REGS. */ 434 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 435 (((MODE) == QImode && (CLASS) != ADDR_REGS) \ 436 ? DATA_REGS \ 437 : (CLASS)) 438 439 /* On the m68k, this is the size of MODE in words, 440 except in the FP regs, where a single reg is always enough. */ 441 #define CLASS_MAX_NREGS(CLASS, MODE) \ 442 ((CLASS) == FP_REGS ? 1 \ 443 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 444 445 /* Moves between fp regs and other regs are two insns. */ 446 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 447 (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ 448 || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ 449 ? 4 : 2) 450 451 /* Stack layout; function entry, exit and calling. */ 452 453 #define STACK_GROWS_DOWNWARD 454 #define FRAME_GROWS_DOWNWARD 1 455 #define STARTING_FRAME_OFFSET 0 456 457 /* On the 680x0, sp@- in a byte insn really pushes a word. 458 On the ColdFire, sp@- in a byte insn pushes just a byte. */ 459 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1) 460 461 #define FIRST_PARM_OFFSET(FNDECL) 8 462 463 /* On the 68000, the RTS insn cannot pop anything. 464 On the 68010, the RTD insn may be used to pop them if the number 465 of args is fixed, but if the number is variable then the caller 466 must pop them all. RTD can't be used for library calls now 467 because the library is compiled with the Unix compiler. 468 Use of RTD is a selectable option, since it is incompatible with 469 standard Unix calling sequences. If the option is not selected, 470 the caller must always pop the args. */ 471 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ 472 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \ 473 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ 474 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ 475 == void_type_node))) \ 476 ? (SIZE) : 0) 477 478 /* On the m68k the return value is always in D0. */ 479 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 480 gen_rtx_REG (TYPE_MODE (VALTYPE), 0) 481 482 /* On the m68k the return value is always in D0. */ 483 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) 484 485 /* On the m68k, D0 is the only register used. */ 486 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) 487 488 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for 489 more than one register. 490 XXX This macro is m68k specific and used only for m68kemb.h. */ 491 #define NEEDS_UNTYPED_CALL 0 492 493 #define PCC_STATIC_STRUCT_RETURN 494 495 /* On the m68k, all arguments are usually pushed on the stack. */ 496 #define FUNCTION_ARG_REGNO_P(N) 0 497 498 /* On the m68k, this is a single integer, which is a number of bytes 499 of arguments scanned so far. */ 500 #define CUMULATIVE_ARGS int 501 502 /* On the m68k, the offset starts at 0. */ 503 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 504 ((CUM) = 0) 505 506 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 507 ((CUM) += ((MODE) != BLKmode \ 508 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ 509 : (int_size_in_bytes (TYPE) + 3) & ~3)) 510 511 /* On the m68k all args are always pushed. */ 512 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 513 514 #define FUNCTION_PROFILER(FILE, LABELNO) \ 515 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) 516 517 #define EXIT_IGNORE_STACK 1 518 519 /* Determine if the epilogue should be output as RTL. 520 You should override this if you define FUNCTION_EXTRA_EPILOGUE. 521 522 XXX This macro is m68k-specific and only used in m68k.md. */ 523 #define USE_RETURN_INSN use_return_insn () 524 525 /* Output assembler code for a block containing the constant parts 526 of a trampoline, leaving space for the variable parts. 527 528 On the m68k, the trampoline looks like this: 529 movl #STATIC,a0 530 jmp FUNCTION 531 532 WARNING: Targets that may run on 68040+ cpus must arrange for 533 the instruction cache to be flushed. Previous incarnations of 534 the m68k trampoline code attempted to get around this by either 535 using an out-of-line transfer function or pc-relative data, but 536 the fact remains that the code to jump to the transfer function 537 or the code to load the pc-relative data needs to be flushed 538 just as much as the "variable" portion of the trampoline. 539 Recognizing that a cache flush is going to be required anyway, 540 dispense with such notions and build a smaller trampoline. 541 542 Since more instructions are required to move a template into 543 place than to create it on the spot, don't use a template. */ 544 545 #define TRAMPOLINE_SIZE 12 546 #define TRAMPOLINE_ALIGNMENT 16 547 548 /* Targets redefine this to invoke code to either flush the cache, 549 or enable stack execution (or both). */ 550 #ifndef FINALIZE_TRAMPOLINE 551 #define FINALIZE_TRAMPOLINE(TRAMP) 552 #endif 553 554 /* We generate a two-instructions program at address TRAMP : 555 movea.l &CXT,%a0 556 jmp FNADDR */ 557 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 558 { \ 559 emit_move_insn (gen_rtx_MEM (HImode, TRAMP), GEN_INT(0x207C)); \ 560 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 2)), CXT); \ 561 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), \ 562 GEN_INT(0x4EF9)); \ 563 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 8)), FNADDR); \ 564 FINALIZE_TRAMPOLINE(TRAMP); \ 565 } 566 567 /* This is the library routine that is used to transfer control from the 568 trampoline to the actual nested function. It is defined for backward 569 compatibility, for linking with object code that used the old trampoline 570 definition. 571 572 A colon is used with no explicit operands to cause the template string 573 to be scanned for %-constructs. 574 575 The function name __transfer_from_trampoline is not actually used. 576 The function definition just permits use of "asm with operands" 577 (though the operand list is empty). */ 578 #define TRANSFER_FROM_TRAMPOLINE \ 579 void \ 580 __transfer_from_trampoline () \ 581 { \ 582 register char *a0 asm ("%a0"); \ 583 asm (GLOBAL_ASM_OP "___trampoline"); \ 584 asm ("___trampoline:"); \ 585 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ 586 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \ 587 asm ("rts":); \ 588 } 589 590 /* There are two registers that can always be eliminated on the m68k. 591 The frame pointer and the arg pointer can be replaced by either the 592 hard frame pointer or to the stack pointer, depending upon the 593 circumstances. The hard frame pointer is not used before reload and 594 so it is not eligible for elimination. */ 595 #define ELIMINABLE_REGS \ 596 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 597 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \ 598 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }} 599 600 #define CAN_ELIMINATE(FROM, TO) \ 601 ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1) 602 603 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 604 (OFFSET) = m68k_initial_elimination_offset(FROM, TO) 605 606 /* Addressing modes, and classification of registers for them. */ 607 608 #define HAVE_POST_INCREMENT 1 609 #define HAVE_PRE_DECREMENT 1 610 611 /* Macros to check register numbers against specific register classes. */ 612 613 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 614 ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) 615 #define REGNO_OK_FOR_BASE_P(REGNO) \ 616 (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) 617 #define REGNO_OK_FOR_DATA_P(REGNO) \ 618 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) 619 #define REGNO_OK_FOR_FP_P(REGNO) \ 620 (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) 621 622 /* Now macros that check whether X is a register and also, 623 strictly, whether it is in a specified class. 624 625 These macros are specific to the m68k, and may be used only 626 in code for printing assembler insns and in conditions for 627 define_optimization. */ 628 629 /* 1 if X is a data register. */ 630 #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) 631 632 /* 1 if X is an fp register. */ 633 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 634 635 /* 1 if X is an address register */ 636 #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) 637 638 639 #define MAX_REGS_PER_ADDRESS 2 640 641 #define CONSTANT_ADDRESS_P(X) \ 642 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 643 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 644 || GET_CODE (X) == HIGH) 645 646 /* Nonzero if the constant value X is a legitimate general operand. 647 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 648 #define LEGITIMATE_CONSTANT_P(X) (GET_MODE (X) != XFmode) 649 650 #ifndef REG_OK_STRICT 651 #define PCREL_GENERAL_OPERAND_OK 0 652 #else 653 #define PCREL_GENERAL_OPERAND_OK (TARGET_PCREL) 654 #endif 655 656 #define LEGITIMATE_PIC_OPERAND_P(X) \ 657 (! symbolic_operand (X, VOIDmode) \ 658 || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X)) \ 659 || PCREL_GENERAL_OPERAND_OK) 660 661 #ifndef REG_OK_STRICT 662 663 /* Nonzero if X is a hard reg that can be used as an index 664 or if it is a pseudo reg. */ 665 #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) 666 /* Nonzero if X is a hard reg that can be used as a base reg 667 or if it is a pseudo reg. */ 668 #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) 669 670 #else 671 672 /* Nonzero if X is a hard reg that can be used as an index. */ 673 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 674 /* Nonzero if X is a hard reg that can be used as a base reg. */ 675 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 676 677 #endif 678 679 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 680 that is a valid memory address for an instruction. 681 The MODE argument is the machine mode for the MEM expression 682 that wants to use this address. 683 684 When generating PIC, an address involving a SYMBOL_REF is legitimate 685 if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF. 686 We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses, 687 and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF. 688 689 Likewise for a LABEL_REF when generating PIC. 690 691 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 692 693 /* Allow SUBREG everywhere we allow REG. This results in better code. It 694 also makes function inlining work when inline functions are called with 695 arguments that are SUBREGs. */ 696 697 #define LEGITIMATE_BASE_REG_P(X) \ 698 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 699 || (GET_CODE (X) == SUBREG \ 700 && GET_CODE (SUBREG_REG (X)) == REG \ 701 && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 702 703 #define INDIRECTABLE_1_ADDRESS_P(X) \ 704 ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ 705 || LEGITIMATE_BASE_REG_P (X) \ 706 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ 707 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \ 708 || (GET_CODE (X) == PLUS \ 709 && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \ 710 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 711 && (TARGET_68020 \ 712 || ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)) \ 713 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ 714 && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \ 715 || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ 716 && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) 717 718 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ 719 { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; } 720 721 /* Only labels on dispatch tables are valid for indexing from. */ 722 #define GO_IF_INDEXABLE_BASE(X, ADDR) \ 723 { rtx temp; \ 724 if (GET_CODE (X) == LABEL_REF \ 725 && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \ 726 && GET_CODE (temp) == JUMP_INSN \ 727 && (GET_CODE (PATTERN (temp)) == ADDR_VEC \ 728 || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \ 729 goto ADDR; \ 730 if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; } 731 732 #define GO_IF_INDEXING(X, ADDR) \ 733 { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ 734 { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ 735 if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ 736 { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } 737 738 #define GO_IF_INDEXED_ADDRESS(X, ADDR) \ 739 { GO_IF_INDEXING (X, ADDR); \ 740 if (GET_CODE (X) == PLUS) \ 741 { if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 742 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100)) \ 743 { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \ 744 if (GET_CODE (XEXP (X, 0)) == CONST_INT \ 745 && (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \ 746 { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } } 747 748 /* ColdFire/5200 does not allow HImode index registers. */ 749 #define LEGITIMATE_INDEX_REG_P(X) \ 750 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 751 || (! TARGET_COLDFIRE \ 752 && GET_CODE (X) == SIGN_EXTEND \ 753 && GET_CODE (XEXP (X, 0)) == REG \ 754 && GET_MODE (XEXP (X, 0)) == HImode \ 755 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ 756 || (GET_CODE (X) == SUBREG \ 757 && GET_CODE (SUBREG_REG (X)) == REG \ 758 && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) 759 760 #define LEGITIMATE_INDEX_P(X) \ 761 (LEGITIMATE_INDEX_REG_P (X) \ 762 || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \ 763 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ 764 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 765 && (INTVAL (XEXP (X, 1)) == 2 \ 766 || INTVAL (XEXP (X, 1)) == 4 \ 767 || (INTVAL (XEXP (X, 1)) == 8 \ 768 && (TARGET_CFV4E || !TARGET_COLDFIRE))))) 769 770 /* Coldfire FPU only accepts addressing modes 2-5 */ 771 #define GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 772 { if (LEGITIMATE_BASE_REG_P (X) \ 773 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ 774 && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \ 775 || ((GET_CODE (X) == PLUS) && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \ 776 && (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 777 && ((((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)))) \ 778 goto ADDR;} 779 780 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */ 781 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 782 { if (TARGET_COLDFIRE_FPU && (GET_MODE_CLASS (MODE) == MODE_FLOAT)) \ 783 { \ 784 GO_IF_COLDFIRE_FPU_LEGITIMATE_ADDRESS (MODE, X, ADDR); \ 785 } \ 786 else \ 787 { \ 788 GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ 789 GO_IF_INDEXED_ADDRESS (X, ADDR); \ 790 if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \ 791 && LEGITIMATE_INDEX_P (XEXP (X, 0)) \ 792 && GET_CODE (XEXP (X, 1)) == LABEL_REF) \ 793 goto ADDR; \ 794 }} 795 796 /* Don't call memory_address_noforce for the address to fetch 797 the switch offset. This address is ok as it stands (see above), 798 but memory_address_noforce would alter it. */ 799 #define PIC_CASE_VECTOR_ADDRESS(index) index 800 801 /* For the 68000, we handle X+REG by loading X into a register R and 802 using R+REG. R will go in an address reg and indexing will be used. 803 However, if REG is a broken-out memory address or multiplication, 804 nothing needs to be done because REG can certainly go in an address reg. */ 805 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } 806 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 807 { register int ch = (X) != (OLDX); \ 808 if (GET_CODE (X) == PLUS) \ 809 { int copied = 0; \ 810 if (GET_CODE (XEXP (X, 0)) == MULT) \ 811 { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \ 812 if (GET_CODE (XEXP (X, 1)) == MULT) \ 813 { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \ 814 if (ch && GET_CODE (XEXP (X, 1)) == REG \ 815 && GET_CODE (XEXP (X, 0)) == REG) \ 816 { if (TARGET_CFV4E && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ 817 { COPY_ONCE (X); X = force_operand (X, 0);} \ 818 goto WIN; } \ 819 if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ 820 if (GET_CODE (XEXP (X, 0)) == REG \ 821 || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ 822 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ 823 && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \ 824 { register rtx temp = gen_reg_rtx (Pmode); \ 825 register rtx val = force_operand (XEXP (X, 1), 0); \ 826 emit_move_insn (temp, val); \ 827 COPY_ONCE (X); \ 828 XEXP (X, 1) = temp; \ 829 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \ 830 && GET_CODE (XEXP (X, 0)) == REG) \ 831 X = force_operand (X, 0); \ 832 goto WIN; } \ 833 else if (GET_CODE (XEXP (X, 1)) == REG \ 834 || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ 835 && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ 836 && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \ 837 { register rtx temp = gen_reg_rtx (Pmode); \ 838 register rtx val = force_operand (XEXP (X, 0), 0); \ 839 emit_move_insn (temp, val); \ 840 COPY_ONCE (X); \ 841 XEXP (X, 0) = temp; \ 842 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \ 843 && GET_CODE (XEXP (X, 1)) == REG) \ 844 X = force_operand (X, 0); \ 845 goto WIN; }}} 846 847 /* On the 68000, only predecrement and postincrement address depend thus 848 (the amount of decrement or increment being the length of the operand). */ 849 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 850 if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL 851 852 #define CASE_VECTOR_MODE HImode 853 #define CASE_VECTOR_PC_RELATIVE 1 854 855 #define DEFAULT_SIGNED_CHAR 1 856 #define MOVE_MAX 4 857 #define SLOW_BYTE_ACCESS 0 858 859 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 860 861 #define STORE_FLAG_VALUE (-1) 862 863 #define Pmode SImode 864 #define FUNCTION_MODE QImode 865 866 867 /* Tell final.c how to eliminate redundant test instructions. */ 868 869 /* Here we define machine-dependent flags and fields in cc_status 870 (see `conditions.h'). */ 871 872 /* Set if the cc value is actually in the 68881, so a floating point 873 conditional branch must be output. */ 874 #define CC_IN_68881 04000 875 876 /* On the 68000, all the insns to store in an address register fail to 877 set the cc's. However, in some cases these instructions can make it 878 possibly invalid to use the saved cc's. In those cases we clear out 879 some or all of the saved cc's so they won't be used. */ 880 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN) 881 882 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ 883 do { if (cc_prev_status.flags & CC_IN_68881) \ 884 return FLOAT; \ 885 if (cc_prev_status.flags & CC_NO_OVERFLOW) \ 886 return NO_OV; \ 887 return NORMAL; } while (0) 888 889 /* Control the assembler format that we output. */ 890 891 #define ASM_APP_ON "#APP\n" 892 #define ASM_APP_OFF "#NO_APP\n" 893 #define TEXT_SECTION_ASM_OP "\t.text" 894 #define DATA_SECTION_ASM_OP "\t.data" 895 #define GLOBAL_ASM_OP "\t.globl\t" 896 #define REGISTER_PREFIX "" 897 #define LOCAL_LABEL_PREFIX "" 898 #define USER_LABEL_PREFIX "_" 899 #define IMMEDIATE_PREFIX "#" 900 901 #define REGISTER_NAMES \ 902 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \ 903 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \ 904 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \ 905 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \ 906 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \ 907 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \ 908 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \ 909 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \ 910 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" } 911 912 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp" 913 914 /* Return a register name by index, handling %fp nicely. 915 We don't replace %fp for targets that don't map it to %a6 916 since it may confuse GAS. */ 917 #define M68K_REGNAME(r) ( \ 918 ((FRAME_POINTER_REGNUM == 14) \ 919 && ((r) == FRAME_POINTER_REGNUM) \ 920 && frame_pointer_needed) ? \ 921 M68K_FP_REG_NAME : reg_names[(r)]) 922 923 /* On the Sun-3, the floating point registers have numbers 924 18 to 25, not 16 to 23 as they do in the compiler. */ 925 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) 926 927 /* Before the prologue, RA is at 0(%sp). */ 928 #define INCOMING_RETURN_ADDR_RTX \ 929 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 930 931 /* After the prologue, RA is at 4(AP) in the current frame. */ 932 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 933 ((COUNT) == 0 \ 934 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \ 935 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 936 937 /* We must not use the DBX register numbers for the DWARF 2 CFA column 938 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. 939 Instead use the identity mapping. */ 940 #define DWARF_FRAME_REGNUM(REG) REG 941 942 /* Before the prologue, the top of the frame is at 4(%sp). */ 943 #define INCOMING_FRAME_SP_OFFSET 4 944 945 /* Describe how we implement __builtin_eh_return. */ 946 #define EH_RETURN_DATA_REGNO(N) \ 947 ((N) < 2 ? (N) : INVALID_REGNUM) 948 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 8) 949 #define EH_RETURN_HANDLER_RTX \ 950 gen_rtx_MEM (Pmode, \ 951 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \ 952 plus_constant (EH_RETURN_STACKADJ_RTX, \ 953 UNITS_PER_WORD))) 954 955 /* Select a format to encode pointers in exception handling data. CODE 956 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 957 true if the symbol may be affected by dynamic relocations. */ 958 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 959 (flag_pic \ 960 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ 961 : DW_EH_PE_absptr) 962 963 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 964 asm_fprintf (FILE, "%U%s", NAME) 965 966 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 967 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM)) 968 969 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 970 asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO]) 971 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 972 asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO]) 973 974 /* The m68k does not use absolute case-vectors, but we must define this macro 975 anyway. */ 976 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 977 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE) 978 979 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 980 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) 981 982 /* We don't have a way to align to more than a two-byte boundary, so do the 983 best we can and don't complain. */ 984 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 985 if ((LOG) >= 1) \ 986 fprintf (FILE, "\t.even\n"); 987 988 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 989 fprintf (FILE, "\t.skip %u\n", (int)(SIZE)) 990 991 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 992 ( fputs (".comm ", (FILE)), \ 993 assemble_name ((FILE), (NAME)), \ 994 fprintf ((FILE), ",%u\n", (int)(ROUNDED))) 995 996 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 997 ( fputs (".lcomm ", (FILE)), \ 998 assemble_name ((FILE), (NAME)), \ 999 fprintf ((FILE), ",%u\n", (int)(ROUNDED))) 1000 1001 /* Output a float value (represented as a C double) as an immediate operand. 1002 This macro is m68k-specific. */ 1003 #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ 1004 do { \ 1005 if (CODE == 'f') \ 1006 { \ 1007 char dstr[30]; \ 1008 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 9, 0); \ 1009 asm_fprintf ((FILE), "%I0r%s", dstr); \ 1010 } \ 1011 else \ 1012 { \ 1013 long l; \ 1014 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ 1015 asm_fprintf ((FILE), "%I0x%lx", l); \ 1016 } \ 1017 } while (0) 1018 1019 /* Output a double value (represented as a C double) as an immediate operand. 1020 This macro is m68k-specific. */ 1021 #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ 1022 do { char dstr[30]; \ 1023 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \ 1024 asm_fprintf (FILE, "%I0r%s", dstr); \ 1025 } while (0) 1026 1027 /* Note, long double immediate operands are not actually 1028 generated by m68k.md. */ 1029 #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \ 1030 do { char dstr[30]; \ 1031 real_to_decimal (dstr, &(VALUE), sizeof (dstr), 0, 1); \ 1032 asm_fprintf (FILE, "%I0r%s", dstr); \ 1033 } while (0) 1034 1035 /* On the 68000, we use several CODE characters: 1036 '.' for dot needed in Motorola-style opcode names. 1037 '-' for an operand pushing on the stack: 1038 sp@-, -(sp) or -(%sp) depending on the style of syntax. 1039 '+' for an operand pushing on the stack: 1040 sp@+, (sp)+ or (%sp)+ depending on the style of syntax. 1041 '@' for a reference to the top word on the stack: 1042 sp@, (sp) or (%sp) depending on the style of syntax. 1043 '#' for an immediate operand prefix (# in MIT and Motorola syntax 1044 but & in SGS syntax). 1045 '!' for the fpcr register (used in some float-to-fixed conversions). 1046 '$' for the letter `s' in an op code, but only on the 68040. 1047 '&' for the letter `d' in an op code, but only on the 68040. 1048 '/' for register prefix needed by longlong.h. 1049 1050 'b' for byte insn (no effect, on the Sun; this is for the ISI). 1051 'd' to force memory addressing to be absolute, not relative. 1052 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 1053 'o' for operands to go directly to output_operand_address (bypassing 1054 print_operand_address--used only for SYMBOL_REFs under TARGET_PCREL) 1055 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), 1056 or print pair of registers as rx:ry. */ 1057 1058 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 1059 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ 1060 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ 1061 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/') 1062 1063 1064 /* See m68k.c for the m68k specific codes. */ 1065 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 1066 1067 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 1068 1069 /* Variables in m68k.c */ 1070 extern const char *m68k_library_id_string; 1071 extern int m68k_last_compare_had_fp_operands; 1072