1 //===-- ArchSpec.h ----------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_UTILITY_ARCHSPEC_H 10 #define LLDB_UTILITY_ARCHSPEC_H 11 12 #include "lldb/Utility/CompletionRequest.h" 13 #include "lldb/Utility/ConstString.h" 14 #include "lldb/lldb-enumerations.h" 15 #include "lldb/lldb-forward.h" 16 #include "lldb/lldb-private-enumerations.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/Triple.h" 19 #include <cstddef> 20 #include <cstdint> 21 #include <string> 22 23 namespace lldb_private { 24 25 /// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture 26 /// specification class. 27 /// 28 /// A class designed to be created from a cpu type and subtype, a 29 /// string representation, or an llvm::Triple. Keeping all of the conversions 30 /// of strings to architecture enumeration values confined to this class 31 /// allows new architecture support to be added easily. 32 class ArchSpec { 33 public: 34 enum MIPSSubType { 35 eMIPSSubType_unknown, 36 eMIPSSubType_mips32, 37 eMIPSSubType_mips32r2, 38 eMIPSSubType_mips32r6, 39 eMIPSSubType_mips32el, 40 eMIPSSubType_mips32r2el, 41 eMIPSSubType_mips32r6el, 42 eMIPSSubType_mips64, 43 eMIPSSubType_mips64r2, 44 eMIPSSubType_mips64r6, 45 eMIPSSubType_mips64el, 46 eMIPSSubType_mips64r2el, 47 eMIPSSubType_mips64r6el, 48 }; 49 50 // Masks for the ases word of an ABI flags structure. 51 enum MIPSASE { 52 eMIPSAse_dsp = 0x00000001, // DSP ASE 53 eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE 54 eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme 55 eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE 56 eMIPSAse_mdmx = 0x00000010, // MDMX ASE 57 eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE 58 eMIPSAse_mt = 0x00000040, // MT ASE 59 eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE 60 eMIPSAse_virt = 0x00000100, // VZ ASE 61 eMIPSAse_msa = 0x00000200, // MSA ASE 62 eMIPSAse_mips16 = 0x00000400, // MIPS16 ASE 63 eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE 64 eMIPSAse_xpa = 0x00001000, // XPA ASE 65 eMIPSAse_mask = 0x00001fff, 66 eMIPSABI_O32 = 0x00002000, 67 eMIPSABI_N32 = 0x00004000, 68 eMIPSABI_N64 = 0x00008000, 69 eMIPSABI_O64 = 0x00020000, 70 eMIPSABI_EABI32 = 0x00040000, 71 eMIPSABI_EABI64 = 0x00080000, 72 eMIPSABI_mask = 0x000ff000 73 }; 74 75 // MIPS Floating point ABI Values 76 enum MIPS_ABI_FP { 77 eMIPS_ABI_FP_ANY = 0x00000000, 78 eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float 79 eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float 80 eMIPS_ABI_FP_SOFT = 0x00300000, // soft float 81 eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64 82 eMIPS_ABI_FP_XX = 0x00500000, // -mfpxx 83 eMIPS_ABI_FP_64 = 0x00600000, // -mips32r2 -mfp64 84 eMIPS_ABI_FP_64A = 0x00700000, // -mips32r2 -mfp64 -mno-odd-spreg 85 eMIPS_ABI_FP_mask = 0x00700000 86 }; 87 88 // ARM specific e_flags 89 enum ARMeflags { 90 eARM_abi_soft_float = 0x00000200, 91 eARM_abi_hard_float = 0x00000400 92 }; 93 94 enum Core { 95 eCore_arm_generic, 96 eCore_arm_armv4, 97 eCore_arm_armv4t, 98 eCore_arm_armv5, 99 eCore_arm_armv5e, 100 eCore_arm_armv5t, 101 eCore_arm_armv6, 102 eCore_arm_armv6m, 103 eCore_arm_armv7, 104 eCore_arm_armv7l, 105 eCore_arm_armv7f, 106 eCore_arm_armv7s, 107 eCore_arm_armv7k, 108 eCore_arm_armv7m, 109 eCore_arm_armv7em, 110 eCore_arm_xscale, 111 112 eCore_thumb, 113 eCore_thumbv4t, 114 eCore_thumbv5, 115 eCore_thumbv5e, 116 eCore_thumbv6, 117 eCore_thumbv6m, 118 eCore_thumbv7, 119 eCore_thumbv7s, 120 eCore_thumbv7k, 121 eCore_thumbv7f, 122 eCore_thumbv7m, 123 eCore_thumbv7em, 124 eCore_arm_arm64, 125 eCore_arm_armv8, 126 eCore_arm_armv8l, 127 eCore_arm_arm64_32, 128 eCore_arm_aarch64, 129 130 eCore_mips32, 131 eCore_mips32r2, 132 eCore_mips32r3, 133 eCore_mips32r5, 134 eCore_mips32r6, 135 eCore_mips32el, 136 eCore_mips32r2el, 137 eCore_mips32r3el, 138 eCore_mips32r5el, 139 eCore_mips32r6el, 140 eCore_mips64, 141 eCore_mips64r2, 142 eCore_mips64r3, 143 eCore_mips64r5, 144 eCore_mips64r6, 145 eCore_mips64el, 146 eCore_mips64r2el, 147 eCore_mips64r3el, 148 eCore_mips64r5el, 149 eCore_mips64r6el, 150 151 eCore_ppc_generic, 152 eCore_ppc_ppc601, 153 eCore_ppc_ppc602, 154 eCore_ppc_ppc603, 155 eCore_ppc_ppc603e, 156 eCore_ppc_ppc603ev, 157 eCore_ppc_ppc604, 158 eCore_ppc_ppc604e, 159 eCore_ppc_ppc620, 160 eCore_ppc_ppc750, 161 eCore_ppc_ppc7400, 162 eCore_ppc_ppc7450, 163 eCore_ppc_ppc970, 164 165 eCore_ppc64le_generic, 166 eCore_ppc64_generic, 167 eCore_ppc64_ppc970_64, 168 169 eCore_s390x_generic, 170 171 eCore_sparc_generic, 172 173 eCore_sparc9_generic, 174 175 eCore_x86_32_i386, 176 eCore_x86_32_i486, 177 eCore_x86_32_i486sx, 178 eCore_x86_32_i686, 179 180 eCore_x86_64_x86_64, 181 eCore_x86_64_x86_64h, // Haswell enabled x86_64 182 eCore_x86_64_amd64, 183 eCore_hexagon_generic, 184 eCore_hexagon_hexagonv4, 185 eCore_hexagon_hexagonv5, 186 187 eCore_uknownMach32, 188 eCore_uknownMach64, 189 190 eCore_arc, // little endian ARC 191 192 kNumCores, 193 194 kCore_invalid, 195 // The following constants are used for wildcard matching only 196 kCore_any, 197 kCore_arm_any, 198 kCore_ppc_any, 199 kCore_ppc64_any, 200 kCore_x86_32_any, 201 kCore_x86_64_any, 202 kCore_hexagon_any, 203 204 kCore_arm_first = eCore_arm_generic, 205 kCore_arm_last = eCore_arm_xscale, 206 207 kCore_thumb_first = eCore_thumb, 208 kCore_thumb_last = eCore_thumbv7em, 209 210 kCore_ppc_first = eCore_ppc_generic, 211 kCore_ppc_last = eCore_ppc_ppc970, 212 213 kCore_ppc64_first = eCore_ppc64_generic, 214 kCore_ppc64_last = eCore_ppc64_ppc970_64, 215 216 kCore_x86_32_first = eCore_x86_32_i386, 217 kCore_x86_32_last = eCore_x86_32_i686, 218 219 kCore_x86_64_first = eCore_x86_64_x86_64, 220 kCore_x86_64_last = eCore_x86_64_x86_64h, 221 222 kCore_hexagon_first = eCore_hexagon_generic, 223 kCore_hexagon_last = eCore_hexagon_hexagonv5, 224 225 kCore_mips32_first = eCore_mips32, 226 kCore_mips32_last = eCore_mips32r6, 227 228 kCore_mips32el_first = eCore_mips32el, 229 kCore_mips32el_last = eCore_mips32r6el, 230 231 kCore_mips64_first = eCore_mips64, 232 kCore_mips64_last = eCore_mips64r6, 233 234 kCore_mips64el_first = eCore_mips64el, 235 kCore_mips64el_last = eCore_mips64r6el, 236 237 kCore_mips_first = eCore_mips32, 238 kCore_mips_last = eCore_mips64r6el 239 240 }; 241 242 /// Default constructor. 243 /// 244 /// Default constructor that initializes the object with invalid cpu type 245 /// and subtype values. 246 ArchSpec(); 247 248 /// Constructor over triple. 249 /// 250 /// Constructs an ArchSpec with properties consistent with the given Triple. 251 explicit ArchSpec(const llvm::Triple &triple); 252 explicit ArchSpec(const char *triple_cstr); 253 explicit ArchSpec(llvm::StringRef triple_str); 254 /// Constructor over architecture name. 255 /// 256 /// Constructs an ArchSpec with properties consistent with the given object 257 /// type and architecture name. 258 explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type, 259 uint32_t cpu_subtype); 260 261 /// Destructor. 262 ~ArchSpec(); 263 264 /// Returns true if the OS, vendor and environment fields of the triple are 265 /// unset. The triple is expected to be normalized 266 /// (llvm::Triple::normalize). 267 static bool ContainsOnlyArch(const llvm::Triple &normalized_triple); 268 269 static void ListSupportedArchNames(StringList &list); 270 static void AutoComplete(CompletionRequest &request); 271 272 /// Returns a static string representing the current architecture. 273 /// 274 /// \return A static string corresponding to the current 275 /// architecture. 276 const char *GetArchitectureName() const; 277 278 /// if MIPS architecture return true. 279 /// 280 /// \return a boolean value. 281 bool IsMIPS() const; 282 283 /// Returns a string representing current architecture as a target CPU for 284 /// tools like compiler, disassembler etc. 285 /// 286 /// \return A string representing target CPU for the current 287 /// architecture. 288 std::string GetClangTargetCPU() const; 289 290 /// Return a string representing target application ABI. 291 /// 292 /// \return A string representing target application ABI. 293 std::string GetTargetABI() const; 294 295 /// Clears the object state. 296 /// 297 /// Clears the object state back to a default invalid state. 298 void Clear(); 299 300 /// Returns the size in bytes of an address of the current architecture. 301 /// 302 /// \return The byte size of an address of the current architecture. 303 uint32_t GetAddressByteSize() const; 304 305 /// Returns a machine family for the current architecture. 306 /// 307 /// \return An LLVM arch type. 308 llvm::Triple::ArchType GetMachine() const; 309 310 /// Returns the distribution id of the architecture. 311 /// 312 /// This will be something like "ubuntu", "fedora", etc. on Linux. 313 /// 314 /// \return A ConstString ref containing the distribution id, 315 /// potentially empty. 316 ConstString GetDistributionId() const; 317 318 /// Set the distribution id of the architecture. 319 /// 320 /// This will be something like "ubuntu", "fedora", etc. on Linux. This 321 /// should be the same value returned by HostInfo::GetDistributionId (). 322 void SetDistributionId(const char *distribution_id); 323 324 /// Tests if this ArchSpec is valid. 325 /// 326 /// \return True if the current architecture is valid, false 327 /// otherwise. 328 bool IsValid() const { 329 return m_core >= eCore_arm_generic && m_core < kNumCores; 330 } 331 explicit operator bool() const { return IsValid(); } 332 333 bool TripleVendorWasSpecified() const { 334 return !m_triple.getVendorName().empty(); 335 } 336 337 bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); } 338 339 bool TripleEnvironmentWasSpecified() const { 340 return m_triple.hasEnvironment(); 341 } 342 343 /// Merges fields from another ArchSpec into this ArchSpec. 344 /// 345 /// This will use the supplied ArchSpec to fill in any fields of the triple 346 /// in this ArchSpec which were unspecified. This can be used to refine a 347 /// generic ArchSpec with a more specific one. For example, if this 348 /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we 349 /// have a triple which is x64-pc-windows-msvc, then merging that triple 350 /// into this one will result in the triple i386-pc-windows-msvc. 351 /// 352 void MergeFrom(const ArchSpec &other); 353 354 /// Change the architecture object type, CPU type and OS type. 355 /// 356 /// \param[in] arch_type The object type of this ArchSpec. 357 /// 358 /// \param[in] cpu The required CPU type. 359 /// 360 /// \param[in] os The optional OS type 361 /// The default value of 0 was chosen to from the ELF spec value 362 /// ELFOSABI_NONE. ELF is the only one using this parameter. If another 363 /// format uses this parameter and 0 does not work, use a value over 364 /// 255 because in the ELF header this is value is only a byte. 365 /// 366 /// \return True if the object, and CPU were successfully set. 367 /// 368 /// As a side effect, the vendor value is usually set to unknown. The 369 /// exceptions are 370 /// aarch64-apple-ios 371 /// arm-apple-ios 372 /// thumb-apple-ios 373 /// x86-apple- 374 /// x86_64-apple- 375 /// 376 /// As a side effect, the os value is usually set to unknown The exceptions 377 /// are 378 /// *-*-aix 379 /// aarch64-apple-ios 380 /// arm-apple-ios 381 /// thumb-apple-ios 382 /// powerpc-apple-darwin 383 /// *-*-freebsd 384 /// *-*-linux 385 /// *-*-netbsd 386 /// *-*-openbsd 387 /// *-*-solaris 388 bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, 389 uint32_t os = 0); 390 391 /// Returns the byte order for the architecture specification. 392 /// 393 /// \return The endian enumeration for the current endianness of 394 /// the architecture specification 395 lldb::ByteOrder GetByteOrder() const; 396 397 /// Sets this ArchSpec's byte order. 398 /// 399 /// In the common case there is no need to call this method as the byte 400 /// order can almost always be determined by the architecture. However, many 401 /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed 402 /// byte order may be incorrect. 403 void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; } 404 405 uint32_t GetMinimumOpcodeByteSize() const; 406 407 uint32_t GetMaximumOpcodeByteSize() const; 408 409 Core GetCore() const { return m_core; } 410 411 uint32_t GetMachOCPUType() const; 412 413 uint32_t GetMachOCPUSubType() const; 414 415 /// Architecture data byte width accessor 416 /// 417 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 418 /// from the Architecture's data bus 419 uint32_t GetDataByteSize() const; 420 421 /// Architecture code byte width accessor 422 /// 423 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 424 /// from the Architecture's code bus 425 uint32_t GetCodeByteSize() const; 426 427 /// Architecture triple accessor. 428 /// 429 /// \return A triple describing this ArchSpec. 430 llvm::Triple &GetTriple() { return m_triple; } 431 432 /// Architecture triple accessor. 433 /// 434 /// \return A triple describing this ArchSpec. 435 const llvm::Triple &GetTriple() const { return m_triple; } 436 437 void DumpTriple(llvm::raw_ostream &s) const; 438 439 /// Architecture triple setter. 440 /// 441 /// Configures this ArchSpec according to the given triple. If the triple 442 /// has unknown components in all of the vendor, OS, and the optional 443 /// environment field (i.e. "i386-unknown-unknown") then default values are 444 /// taken from the host. Architecture and environment components are used 445 /// to further resolve the CPU type and subtype, endian characteristics, 446 /// etc. 447 /// 448 /// \return A triple describing this ArchSpec. 449 bool SetTriple(const llvm::Triple &triple); 450 451 bool SetTriple(llvm::StringRef triple_str); 452 453 /// Returns the default endianness of the architecture. 454 /// 455 /// \return The endian enumeration for the default endianness of 456 /// the architecture. 457 lldb::ByteOrder GetDefaultEndian() const; 458 459 /// Returns true if 'char' is a signed type by default in the architecture 460 /// false otherwise 461 /// 462 /// \return True if 'char' is a signed type by default on the 463 /// architecture and false otherwise. 464 bool CharIsSignedByDefault() const; 465 466 /// Compare an ArchSpec to another ArchSpec, requiring an exact cpu type 467 /// match between them. e.g. armv7s is not an exact match with armv7 - this 468 /// would return false 469 /// 470 /// \return true if the two ArchSpecs match. 471 bool IsExactMatch(const ArchSpec &rhs) const; 472 473 /// Compare an ArchSpec to another ArchSpec, requiring a compatible cpu type 474 /// match between them. e.g. armv7s is compatible with armv7 - this method 475 /// would return true 476 /// 477 /// \return true if the two ArchSpecs are compatible 478 bool IsCompatibleMatch(const ArchSpec &rhs) const; 479 480 bool IsFullySpecifiedTriple() const; 481 482 void PiecewiseTripleCompare(const ArchSpec &other, bool &arch_different, 483 bool &vendor_different, bool &os_different, 484 bool &os_version_different, 485 bool &env_different) const; 486 487 /// Detect whether this architecture uses thumb code exclusively 488 /// 489 /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute 490 /// the Thumb instructions, never Arm. We should normally pick up 491 /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints 492 /// on each function - but when doing bare-boards low level debugging 493 /// (especially common with these embedded processors), we may not have 494 /// those things easily accessible. 495 /// 496 /// \return true if this is an arm ArchSpec which can only execute Thumb 497 /// instructions 498 bool IsAlwaysThumbInstructions() const; 499 500 uint32_t GetFlags() const { return m_flags; } 501 502 void SetFlags(uint32_t flags) { m_flags = flags; } 503 504 void SetFlags(std::string elf_abi); 505 506 protected: 507 bool IsEqualTo(const ArchSpec &rhs, bool exact_match) const; 508 void UpdateCore(); 509 510 llvm::Triple m_triple; 511 Core m_core = kCore_invalid; 512 lldb::ByteOrder m_byte_order = lldb::eByteOrderInvalid; 513 514 // Additional arch flags which we cannot get from triple and core For MIPS 515 // these are application specific extensions like micromips, mips16 etc. 516 uint32_t m_flags = 0; 517 518 ConstString m_distribution_id; 519 520 // Called when m_def or m_entry are changed. Fills in all remaining members 521 // with default values. 522 void CoreUpdated(bool update_triple); 523 }; 524 525 /// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than 526 /// operator. 527 /// 528 /// Tests two ArchSpec objects to see if \a lhs is less than \a rhs. 529 /// 530 /// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in] 531 /// rhs The Left Hand Side ArchSpec object to compare. 532 /// 533 /// \return true if \a lhs is less than \a rhs 534 bool operator<(const ArchSpec &lhs, const ArchSpec &rhs); 535 bool operator==(const ArchSpec &lhs, const ArchSpec &rhs); 536 537 bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch); 538 539 } // namespace lldb_private 540 541 #endif // #ifndef LLDB_UTILITY_ARCHSPEC_H 542