1 //===-- ArchSpec.h ----------------------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #ifndef LLDB_UTILITY_ARCHSPEC_H 10 #define LLDB_UTILITY_ARCHSPEC_H 11 12 #include "lldb/Utility/CompletionRequest.h" 13 #include "lldb/Utility/ConstString.h" 14 #include "lldb/lldb-enumerations.h" 15 #include "lldb/lldb-forward.h" 16 #include "lldb/lldb-private-enumerations.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/Support/YAMLTraits.h" 20 #include <cstddef> 21 #include <cstdint> 22 #include <string> 23 24 namespace lldb_private { 25 26 /// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture 27 /// specification class. 28 /// 29 /// A class designed to be created from a cpu type and subtype, a 30 /// string representation, or an llvm::Triple. Keeping all of the conversions 31 /// of strings to architecture enumeration values confined to this class 32 /// allows new architecture support to be added easily. 33 class ArchSpec { 34 public: 35 enum MIPSSubType { 36 eMIPSSubType_unknown, 37 eMIPSSubType_mips32, 38 eMIPSSubType_mips32r2, 39 eMIPSSubType_mips32r6, 40 eMIPSSubType_mips32el, 41 eMIPSSubType_mips32r2el, 42 eMIPSSubType_mips32r6el, 43 eMIPSSubType_mips64, 44 eMIPSSubType_mips64r2, 45 eMIPSSubType_mips64r6, 46 eMIPSSubType_mips64el, 47 eMIPSSubType_mips64r2el, 48 eMIPSSubType_mips64r6el, 49 }; 50 51 // Masks for the ases word of an ABI flags structure. 52 enum MIPSASE { 53 eMIPSAse_dsp = 0x00000001, // DSP ASE 54 eMIPSAse_dspr2 = 0x00000002, // DSP R2 ASE 55 eMIPSAse_eva = 0x00000004, // Enhanced VA Scheme 56 eMIPSAse_mcu = 0x00000008, // MCU (MicroController) ASE 57 eMIPSAse_mdmx = 0x00000010, // MDMX ASE 58 eMIPSAse_mips3d = 0x00000020, // MIPS-3D ASE 59 eMIPSAse_mt = 0x00000040, // MT ASE 60 eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE 61 eMIPSAse_virt = 0x00000100, // VZ ASE 62 eMIPSAse_msa = 0x00000200, // MSA ASE 63 eMIPSAse_mips16 = 0x00000400, // MIPS16 ASE 64 eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE 65 eMIPSAse_xpa = 0x00001000, // XPA ASE 66 eMIPSAse_mask = 0x00001fff, 67 eMIPSABI_O32 = 0x00002000, 68 eMIPSABI_N32 = 0x00004000, 69 eMIPSABI_N64 = 0x00008000, 70 eMIPSABI_O64 = 0x00020000, 71 eMIPSABI_EABI32 = 0x00040000, 72 eMIPSABI_EABI64 = 0x00080000, 73 eMIPSABI_mask = 0x000ff000 74 }; 75 76 // MIPS Floating point ABI Values 77 enum MIPS_ABI_FP { 78 eMIPS_ABI_FP_ANY = 0x00000000, 79 eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float 80 eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float 81 eMIPS_ABI_FP_SOFT = 0x00300000, // soft float 82 eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64 83 eMIPS_ABI_FP_XX = 0x00500000, // -mfpxx 84 eMIPS_ABI_FP_64 = 0x00600000, // -mips32r2 -mfp64 85 eMIPS_ABI_FP_64A = 0x00700000, // -mips32r2 -mfp64 -mno-odd-spreg 86 eMIPS_ABI_FP_mask = 0x00700000 87 }; 88 89 // ARM specific e_flags 90 enum ARMeflags { 91 eARM_abi_soft_float = 0x00000200, 92 eARM_abi_hard_float = 0x00000400 93 }; 94 95 enum Core { 96 eCore_arm_generic, 97 eCore_arm_armv4, 98 eCore_arm_armv4t, 99 eCore_arm_armv5, 100 eCore_arm_armv5e, 101 eCore_arm_armv5t, 102 eCore_arm_armv6, 103 eCore_arm_armv6m, 104 eCore_arm_armv7, 105 eCore_arm_armv7l, 106 eCore_arm_armv7f, 107 eCore_arm_armv7s, 108 eCore_arm_armv7k, 109 eCore_arm_armv7m, 110 eCore_arm_armv7em, 111 eCore_arm_xscale, 112 113 eCore_thumb, 114 eCore_thumbv4t, 115 eCore_thumbv5, 116 eCore_thumbv5e, 117 eCore_thumbv6, 118 eCore_thumbv6m, 119 eCore_thumbv7, 120 eCore_thumbv7s, 121 eCore_thumbv7k, 122 eCore_thumbv7f, 123 eCore_thumbv7m, 124 eCore_thumbv7em, 125 eCore_arm_arm64, 126 eCore_arm_armv8, 127 eCore_arm_armv8l, 128 eCore_arm_arm64_32, 129 eCore_arm_aarch64, 130 131 eCore_mips32, 132 eCore_mips32r2, 133 eCore_mips32r3, 134 eCore_mips32r5, 135 eCore_mips32r6, 136 eCore_mips32el, 137 eCore_mips32r2el, 138 eCore_mips32r3el, 139 eCore_mips32r5el, 140 eCore_mips32r6el, 141 eCore_mips64, 142 eCore_mips64r2, 143 eCore_mips64r3, 144 eCore_mips64r5, 145 eCore_mips64r6, 146 eCore_mips64el, 147 eCore_mips64r2el, 148 eCore_mips64r3el, 149 eCore_mips64r5el, 150 eCore_mips64r6el, 151 152 eCore_ppc_generic, 153 eCore_ppc_ppc601, 154 eCore_ppc_ppc602, 155 eCore_ppc_ppc603, 156 eCore_ppc_ppc603e, 157 eCore_ppc_ppc603ev, 158 eCore_ppc_ppc604, 159 eCore_ppc_ppc604e, 160 eCore_ppc_ppc620, 161 eCore_ppc_ppc750, 162 eCore_ppc_ppc7400, 163 eCore_ppc_ppc7450, 164 eCore_ppc_ppc970, 165 166 eCore_ppc64le_generic, 167 eCore_ppc64_generic, 168 eCore_ppc64_ppc970_64, 169 170 eCore_s390x_generic, 171 172 eCore_sparc_generic, 173 174 eCore_sparc9_generic, 175 176 eCore_x86_32_i386, 177 eCore_x86_32_i486, 178 eCore_x86_32_i486sx, 179 eCore_x86_32_i686, 180 181 eCore_x86_64_x86_64, 182 eCore_x86_64_x86_64h, // Haswell enabled x86_64 183 eCore_x86_64_amd64, 184 eCore_hexagon_generic, 185 eCore_hexagon_hexagonv4, 186 eCore_hexagon_hexagonv5, 187 188 eCore_uknownMach32, 189 eCore_uknownMach64, 190 191 eCore_arc, // little endian ARC 192 193 eCore_avr, 194 195 eCore_wasm32, 196 197 kNumCores, 198 199 kCore_invalid, 200 // The following constants are used for wildcard matching only 201 kCore_any, 202 kCore_arm_any, 203 kCore_ppc_any, 204 kCore_ppc64_any, 205 kCore_x86_32_any, 206 kCore_x86_64_any, 207 kCore_hexagon_any, 208 209 kCore_arm_first = eCore_arm_generic, 210 kCore_arm_last = eCore_arm_xscale, 211 212 kCore_thumb_first = eCore_thumb, 213 kCore_thumb_last = eCore_thumbv7em, 214 215 kCore_ppc_first = eCore_ppc_generic, 216 kCore_ppc_last = eCore_ppc_ppc970, 217 218 kCore_ppc64_first = eCore_ppc64_generic, 219 kCore_ppc64_last = eCore_ppc64_ppc970_64, 220 221 kCore_x86_32_first = eCore_x86_32_i386, 222 kCore_x86_32_last = eCore_x86_32_i686, 223 224 kCore_x86_64_first = eCore_x86_64_x86_64, 225 kCore_x86_64_last = eCore_x86_64_x86_64h, 226 227 kCore_hexagon_first = eCore_hexagon_generic, 228 kCore_hexagon_last = eCore_hexagon_hexagonv5, 229 230 kCore_mips32_first = eCore_mips32, 231 kCore_mips32_last = eCore_mips32r6, 232 233 kCore_mips32el_first = eCore_mips32el, 234 kCore_mips32el_last = eCore_mips32r6el, 235 236 kCore_mips64_first = eCore_mips64, 237 kCore_mips64_last = eCore_mips64r6, 238 239 kCore_mips64el_first = eCore_mips64el, 240 kCore_mips64el_last = eCore_mips64r6el, 241 242 kCore_mips_first = eCore_mips32, 243 kCore_mips_last = eCore_mips64r6el 244 245 }; 246 247 /// Default constructor. 248 /// 249 /// Default constructor that initializes the object with invalid cpu type 250 /// and subtype values. 251 ArchSpec(); 252 253 /// Constructor over triple. 254 /// 255 /// Constructs an ArchSpec with properties consistent with the given Triple. 256 explicit ArchSpec(const llvm::Triple &triple); 257 explicit ArchSpec(const char *triple_cstr); 258 explicit ArchSpec(llvm::StringRef triple_str); 259 /// Constructor over architecture name. 260 /// 261 /// Constructs an ArchSpec with properties consistent with the given object 262 /// type and architecture name. 263 explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type, 264 uint32_t cpu_subtype); 265 266 /// Destructor. 267 ~ArchSpec(); 268 269 /// Returns true if the OS, vendor and environment fields of the triple are 270 /// unset. The triple is expected to be normalized 271 /// (llvm::Triple::normalize). 272 static bool ContainsOnlyArch(const llvm::Triple &normalized_triple); 273 274 static void ListSupportedArchNames(StringList &list); 275 static void AutoComplete(CompletionRequest &request); 276 277 /// Returns a static string representing the current architecture. 278 /// 279 /// \return A static string corresponding to the current 280 /// architecture. 281 const char *GetArchitectureName() const; 282 283 /// if MIPS architecture return true. 284 /// 285 /// \return a boolean value. 286 bool IsMIPS() const; 287 288 /// Returns a string representing current architecture as a target CPU for 289 /// tools like compiler, disassembler etc. 290 /// 291 /// \return A string representing target CPU for the current 292 /// architecture. 293 std::string GetClangTargetCPU() const; 294 295 /// Return a string representing target application ABI. 296 /// 297 /// \return A string representing target application ABI. 298 std::string GetTargetABI() const; 299 300 /// Clears the object state. 301 /// 302 /// Clears the object state back to a default invalid state. 303 void Clear(); 304 305 /// Returns the size in bytes of an address of the current architecture. 306 /// 307 /// \return The byte size of an address of the current architecture. 308 uint32_t GetAddressByteSize() const; 309 310 /// Returns a machine family for the current architecture. 311 /// 312 /// \return An LLVM arch type. 313 llvm::Triple::ArchType GetMachine() const; 314 315 /// Returns the distribution id of the architecture. 316 /// 317 /// This will be something like "ubuntu", "fedora", etc. on Linux. 318 /// 319 /// \return A ConstString ref containing the distribution id, 320 /// potentially empty. 321 ConstString GetDistributionId() const; 322 323 /// Set the distribution id of the architecture. 324 /// 325 /// This will be something like "ubuntu", "fedora", etc. on Linux. This 326 /// should be the same value returned by HostInfo::GetDistributionId (). 327 void SetDistributionId(const char *distribution_id); 328 329 /// Tests if this ArchSpec is valid. 330 /// 331 /// \return True if the current architecture is valid, false 332 /// otherwise. 333 bool IsValid() const { 334 return m_core >= eCore_arm_generic && m_core < kNumCores; 335 } 336 explicit operator bool() const { return IsValid(); } 337 338 bool TripleVendorWasSpecified() const { 339 return !m_triple.getVendorName().empty(); 340 } 341 342 bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); } 343 344 bool TripleEnvironmentWasSpecified() const { 345 return m_triple.hasEnvironment(); 346 } 347 348 /// Merges fields from another ArchSpec into this ArchSpec. 349 /// 350 /// This will use the supplied ArchSpec to fill in any fields of the triple 351 /// in this ArchSpec which were unspecified. This can be used to refine a 352 /// generic ArchSpec with a more specific one. For example, if this 353 /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we 354 /// have a triple which is x64-pc-windows-msvc, then merging that triple 355 /// into this one will result in the triple i386-pc-windows-msvc. 356 /// 357 void MergeFrom(const ArchSpec &other); 358 359 /// Change the architecture object type, CPU type and OS type. 360 /// 361 /// \param[in] arch_type The object type of this ArchSpec. 362 /// 363 /// \param[in] cpu The required CPU type. 364 /// 365 /// \param[in] os The optional OS type 366 /// The default value of 0 was chosen to from the ELF spec value 367 /// ELFOSABI_NONE. ELF is the only one using this parameter. If another 368 /// format uses this parameter and 0 does not work, use a value over 369 /// 255 because in the ELF header this is value is only a byte. 370 /// 371 /// \return True if the object, and CPU were successfully set. 372 /// 373 /// As a side effect, the vendor value is usually set to unknown. The 374 /// exceptions are 375 /// aarch64-apple-ios 376 /// arm-apple-ios 377 /// thumb-apple-ios 378 /// x86-apple- 379 /// x86_64-apple- 380 /// 381 /// As a side effect, the os value is usually set to unknown The exceptions 382 /// are 383 /// *-*-aix 384 /// aarch64-apple-ios 385 /// arm-apple-ios 386 /// thumb-apple-ios 387 /// powerpc-apple-darwin 388 /// *-*-freebsd 389 /// *-*-linux 390 /// *-*-netbsd 391 /// *-*-openbsd 392 /// *-*-solaris 393 bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub, 394 uint32_t os = 0); 395 396 /// Returns the byte order for the architecture specification. 397 /// 398 /// \return The endian enumeration for the current endianness of 399 /// the architecture specification 400 lldb::ByteOrder GetByteOrder() const; 401 402 /// Sets this ArchSpec's byte order. 403 /// 404 /// In the common case there is no need to call this method as the byte 405 /// order can almost always be determined by the architecture. However, many 406 /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed 407 /// byte order may be incorrect. 408 void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; } 409 410 uint32_t GetMinimumOpcodeByteSize() const; 411 412 uint32_t GetMaximumOpcodeByteSize() const; 413 414 Core GetCore() const { return m_core; } 415 416 uint32_t GetMachOCPUType() const; 417 418 uint32_t GetMachOCPUSubType() const; 419 420 /// Architecture data byte width accessor 421 /// 422 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 423 /// from the Architecture's data bus 424 uint32_t GetDataByteSize() const; 425 426 /// Architecture code byte width accessor 427 /// 428 /// \return the size in 8-bit (host) bytes of a minimum addressable unit 429 /// from the Architecture's code bus 430 uint32_t GetCodeByteSize() const; 431 432 /// Architecture triple accessor. 433 /// 434 /// \return A triple describing this ArchSpec. 435 llvm::Triple &GetTriple() { return m_triple; } 436 437 /// Architecture triple accessor. 438 /// 439 /// \return A triple describing this ArchSpec. 440 const llvm::Triple &GetTriple() const { return m_triple; } 441 442 void DumpTriple(llvm::raw_ostream &s) const; 443 444 /// Architecture triple setter. 445 /// 446 /// Configures this ArchSpec according to the given triple. If the triple 447 /// has unknown components in all of the vendor, OS, and the optional 448 /// environment field (i.e. "i386-unknown-unknown") then default values are 449 /// taken from the host. Architecture and environment components are used 450 /// to further resolve the CPU type and subtype, endian characteristics, 451 /// etc. 452 /// 453 /// \return A triple describing this ArchSpec. 454 bool SetTriple(const llvm::Triple &triple); 455 456 bool SetTriple(llvm::StringRef triple_str); 457 458 /// Returns the default endianness of the architecture. 459 /// 460 /// \return The endian enumeration for the default endianness of 461 /// the architecture. 462 lldb::ByteOrder GetDefaultEndian() const; 463 464 /// Returns true if 'char' is a signed type by default in the architecture 465 /// false otherwise 466 /// 467 /// \return True if 'char' is a signed type by default on the 468 /// architecture and false otherwise. 469 bool CharIsSignedByDefault() const; 470 471 /// Compare an ArchSpec to another ArchSpec, requiring an exact cpu type 472 /// match between them. e.g. armv7s is not an exact match with armv7 - this 473 /// would return false 474 /// 475 /// \return true if the two ArchSpecs match. 476 bool IsExactMatch(const ArchSpec &rhs) const; 477 478 /// Compare an ArchSpec to another ArchSpec, requiring a compatible cpu type 479 /// match between them. e.g. armv7s is compatible with armv7 - this method 480 /// would return true 481 /// 482 /// \return true if the two ArchSpecs are compatible 483 bool IsCompatibleMatch(const ArchSpec &rhs) const; 484 485 bool IsFullySpecifiedTriple() const; 486 487 void PiecewiseTripleCompare(const ArchSpec &other, bool &arch_different, 488 bool &vendor_different, bool &os_different, 489 bool &os_version_different, 490 bool &env_different) const; 491 492 /// Detect whether this architecture uses thumb code exclusively 493 /// 494 /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute 495 /// the Thumb instructions, never Arm. We should normally pick up 496 /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints 497 /// on each function - but when doing bare-boards low level debugging 498 /// (especially common with these embedded processors), we may not have 499 /// those things easily accessible. 500 /// 501 /// \return true if this is an arm ArchSpec which can only execute Thumb 502 /// instructions 503 bool IsAlwaysThumbInstructions() const; 504 505 uint32_t GetFlags() const { return m_flags; } 506 507 void SetFlags(uint32_t flags) { m_flags = flags; } 508 509 void SetFlags(std::string elf_abi); 510 511 protected: 512 bool IsEqualTo(const ArchSpec &rhs, bool exact_match) const; 513 void UpdateCore(); 514 515 llvm::Triple m_triple; 516 Core m_core = kCore_invalid; 517 lldb::ByteOrder m_byte_order = lldb::eByteOrderInvalid; 518 519 // Additional arch flags which we cannot get from triple and core For MIPS 520 // these are application specific extensions like micromips, mips16 etc. 521 uint32_t m_flags = 0; 522 523 ConstString m_distribution_id; 524 525 // Called when m_def or m_entry are changed. Fills in all remaining members 526 // with default values. 527 void CoreUpdated(bool update_triple); 528 }; 529 530 /// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than 531 /// operator. 532 /// 533 /// Tests two ArchSpec objects to see if \a lhs is less than \a rhs. 534 /// 535 /// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in] 536 /// rhs The Left Hand Side ArchSpec object to compare. 537 /// 538 /// \return true if \a lhs is less than \a rhs 539 bool operator<(const ArchSpec &lhs, const ArchSpec &rhs); 540 bool operator==(const ArchSpec &lhs, const ArchSpec &rhs); 541 542 bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch); 543 544 } // namespace lldb_private 545 546 namespace llvm { 547 namespace yaml { 548 template <> struct ScalarTraits<lldb_private::ArchSpec> { 549 static void output(const lldb_private::ArchSpec &, void *, raw_ostream &); 550 static StringRef input(StringRef, void *, lldb_private::ArchSpec &); 551 static QuotingType mustQuote(StringRef S) { return QuotingType::Double; } 552 }; 553 } // namespace yaml 554 } // namespace llvm 555 556 LLVM_YAML_IS_SEQUENCE_VECTOR(lldb_private::ArchSpec) 557 558 #endif // LLDB_UTILITY_ARCHSPEC_H 559