1 /* i386.c -- Assemble code for the Intel 80386 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004, 2005, 2006 4 Free Software Foundation, Inc. 5 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS; see the file COPYING. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 21 02110-1301, USA. */ 22 23 /* Intel 80386 machine specific gas. 24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu). 25 x86_64 support by Jan Hubicka (jh@suse.cz) 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz) 27 Bugs & suggestions are completely welcome. This is free software. 28 Please help us make it better. */ 29 30 #include "as.h" 31 #include "safe-ctype.h" 32 #include "subsegs.h" 33 #include "dwarf2dbg.h" 34 #include "dw2gencfi.h" 35 #include "opcode/i386.h" 36 #include "elf/x86-64.h" 37 38 #ifndef REGISTER_WARNINGS 39 #define REGISTER_WARNINGS 1 40 #endif 41 42 #ifndef INFER_ADDR_PREFIX 43 #define INFER_ADDR_PREFIX 1 44 #endif 45 46 #ifndef SCALE1_WHEN_NO_INDEX 47 /* Specifying a scale factor besides 1 when there is no index is 48 futile. eg. `mov (%ebx,2),%al' does exactly the same as 49 `mov (%ebx),%al'. To slavishly follow what the programmer 50 specified, set SCALE1_WHEN_NO_INDEX to 0. */ 51 #define SCALE1_WHEN_NO_INDEX 1 52 #endif 53 54 #ifndef DEFAULT_ARCH 55 #define DEFAULT_ARCH "i386" 56 #endif 57 58 #ifndef INLINE 59 #if __GNUC__ >= 2 60 #define INLINE __inline__ 61 #else 62 #define INLINE 63 #endif 64 #endif 65 66 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int)); 67 static INLINE int fits_in_signed_byte PARAMS ((offsetT)); 68 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT)); 69 static INLINE int fits_in_unsigned_word PARAMS ((offsetT)); 70 static INLINE int fits_in_signed_word PARAMS ((offsetT)); 71 static INLINE int fits_in_unsigned_long PARAMS ((offsetT)); 72 static INLINE int fits_in_signed_long PARAMS ((offsetT)); 73 static int smallest_imm_type PARAMS ((offsetT)); 74 static offsetT offset_in_range PARAMS ((offsetT, int)); 75 static int add_prefix PARAMS ((unsigned int)); 76 static void set_code_flag PARAMS ((int)); 77 static void set_16bit_gcc_code_flag PARAMS ((int)); 78 static void set_intel_syntax PARAMS ((int)); 79 static void set_cpu_arch PARAMS ((int)); 80 #ifdef TE_PE 81 static void pe_directive_secrel PARAMS ((int)); 82 #endif 83 static void signed_cons PARAMS ((int)); 84 static char *output_invalid PARAMS ((int c)); 85 static int i386_operand PARAMS ((char *operand_string)); 86 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); 87 static const reg_entry *parse_register PARAMS ((char *reg_string, 88 char **end_op)); 89 static char *parse_insn PARAMS ((char *, char *)); 90 static char *parse_operands PARAMS ((char *, const char *)); 91 static void swap_operands PARAMS ((void)); 92 static void optimize_imm PARAMS ((void)); 93 static void optimize_disp PARAMS ((void)); 94 static int match_template PARAMS ((void)); 95 static int check_string PARAMS ((void)); 96 static int process_suffix PARAMS ((void)); 97 static int check_byte_reg PARAMS ((void)); 98 static int check_long_reg PARAMS ((void)); 99 static int check_qword_reg PARAMS ((void)); 100 static int check_word_reg PARAMS ((void)); 101 static int finalize_imm PARAMS ((void)); 102 static int process_operands PARAMS ((void)); 103 static const seg_entry *build_modrm_byte PARAMS ((void)); 104 static void output_insn PARAMS ((void)); 105 static void output_branch PARAMS ((void)); 106 static void output_jump PARAMS ((void)); 107 static void output_interseg_jump PARAMS ((void)); 108 static void output_imm PARAMS ((fragS *insn_start_frag, 109 offsetT insn_start_off)); 110 static void output_disp PARAMS ((fragS *insn_start_frag, 111 offsetT insn_start_off)); 112 #ifndef I386COFF 113 static void s_bss PARAMS ((int)); 114 #endif 115 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 116 static void handle_large_common (int small ATTRIBUTE_UNUSED); 117 #endif 118 119 static const char *default_arch = DEFAULT_ARCH; 120 121 /* 'md_assemble ()' gathers together information and puts it into a 122 i386_insn. */ 123 124 union i386_op 125 { 126 expressionS *disps; 127 expressionS *imms; 128 const reg_entry *regs; 129 }; 130 131 struct _i386_insn 132 { 133 /* TM holds the template for the insn were currently assembling. */ 134 template tm; 135 136 /* SUFFIX holds the instruction mnemonic suffix if given. 137 (e.g. 'l' for 'movl') */ 138 char suffix; 139 140 /* OPERANDS gives the number of given operands. */ 141 unsigned int operands; 142 143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number 144 of given register, displacement, memory operands and immediate 145 operands. */ 146 unsigned int reg_operands, disp_operands, mem_operands, imm_operands; 147 148 /* TYPES [i] is the type (see above #defines) which tells us how to 149 use OP[i] for the corresponding operand. */ 150 unsigned int types[MAX_OPERANDS]; 151 152 /* Displacement expression, immediate expression, or register for each 153 operand. */ 154 union i386_op op[MAX_OPERANDS]; 155 156 /* Flags for operands. */ 157 unsigned int flags[MAX_OPERANDS]; 158 #define Operand_PCrel 1 159 160 /* Relocation type for operand */ 161 enum bfd_reloc_code_real reloc[MAX_OPERANDS]; 162 163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode 164 the base index byte below. */ 165 const reg_entry *base_reg; 166 const reg_entry *index_reg; 167 unsigned int log2_scale_factor; 168 169 /* SEG gives the seg_entries of this insn. They are zero unless 170 explicit segment overrides are given. */ 171 const seg_entry *seg[2]; 172 173 /* PREFIX holds all the given prefix opcodes (usually null). 174 PREFIXES is the number of prefix opcodes. */ 175 unsigned int prefixes; 176 unsigned char prefix[MAX_PREFIXES]; 177 178 /* RM and SIB are the modrm byte and the sib byte where the 179 addressing modes of this insn are encoded. */ 180 181 modrm_byte rm; 182 rex_byte rex; 183 sib_byte sib; 184 }; 185 186 typedef struct _i386_insn i386_insn; 187 188 /* List of chars besides those in app.c:symbol_chars that can start an 189 operand. Used to prevent the scrubber eating vital white-space. */ 190 const char extra_symbol_chars[] = "*%-([" 191 #ifdef LEX_AT 192 "@" 193 #endif 194 #ifdef LEX_QM 195 "?" 196 #endif 197 ; 198 199 #if (defined (TE_I386AIX) \ 200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ 201 && !defined (TE_GNU) \ 202 && !defined (TE_LINUX) \ 203 && !defined (TE_NETWARE) \ 204 && !defined (TE_FreeBSD) \ 205 && !defined (TE_NetBSD) \ 206 && !defined (TE_OpenBSD))) 207 /* This array holds the chars that always start a comment. If the 208 pre-processor is disabled, these aren't very useful. The option 209 --divide will remove '/' from this list. */ 210 const char *i386_comment_chars = "#/"; 211 #define SVR4_COMMENT_CHARS 1 212 #define PREFIX_SEPARATOR '\\' 213 214 #else 215 const char *i386_comment_chars = "#"; 216 #define PREFIX_SEPARATOR '/' 217 #endif 218 219 /* This array holds the chars that only start a comment at the beginning of 220 a line. If the line seems to have the form '# 123 filename' 221 .line and .file directives will appear in the pre-processed output. 222 Note that input_file.c hand checks for '#' at the beginning of the 223 first line of the input file. This is because the compiler outputs 224 #NO_APP at the beginning of its output. 225 Also note that comments started like this one will always work if 226 '/' isn't otherwise defined. */ 227 const char line_comment_chars[] = "#/"; 228 229 const char line_separator_chars[] = ";"; 230 231 /* Chars that can be used to separate mant from exp in floating point 232 nums. */ 233 const char EXP_CHARS[] = "eE"; 234 235 /* Chars that mean this number is a floating point constant 236 As in 0f12.456 237 or 0d1.2345e12. */ 238 const char FLT_CHARS[] = "fFdDxX"; 239 240 /* Tables for lexical analysis. */ 241 static char mnemonic_chars[256]; 242 static char register_chars[256]; 243 static char operand_chars[256]; 244 static char identifier_chars[256]; 245 static char digit_chars[256]; 246 247 /* Lexical macros. */ 248 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) 249 #define is_operand_char(x) (operand_chars[(unsigned char) x]) 250 #define is_register_char(x) (register_chars[(unsigned char) x]) 251 #define is_space_char(x) ((x) == ' ') 252 #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) 253 #define is_digit_char(x) (digit_chars[(unsigned char) x]) 254 255 /* All non-digit non-letter characters that may occur in an operand. */ 256 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; 257 258 /* md_assemble() always leaves the strings it's passed unaltered. To 259 effect this we maintain a stack of saved characters that we've smashed 260 with '\0's (indicating end of strings for various sub-fields of the 261 assembler instruction). */ 262 static char save_stack[32]; 263 static char *save_stack_p; 264 #define END_STRING_AND_SAVE(s) \ 265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) 266 #define RESTORE_END_STRING(s) \ 267 do { *(s) = *--save_stack_p; } while (0) 268 269 /* The instruction we're assembling. */ 270 static i386_insn i; 271 272 /* Possible templates for current insn. */ 273 static const templates *current_templates; 274 275 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ 276 static expressionS disp_expressions[2], im_expressions[2]; 277 278 /* Current operand we are working on. */ 279 static int this_operand; 280 281 /* We support four different modes. FLAG_CODE variable is used to distinguish 282 these. */ 283 284 enum flag_code { 285 CODE_32BIT, 286 CODE_16BIT, 287 CODE_64BIT }; 288 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1) 289 290 static enum flag_code flag_code; 291 static unsigned int object_64bit; 292 static int use_rela_relocations = 0; 293 294 /* The names used to print error messages. */ 295 static const char *flag_code_names[] = 296 { 297 "32", 298 "16", 299 "64" 300 }; 301 302 /* 1 for intel syntax, 303 0 if att syntax. */ 304 static int intel_syntax = 0; 305 306 /* 1 if register prefix % not required. */ 307 static int allow_naked_reg = 0; 308 309 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, 310 leave, push, and pop instructions so that gcc has the same stack 311 frame as in 32 bit mode. */ 312 static char stackop_size = '\0'; 313 314 /* Non-zero to optimize code alignment. */ 315 int optimize_align_code = 1; 316 317 /* Non-zero to quieten some warnings. */ 318 static int quiet_warnings = 0; 319 320 /* CPU name. */ 321 static const char *cpu_arch_name = NULL; 322 static const char *cpu_sub_arch_name = NULL; 323 324 /* CPU feature flags. */ 325 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64; 326 327 /* If set, conditional jumps are not automatically promoted to handle 328 larger than a byte offset. */ 329 static unsigned int no_cond_jump_promotion = 0; 330 331 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ 332 static symbolS *GOT_symbol; 333 334 /* The dwarf2 return column, adjusted for 32 or 64 bit. */ 335 unsigned int x86_dwarf2_return_column; 336 337 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 338 int x86_cie_data_alignment; 339 340 /* Interface to relax_segment. 341 There are 3 major relax states for 386 jump insns because the 342 different types of jumps add different sizes to frags when we're 343 figuring out what sort of jump to choose to reach a given label. */ 344 345 /* Types. */ 346 #define UNCOND_JUMP 0 347 #define COND_JUMP 1 348 #define COND_JUMP86 2 349 350 /* Sizes. */ 351 #define CODE16 1 352 #define SMALL 0 353 #define SMALL16 (SMALL | CODE16) 354 #define BIG 2 355 #define BIG16 (BIG | CODE16) 356 357 #ifndef INLINE 358 #ifdef __GNUC__ 359 #define INLINE __inline__ 360 #else 361 #define INLINE 362 #endif 363 #endif 364 365 #define ENCODE_RELAX_STATE(type, size) \ 366 ((relax_substateT) (((type) << 2) | (size))) 367 #define TYPE_FROM_RELAX_STATE(s) \ 368 ((s) >> 2) 369 #define DISP_SIZE_FROM_RELAX_STATE(s) \ 370 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) 371 372 /* This table is used by relax_frag to promote short jumps to long 373 ones where necessary. SMALL (short) jumps may be promoted to BIG 374 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We 375 don't allow a short jump in a 32 bit code segment to be promoted to 376 a 16 bit offset jump because it's slower (requires data size 377 prefix), and doesn't work, unless the destination is in the bottom 378 64k of the code segment (The top 16 bits of eip are zeroed). */ 379 380 const relax_typeS md_relax_table[] = 381 { 382 /* The fields are: 383 1) most positive reach of this state, 384 2) most negative reach of this state, 385 3) how many bytes this mode will have in the variable part of the frag 386 4) which index into the table to try if we can't fit into this one. */ 387 388 /* UNCOND_JUMP states. */ 389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, 390 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, 391 /* dword jmp adds 4 bytes to frag: 392 0 extra opcode bytes, 4 displacement bytes. */ 393 {0, 0, 4, 0}, 394 /* word jmp adds 2 byte2 to frag: 395 0 extra opcode bytes, 2 displacement bytes. */ 396 {0, 0, 2, 0}, 397 398 /* COND_JUMP states. */ 399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, 400 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, 401 /* dword conditionals adds 5 bytes to frag: 402 1 extra opcode byte, 4 displacement bytes. */ 403 {0, 0, 5, 0}, 404 /* word conditionals add 3 bytes to frag: 405 1 extra opcode byte, 2 displacement bytes. */ 406 {0, 0, 3, 0}, 407 408 /* COND_JUMP86 states. */ 409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, 410 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, 411 /* dword conditionals adds 5 bytes to frag: 412 1 extra opcode byte, 4 displacement bytes. */ 413 {0, 0, 5, 0}, 414 /* word conditionals add 4 bytes to frag: 415 1 displacement byte and a 3 byte long branch insn. */ 416 {0, 0, 4, 0} 417 }; 418 419 static const arch_entry cpu_arch[] = { 420 {"i8086", Cpu086 }, 421 {"i186", Cpu086|Cpu186 }, 422 {"i286", Cpu086|Cpu186|Cpu286 }, 423 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, 424 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, 425 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 }, 426 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 }, 427 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 }, 428 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 }, 429 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX }, 430 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE }, 431 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 }, 432 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI }, 433 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX }, 434 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow }, 435 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA }, 436 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 }, 437 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 }, 438 {".mmx", CpuMMX }, 439 {".sse", CpuMMX|CpuMMX2|CpuSSE }, 440 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 }, 441 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 }, 442 {".3dnow", CpuMMX|Cpu3dnow }, 443 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA }, 444 {".padlock", CpuPadLock }, 445 {".pacifica", CpuSVME }, 446 {".svme", CpuSVME }, 447 {NULL, 0 } 448 }; 449 450 const pseudo_typeS md_pseudo_table[] = 451 { 452 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) 453 {"align", s_align_bytes, 0}, 454 #else 455 {"align", s_align_ptwo, 0}, 456 #endif 457 {"arch", set_cpu_arch, 0}, 458 #ifndef I386COFF 459 {"bss", s_bss, 0}, 460 #endif 461 {"ffloat", float_cons, 'f'}, 462 {"dfloat", float_cons, 'd'}, 463 {"tfloat", float_cons, 'x'}, 464 {"value", cons, 2}, 465 {"slong", signed_cons, 4}, 466 {"noopt", s_ignore, 0}, 467 {"optim", s_ignore, 0}, 468 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, 469 {"code16", set_code_flag, CODE_16BIT}, 470 {"code32", set_code_flag, CODE_32BIT}, 471 {"code64", set_code_flag, CODE_64BIT}, 472 {"intel_syntax", set_intel_syntax, 1}, 473 {"att_syntax", set_intel_syntax, 0}, 474 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 475 {"largecomm", handle_large_common, 0}, 476 #else 477 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0}, 478 {"loc", dwarf2_directive_loc, 0}, 479 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, 480 #endif 481 #ifdef TE_PE 482 {"secrel32", pe_directive_secrel, 0}, 483 #endif 484 {0, 0, 0} 485 }; 486 487 /* For interface with expression (). */ 488 extern char *input_line_pointer; 489 490 /* Hash table for instruction mnemonic lookup. */ 491 static struct hash_control *op_hash; 492 493 /* Hash table for register lookup. */ 494 static struct hash_control *reg_hash; 495 496 void 497 i386_align_code (fragP, count) 498 fragS *fragP; 499 int count; 500 { 501 /* Various efficient no-op patterns for aligning code labels. 502 Note: Don't try to assemble the instructions in the comments. 503 0L and 0w are not legal. */ 504 static const char f32_1[] = 505 {0x90}; /* nop */ 506 static const char f32_2[] = 507 {0x89,0xf6}; /* movl %esi,%esi */ 508 static const char f32_3[] = 509 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ 510 static const char f32_4[] = 511 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 512 static const char f32_5[] = 513 {0x90, /* nop */ 514 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 515 static const char f32_6[] = 516 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ 517 static const char f32_7[] = 518 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 519 static const char f32_8[] = 520 {0x90, /* nop */ 521 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 522 static const char f32_9[] = 523 {0x89,0xf6, /* movl %esi,%esi */ 524 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 525 static const char f32_10[] = 526 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ 527 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 528 static const char f32_11[] = 529 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ 530 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 531 static const char f32_12[] = 532 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 533 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ 534 static const char f32_13[] = 535 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 536 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 537 static const char f32_14[] = 538 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ 539 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 540 static const char f32_15[] = 541 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ 542 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; 543 static const char f16_3[] = 544 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ 545 static const char f16_4[] = 546 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 547 static const char f16_5[] = 548 {0x90, /* nop */ 549 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 550 static const char f16_6[] = 551 {0x89,0xf6, /* mov %si,%si */ 552 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 553 static const char f16_7[] = 554 {0x8d,0x74,0x00, /* lea 0(%si),%si */ 555 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 556 static const char f16_8[] = 557 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ 558 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 559 static const char *const f32_patt[] = { 560 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, 561 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 562 }; 563 static const char *const f16_patt[] = { 564 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, 565 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 566 }; 567 568 if (count <= 0 || count > 15) 569 return; 570 571 /* The recommended way to pad 64bit code is to use NOPs preceded by 572 maximally four 0x66 prefixes. Balance the size of nops. */ 573 if (flag_code == CODE_64BIT) 574 { 575 int i; 576 int nnops = (count + 3) / 4; 577 int len = count / nnops; 578 int remains = count - nnops * len; 579 int pos = 0; 580 581 for (i = 0; i < remains; i++) 582 { 583 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len); 584 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90; 585 pos += len + 1; 586 } 587 for (; i < nnops; i++) 588 { 589 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1); 590 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90; 591 pos += len; 592 } 593 } 594 else 595 if (flag_code == CODE_16BIT) 596 { 597 memcpy (fragP->fr_literal + fragP->fr_fix, 598 f16_patt[count - 1], count); 599 if (count > 8) 600 /* Adjust jump offset. */ 601 fragP->fr_literal[fragP->fr_fix + 1] = count - 2; 602 } 603 else 604 memcpy (fragP->fr_literal + fragP->fr_fix, 605 f32_patt[count - 1], count); 606 fragP->fr_var = count; 607 } 608 609 static INLINE unsigned int 610 mode_from_disp_size (t) 611 unsigned int t; 612 { 613 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0; 614 } 615 616 static INLINE int 617 fits_in_signed_byte (num) 618 offsetT num; 619 { 620 return (num >= -128) && (num <= 127); 621 } 622 623 static INLINE int 624 fits_in_unsigned_byte (num) 625 offsetT num; 626 { 627 return (num & 0xff) == num; 628 } 629 630 static INLINE int 631 fits_in_unsigned_word (num) 632 offsetT num; 633 { 634 return (num & 0xffff) == num; 635 } 636 637 static INLINE int 638 fits_in_signed_word (num) 639 offsetT num; 640 { 641 return (-32768 <= num) && (num <= 32767); 642 } 643 static INLINE int 644 fits_in_signed_long (num) 645 offsetT num ATTRIBUTE_UNUSED; 646 { 647 #ifndef BFD64 648 return 1; 649 #else 650 return (!(((offsetT) -1 << 31) & num) 651 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); 652 #endif 653 } /* fits_in_signed_long() */ 654 static INLINE int 655 fits_in_unsigned_long (num) 656 offsetT num ATTRIBUTE_UNUSED; 657 { 658 #ifndef BFD64 659 return 1; 660 #else 661 return (num & (((offsetT) 2 << 31) - 1)) == num; 662 #endif 663 } /* fits_in_unsigned_long() */ 664 665 static int 666 smallest_imm_type (num) 667 offsetT num; 668 { 669 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)) 670 { 671 /* This code is disabled on the 486 because all the Imm1 forms 672 in the opcode table are slower on the i486. They're the 673 versions with the implicitly specified single-position 674 displacement, which has another syntax if you really want to 675 use that form. */ 676 if (num == 1) 677 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64; 678 } 679 return (fits_in_signed_byte (num) 680 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64) 681 : fits_in_unsigned_byte (num) 682 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64) 683 : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) 684 ? (Imm16 | Imm32 | Imm32S | Imm64) 685 : fits_in_signed_long (num) 686 ? (Imm32 | Imm32S | Imm64) 687 : fits_in_unsigned_long (num) 688 ? (Imm32 | Imm64) 689 : Imm64); 690 } 691 692 static offsetT 693 offset_in_range (val, size) 694 offsetT val; 695 int size; 696 { 697 addressT mask; 698 699 switch (size) 700 { 701 case 1: mask = ((addressT) 1 << 8) - 1; break; 702 case 2: mask = ((addressT) 1 << 16) - 1; break; 703 case 4: mask = ((addressT) 2 << 31) - 1; break; 704 #ifdef BFD64 705 case 8: mask = ((addressT) 2 << 63) - 1; break; 706 #endif 707 default: abort (); 708 } 709 710 /* If BFD64, sign extend val. */ 711 if (!use_rela_relocations) 712 if ((val & ~(((addressT) 2 << 31) - 1)) == 0) 713 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); 714 715 if ((val & ~mask) != 0 && (val & ~mask) != ~mask) 716 { 717 char buf1[40], buf2[40]; 718 719 sprint_value (buf1, val); 720 sprint_value (buf2, val & mask); 721 as_warn (_("%s shortened to %s"), buf1, buf2); 722 } 723 return val & mask; 724 } 725 726 /* Returns 0 if attempting to add a prefix where one from the same 727 class already exists, 1 if non rep/repne added, 2 if rep/repne 728 added. */ 729 static int 730 add_prefix (prefix) 731 unsigned int prefix; 732 { 733 int ret = 1; 734 unsigned int q; 735 736 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 737 && flag_code == CODE_64BIT) 738 { 739 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64) 740 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ)) 741 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ)))) 742 ret = 0; 743 q = REX_PREFIX; 744 } 745 else 746 { 747 switch (prefix) 748 { 749 default: 750 abort (); 751 752 case CS_PREFIX_OPCODE: 753 case DS_PREFIX_OPCODE: 754 case ES_PREFIX_OPCODE: 755 case FS_PREFIX_OPCODE: 756 case GS_PREFIX_OPCODE: 757 case SS_PREFIX_OPCODE: 758 q = SEG_PREFIX; 759 break; 760 761 case REPNE_PREFIX_OPCODE: 762 case REPE_PREFIX_OPCODE: 763 ret = 2; 764 /* fall thru */ 765 case LOCK_PREFIX_OPCODE: 766 q = LOCKREP_PREFIX; 767 break; 768 769 case FWAIT_OPCODE: 770 q = WAIT_PREFIX; 771 break; 772 773 case ADDR_PREFIX_OPCODE: 774 q = ADDR_PREFIX; 775 break; 776 777 case DATA_PREFIX_OPCODE: 778 q = DATA_PREFIX; 779 break; 780 } 781 if (i.prefix[q] != 0) 782 ret = 0; 783 } 784 785 if (ret) 786 { 787 if (!i.prefix[q]) 788 ++i.prefixes; 789 i.prefix[q] |= prefix; 790 } 791 else 792 as_bad (_("same type of prefix used twice")); 793 794 return ret; 795 } 796 797 static void 798 set_code_flag (value) 799 int value; 800 { 801 flag_code = value; 802 cpu_arch_flags &= ~(Cpu64 | CpuNo64); 803 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); 804 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer)) 805 { 806 as_bad (_("64bit mode not supported on this CPU.")); 807 } 808 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386)) 809 { 810 as_bad (_("32bit mode not supported on this CPU.")); 811 } 812 stackop_size = '\0'; 813 } 814 815 static void 816 set_16bit_gcc_code_flag (new_code_flag) 817 int new_code_flag; 818 { 819 flag_code = new_code_flag; 820 cpu_arch_flags &= ~(Cpu64 | CpuNo64); 821 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); 822 stackop_size = LONG_MNEM_SUFFIX; 823 } 824 825 static void 826 set_intel_syntax (syntax_flag) 827 int syntax_flag; 828 { 829 /* Find out if register prefixing is specified. */ 830 int ask_naked_reg = 0; 831 832 SKIP_WHITESPACE (); 833 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 834 { 835 char *string = input_line_pointer; 836 int e = get_symbol_end (); 837 838 if (strcmp (string, "prefix") == 0) 839 ask_naked_reg = 1; 840 else if (strcmp (string, "noprefix") == 0) 841 ask_naked_reg = -1; 842 else 843 as_bad (_("bad argument to syntax directive.")); 844 *input_line_pointer = e; 845 } 846 demand_empty_rest_of_line (); 847 848 intel_syntax = syntax_flag; 849 850 if (ask_naked_reg == 0) 851 allow_naked_reg = (intel_syntax 852 && (bfd_get_symbol_leading_char (stdoutput) != '\0')); 853 else 854 allow_naked_reg = (ask_naked_reg < 0); 855 856 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; 857 identifier_chars['$'] = intel_syntax ? '$' : 0; 858 } 859 860 static void 861 set_cpu_arch (dummy) 862 int dummy ATTRIBUTE_UNUSED; 863 { 864 SKIP_WHITESPACE (); 865 866 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 867 { 868 char *string = input_line_pointer; 869 int e = get_symbol_end (); 870 int i; 871 872 for (i = 0; cpu_arch[i].name; i++) 873 { 874 if (strcmp (string, cpu_arch[i].name) == 0) 875 { 876 if (*string != '.') 877 { 878 cpu_arch_name = cpu_arch[i].name; 879 cpu_sub_arch_name = NULL; 880 cpu_arch_flags = (cpu_arch[i].flags 881 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64)); 882 break; 883 } 884 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags) 885 { 886 cpu_sub_arch_name = cpu_arch[i].name; 887 cpu_arch_flags |= cpu_arch[i].flags; 888 } 889 *input_line_pointer = e; 890 demand_empty_rest_of_line (); 891 return; 892 } 893 } 894 if (!cpu_arch[i].name) 895 as_bad (_("no such architecture: `%s'"), string); 896 897 *input_line_pointer = e; 898 } 899 else 900 as_bad (_("missing cpu architecture")); 901 902 no_cond_jump_promotion = 0; 903 if (*input_line_pointer == ',' 904 && !is_end_of_line[(unsigned char) input_line_pointer[1]]) 905 { 906 char *string = ++input_line_pointer; 907 int e = get_symbol_end (); 908 909 if (strcmp (string, "nojumps") == 0) 910 no_cond_jump_promotion = 1; 911 else if (strcmp (string, "jumps") == 0) 912 ; 913 else 914 as_bad (_("no such architecture modifier: `%s'"), string); 915 916 *input_line_pointer = e; 917 } 918 919 demand_empty_rest_of_line (); 920 } 921 922 unsigned long 923 i386_mach () 924 { 925 if (!strcmp (default_arch, "x86_64")) 926 return bfd_mach_x86_64; 927 else if (!strcmp (default_arch, "i386")) 928 return bfd_mach_i386_i386; 929 else 930 as_fatal (_("Unknown architecture")); 931 } 932 933 void 934 md_begin () 935 { 936 const char *hash_err; 937 938 /* Initialize op_hash hash table. */ 939 op_hash = hash_new (); 940 941 { 942 const template *optab; 943 templates *core_optab; 944 945 /* Setup for loop. */ 946 optab = i386_optab; 947 core_optab = (templates *) xmalloc (sizeof (templates)); 948 core_optab->start = optab; 949 950 while (1) 951 { 952 ++optab; 953 if (optab->name == NULL 954 || strcmp (optab->name, (optab - 1)->name) != 0) 955 { 956 /* different name --> ship out current template list; 957 add to hash table; & begin anew. */ 958 core_optab->end = optab; 959 hash_err = hash_insert (op_hash, 960 (optab - 1)->name, 961 (PTR) core_optab); 962 if (hash_err) 963 { 964 as_fatal (_("Internal Error: Can't hash %s: %s"), 965 (optab - 1)->name, 966 hash_err); 967 } 968 if (optab->name == NULL) 969 break; 970 core_optab = (templates *) xmalloc (sizeof (templates)); 971 core_optab->start = optab; 972 } 973 } 974 } 975 976 /* Initialize reg_hash hash table. */ 977 reg_hash = hash_new (); 978 { 979 const reg_entry *regtab; 980 981 for (regtab = i386_regtab; 982 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); 983 regtab++) 984 { 985 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); 986 if (hash_err) 987 as_fatal (_("Internal Error: Can't hash %s: %s"), 988 regtab->reg_name, 989 hash_err); 990 } 991 } 992 993 /* Fill in lexical tables: mnemonic_chars, operand_chars. */ 994 { 995 int c; 996 char *p; 997 998 for (c = 0; c < 256; c++) 999 { 1000 if (ISDIGIT (c)) 1001 { 1002 digit_chars[c] = c; 1003 mnemonic_chars[c] = c; 1004 register_chars[c] = c; 1005 operand_chars[c] = c; 1006 } 1007 else if (ISLOWER (c)) 1008 { 1009 mnemonic_chars[c] = c; 1010 register_chars[c] = c; 1011 operand_chars[c] = c; 1012 } 1013 else if (ISUPPER (c)) 1014 { 1015 mnemonic_chars[c] = TOLOWER (c); 1016 register_chars[c] = mnemonic_chars[c]; 1017 operand_chars[c] = c; 1018 } 1019 1020 if (ISALPHA (c) || ISDIGIT (c)) 1021 identifier_chars[c] = c; 1022 else if (c >= 128) 1023 { 1024 identifier_chars[c] = c; 1025 operand_chars[c] = c; 1026 } 1027 } 1028 1029 #ifdef LEX_AT 1030 identifier_chars['@'] = '@'; 1031 #endif 1032 #ifdef LEX_QM 1033 identifier_chars['?'] = '?'; 1034 operand_chars['?'] = '?'; 1035 #endif 1036 digit_chars['-'] = '-'; 1037 mnemonic_chars['-'] = '-'; 1038 identifier_chars['_'] = '_'; 1039 identifier_chars['.'] = '.'; 1040 1041 for (p = operand_special_chars; *p != '\0'; p++) 1042 operand_chars[(unsigned char) *p] = *p; 1043 } 1044 1045 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 1046 if (IS_ELF) 1047 { 1048 record_alignment (text_section, 2); 1049 record_alignment (data_section, 2); 1050 record_alignment (bss_section, 2); 1051 } 1052 #endif 1053 1054 if (flag_code == CODE_64BIT) 1055 { 1056 x86_dwarf2_return_column = 16; 1057 x86_cie_data_alignment = -8; 1058 } 1059 else 1060 { 1061 x86_dwarf2_return_column = 8; 1062 x86_cie_data_alignment = -4; 1063 } 1064 } 1065 1066 void 1067 i386_print_statistics (file) 1068 FILE *file; 1069 { 1070 hash_print_statistics (file, "i386 opcode", op_hash); 1071 hash_print_statistics (file, "i386 register", reg_hash); 1072 } 1073 1074 #ifdef DEBUG386 1075 1076 /* Debugging routines for md_assemble. */ 1077 static void pi PARAMS ((char *, i386_insn *)); 1078 static void pte PARAMS ((template *)); 1079 static void pt PARAMS ((unsigned int)); 1080 static void pe PARAMS ((expressionS *)); 1081 static void ps PARAMS ((symbolS *)); 1082 1083 static void 1084 pi (line, x) 1085 char *line; 1086 i386_insn *x; 1087 { 1088 unsigned int i; 1089 1090 fprintf (stdout, "%s: template ", line); 1091 pte (&x->tm); 1092 fprintf (stdout, " address: base %s index %s scale %x\n", 1093 x->base_reg ? x->base_reg->reg_name : "none", 1094 x->index_reg ? x->index_reg->reg_name : "none", 1095 x->log2_scale_factor); 1096 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", 1097 x->rm.mode, x->rm.reg, x->rm.regmem); 1098 fprintf (stdout, " sib: base %x index %x scale %x\n", 1099 x->sib.base, x->sib.index, x->sib.scale); 1100 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", 1101 (x->rex & REX_MODE64) != 0, 1102 (x->rex & REX_EXTX) != 0, 1103 (x->rex & REX_EXTY) != 0, 1104 (x->rex & REX_EXTZ) != 0); 1105 for (i = 0; i < x->operands; i++) 1106 { 1107 fprintf (stdout, " #%d: ", i + 1); 1108 pt (x->types[i]); 1109 fprintf (stdout, "\n"); 1110 if (x->types[i] 1111 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) 1112 fprintf (stdout, "%s\n", x->op[i].regs->reg_name); 1113 if (x->types[i] & Imm) 1114 pe (x->op[i].imms); 1115 if (x->types[i] & Disp) 1116 pe (x->op[i].disps); 1117 } 1118 } 1119 1120 static void 1121 pte (t) 1122 template *t; 1123 { 1124 unsigned int i; 1125 fprintf (stdout, " %d operands ", t->operands); 1126 fprintf (stdout, "opcode %x ", t->base_opcode); 1127 if (t->extension_opcode != None) 1128 fprintf (stdout, "ext %x ", t->extension_opcode); 1129 if (t->opcode_modifier & D) 1130 fprintf (stdout, "D"); 1131 if (t->opcode_modifier & W) 1132 fprintf (stdout, "W"); 1133 fprintf (stdout, "\n"); 1134 for (i = 0; i < t->operands; i++) 1135 { 1136 fprintf (stdout, " #%d type ", i + 1); 1137 pt (t->operand_types[i]); 1138 fprintf (stdout, "\n"); 1139 } 1140 } 1141 1142 static void 1143 pe (e) 1144 expressionS *e; 1145 { 1146 fprintf (stdout, " operation %d\n", e->X_op); 1147 fprintf (stdout, " add_number %ld (%lx)\n", 1148 (long) e->X_add_number, (long) e->X_add_number); 1149 if (e->X_add_symbol) 1150 { 1151 fprintf (stdout, " add_symbol "); 1152 ps (e->X_add_symbol); 1153 fprintf (stdout, "\n"); 1154 } 1155 if (e->X_op_symbol) 1156 { 1157 fprintf (stdout, " op_symbol "); 1158 ps (e->X_op_symbol); 1159 fprintf (stdout, "\n"); 1160 } 1161 } 1162 1163 static void 1164 ps (s) 1165 symbolS *s; 1166 { 1167 fprintf (stdout, "%s type %s%s", 1168 S_GET_NAME (s), 1169 S_IS_EXTERNAL (s) ? "EXTERNAL " : "", 1170 segment_name (S_GET_SEGMENT (s))); 1171 } 1172 1173 static struct type_name 1174 { 1175 unsigned int mask; 1176 char *tname; 1177 } 1178 const type_names[] = 1179 { 1180 { Reg8, "r8" }, 1181 { Reg16, "r16" }, 1182 { Reg32, "r32" }, 1183 { Reg64, "r64" }, 1184 { Imm8, "i8" }, 1185 { Imm8S, "i8s" }, 1186 { Imm16, "i16" }, 1187 { Imm32, "i32" }, 1188 { Imm32S, "i32s" }, 1189 { Imm64, "i64" }, 1190 { Imm1, "i1" }, 1191 { BaseIndex, "BaseIndex" }, 1192 { Disp8, "d8" }, 1193 { Disp16, "d16" }, 1194 { Disp32, "d32" }, 1195 { Disp32S, "d32s" }, 1196 { Disp64, "d64" }, 1197 { InOutPortReg, "InOutPortReg" }, 1198 { ShiftCount, "ShiftCount" }, 1199 { Control, "control reg" }, 1200 { Test, "test reg" }, 1201 { Debug, "debug reg" }, 1202 { FloatReg, "FReg" }, 1203 { FloatAcc, "FAcc" }, 1204 { SReg2, "SReg2" }, 1205 { SReg3, "SReg3" }, 1206 { Acc, "Acc" }, 1207 { JumpAbsolute, "Jump Absolute" }, 1208 { RegMMX, "rMMX" }, 1209 { RegXMM, "rXMM" }, 1210 { EsSeg, "es" }, 1211 { 0, "" } 1212 }; 1213 1214 static void 1215 pt (t) 1216 unsigned int t; 1217 { 1218 const struct type_name *ty; 1219 1220 for (ty = type_names; ty->mask; ty++) 1221 if (t & ty->mask) 1222 fprintf (stdout, "%s, ", ty->tname); 1223 fflush (stdout); 1224 } 1225 1226 #endif /* DEBUG386 */ 1227 1228 static bfd_reloc_code_real_type 1229 reloc (unsigned int size, 1230 int pcrel, 1231 int sign, 1232 bfd_reloc_code_real_type other) 1233 { 1234 if (other != NO_RELOC) 1235 { 1236 reloc_howto_type *reloc; 1237 1238 if (size == 8) 1239 switch (other) 1240 { 1241 case BFD_RELOC_X86_64_GOT32: 1242 return BFD_RELOC_X86_64_GOT64; 1243 break; 1244 case BFD_RELOC_X86_64_PLTOFF64: 1245 return BFD_RELOC_X86_64_PLTOFF64; 1246 break; 1247 case BFD_RELOC_X86_64_GOTPC32: 1248 other = BFD_RELOC_X86_64_GOTPC64; 1249 break; 1250 case BFD_RELOC_X86_64_GOTPCREL: 1251 other = BFD_RELOC_X86_64_GOTPCREL64; 1252 break; 1253 case BFD_RELOC_X86_64_TPOFF32: 1254 other = BFD_RELOC_X86_64_TPOFF64; 1255 break; 1256 case BFD_RELOC_X86_64_DTPOFF32: 1257 other = BFD_RELOC_X86_64_DTPOFF64; 1258 break; 1259 default: 1260 break; 1261 } 1262 1263 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ 1264 if (size == 4 && flag_code != CODE_64BIT) 1265 sign = -1; 1266 1267 reloc = bfd_reloc_type_lookup (stdoutput, other); 1268 if (!reloc) 1269 as_bad (_("unknown relocation (%u)"), other); 1270 else if (size != bfd_get_reloc_size (reloc)) 1271 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), 1272 bfd_get_reloc_size (reloc), 1273 size); 1274 else if (pcrel && !reloc->pc_relative) 1275 as_bad (_("non-pc-relative relocation for pc-relative field")); 1276 else if ((reloc->complain_on_overflow == complain_overflow_signed 1277 && !sign) 1278 || (reloc->complain_on_overflow == complain_overflow_unsigned 1279 && sign > 0)) 1280 as_bad (_("relocated field and relocation type differ in signedness")); 1281 else 1282 return other; 1283 return NO_RELOC; 1284 } 1285 1286 if (pcrel) 1287 { 1288 if (!sign) 1289 as_bad (_("there are no unsigned pc-relative relocations")); 1290 switch (size) 1291 { 1292 case 1: return BFD_RELOC_8_PCREL; 1293 case 2: return BFD_RELOC_16_PCREL; 1294 case 4: return BFD_RELOC_32_PCREL; 1295 case 8: return BFD_RELOC_64_PCREL; 1296 } 1297 as_bad (_("cannot do %u byte pc-relative relocation"), size); 1298 } 1299 else 1300 { 1301 if (sign > 0) 1302 switch (size) 1303 { 1304 case 4: return BFD_RELOC_X86_64_32S; 1305 } 1306 else 1307 switch (size) 1308 { 1309 case 1: return BFD_RELOC_8; 1310 case 2: return BFD_RELOC_16; 1311 case 4: return BFD_RELOC_32; 1312 case 8: return BFD_RELOC_64; 1313 } 1314 as_bad (_("cannot do %s %u byte relocation"), 1315 sign > 0 ? "signed" : "unsigned", size); 1316 } 1317 1318 abort (); 1319 return BFD_RELOC_NONE; 1320 } 1321 1322 /* Here we decide which fixups can be adjusted to make them relative to 1323 the beginning of the section instead of the symbol. Basically we need 1324 to make sure that the dynamic relocations are done correctly, so in 1325 some cases we force the original symbol to be used. */ 1326 1327 int 1328 tc_i386_fix_adjustable (fixP) 1329 fixS *fixP ATTRIBUTE_UNUSED; 1330 { 1331 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 1332 if (!IS_ELF) 1333 return 1; 1334 1335 /* Don't adjust pc-relative references to merge sections in 64-bit 1336 mode. */ 1337 if (use_rela_relocations 1338 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 1339 && fixP->fx_pcrel) 1340 return 0; 1341 1342 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations 1343 and changed later by validate_fix. */ 1344 if (GOT_symbol && fixP->fx_subsy == GOT_symbol 1345 && fixP->fx_r_type == BFD_RELOC_32_PCREL) 1346 return 0; 1347 1348 /* adjust_reloc_syms doesn't know about the GOT. */ 1349 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF 1350 || fixP->fx_r_type == BFD_RELOC_386_PLT32 1351 || fixP->fx_r_type == BFD_RELOC_386_GOT32 1352 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD 1353 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM 1354 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 1355 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 1356 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE 1357 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE 1358 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 1359 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE 1360 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC 1361 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL 1362 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 1363 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 1364 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL 1365 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD 1366 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD 1367 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 1368 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 1369 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF 1370 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 1371 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 1372 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 1373 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC 1374 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL 1375 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 1376 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 1377 return 0; 1378 #endif 1379 return 1; 1380 } 1381 1382 static int intel_float_operand PARAMS ((const char *mnemonic)); 1383 1384 static int 1385 intel_float_operand (mnemonic) 1386 const char *mnemonic; 1387 { 1388 /* Note that the value returned is meaningful only for opcodes with (memory) 1389 operands, hence the code here is free to improperly handle opcodes that 1390 have no operands (for better performance and smaller code). */ 1391 1392 if (mnemonic[0] != 'f') 1393 return 0; /* non-math */ 1394 1395 switch (mnemonic[1]) 1396 { 1397 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and 1398 the fs segment override prefix not currently handled because no 1399 call path can make opcodes without operands get here */ 1400 case 'i': 1401 return 2 /* integer op */; 1402 case 'l': 1403 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) 1404 return 3; /* fldcw/fldenv */ 1405 break; 1406 case 'n': 1407 if (mnemonic[2] != 'o' /* fnop */) 1408 return 3; /* non-waiting control op */ 1409 break; 1410 case 'r': 1411 if (mnemonic[2] == 's') 1412 return 3; /* frstor/frstpm */ 1413 break; 1414 case 's': 1415 if (mnemonic[2] == 'a') 1416 return 3; /* fsave */ 1417 if (mnemonic[2] == 't') 1418 { 1419 switch (mnemonic[3]) 1420 { 1421 case 'c': /* fstcw */ 1422 case 'd': /* fstdw */ 1423 case 'e': /* fstenv */ 1424 case 's': /* fsts[gw] */ 1425 return 3; 1426 } 1427 } 1428 break; 1429 case 'x': 1430 if (mnemonic[2] == 'r' || mnemonic[2] == 's') 1431 return 0; /* fxsave/fxrstor are not really math ops */ 1432 break; 1433 } 1434 1435 return 1; 1436 } 1437 1438 /* This is the guts of the machine-dependent assembler. LINE points to a 1439 machine dependent instruction. This function is supposed to emit 1440 the frags/bytes it assembles to. */ 1441 1442 void 1443 md_assemble (line) 1444 char *line; 1445 { 1446 int j; 1447 char mnemonic[MAX_MNEM_SIZE]; 1448 1449 /* Initialize globals. */ 1450 memset (&i, '\0', sizeof (i)); 1451 for (j = 0; j < MAX_OPERANDS; j++) 1452 i.reloc[j] = NO_RELOC; 1453 memset (disp_expressions, '\0', sizeof (disp_expressions)); 1454 memset (im_expressions, '\0', sizeof (im_expressions)); 1455 save_stack_p = save_stack; 1456 1457 /* First parse an instruction mnemonic & call i386_operand for the operands. 1458 We assume that the scrubber has arranged it so that line[0] is the valid 1459 start of a (possibly prefixed) mnemonic. */ 1460 1461 line = parse_insn (line, mnemonic); 1462 if (line == NULL) 1463 return; 1464 1465 line = parse_operands (line, mnemonic); 1466 if (line == NULL) 1467 return; 1468 1469 /* Now we've parsed the mnemonic into a set of templates, and have the 1470 operands at hand. */ 1471 1472 /* All intel opcodes have reversed operands except for "bound" and 1473 "enter". We also don't reverse intersegment "jmp" and "call" 1474 instructions with 2 immediate operands so that the immediate segment 1475 precedes the offset, as it does when in AT&T mode. "enter" and the 1476 intersegment "jmp" and "call" instructions are the only ones that 1477 have two immediate operands. */ 1478 if (intel_syntax && i.operands > 1 1479 && (strcmp (mnemonic, "bound") != 0) 1480 && (strcmp (mnemonic, "invlpga") != 0) 1481 && !((i.types[0] & Imm) && (i.types[1] & Imm))) 1482 swap_operands (); 1483 1484 if (i.imm_operands) 1485 optimize_imm (); 1486 1487 /* Don't optimize displacement for movabs since it only takes 64bit 1488 displacement. */ 1489 if (i.disp_operands 1490 && (flag_code != CODE_64BIT 1491 || strcmp (mnemonic, "movabs") != 0)) 1492 optimize_disp (); 1493 1494 /* Next, we find a template that matches the given insn, 1495 making sure the overlap of the given operands types is consistent 1496 with the template operand types. */ 1497 1498 if (!match_template ()) 1499 return; 1500 1501 if (intel_syntax) 1502 { 1503 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ 1504 if (SYSV386_COMPAT 1505 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) 1506 i.tm.base_opcode ^= FloatR; 1507 1508 /* Zap movzx and movsx suffix. The suffix may have been set from 1509 "word ptr" or "byte ptr" on the source operand, but we'll use 1510 the suffix later to choose the destination register. */ 1511 if ((i.tm.base_opcode & ~9) == 0x0fb6) 1512 { 1513 if (i.reg_operands < 2 1514 && !i.suffix 1515 && (~i.tm.opcode_modifier 1516 & (No_bSuf 1517 | No_wSuf 1518 | No_lSuf 1519 | No_sSuf 1520 | No_xSuf 1521 | No_qSuf))) 1522 as_bad (_("ambiguous operand size for `%s'"), i.tm.name); 1523 1524 i.suffix = 0; 1525 } 1526 } 1527 1528 if (i.tm.opcode_modifier & FWait) 1529 if (!add_prefix (FWAIT_OPCODE)) 1530 return; 1531 1532 /* Check string instruction segment overrides. */ 1533 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) 1534 { 1535 if (!check_string ()) 1536 return; 1537 } 1538 1539 if (!process_suffix ()) 1540 return; 1541 1542 /* Make still unresolved immediate matches conform to size of immediate 1543 given in i.suffix. */ 1544 if (!finalize_imm ()) 1545 return; 1546 1547 if (i.types[0] & Imm1) 1548 i.imm_operands = 0; /* kludge for shift insns. */ 1549 if (i.types[0] & ImplicitRegister) 1550 i.reg_operands--; 1551 if (i.types[1] & ImplicitRegister) 1552 i.reg_operands--; 1553 if (i.types[2] & ImplicitRegister) 1554 i.reg_operands--; 1555 1556 if (i.tm.opcode_modifier & ImmExt) 1557 { 1558 expressionS *exp; 1559 1560 if ((i.tm.cpu_flags & (CpuPNI|CpuXSAVE|CpuSMAP)) && i.operands > 0) 1561 { 1562 /* These Intel Prescott New Instructions have the fixed 1563 operands with an opcode suffix which is coded in the same 1564 place as an 8-bit immediate field would be. Here we check 1565 those operands and remove them afterwards. */ 1566 unsigned int x; 1567 1568 for (x = 0; x < i.operands; x++) 1569 if (i.op[x].regs->reg_num != x) 1570 as_bad (_("can't use register '%%%s' as operand %d in '%s'."), 1571 i.op[x].regs->reg_name, x + 1, i.tm.name); 1572 i.operands = 0; 1573 } 1574 1575 /* These AMD 3DNow! and Intel Katmai New Instructions have an 1576 opcode suffix which is coded in the same place as an 8-bit 1577 immediate field would be. Here we fake an 8-bit immediate 1578 operand from the opcode suffix stored in tm.extension_opcode. */ 1579 1580 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); 1581 1582 exp = &im_expressions[i.imm_operands++]; 1583 i.op[i.operands].imms = exp; 1584 i.types[i.operands++] = Imm8; 1585 exp->X_op = O_constant; 1586 exp->X_add_number = i.tm.extension_opcode; 1587 i.tm.extension_opcode = None; 1588 } 1589 1590 /* For insns with operands there are more diddles to do to the opcode. */ 1591 if (i.operands) 1592 { 1593 if (!process_operands ()) 1594 return; 1595 } 1596 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) 1597 { 1598 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ 1599 as_warn (_("translating to `%sp'"), i.tm.name); 1600 } 1601 1602 /* Handle conversion of 'int $3' --> special int3 insn. */ 1603 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) 1604 { 1605 i.tm.base_opcode = INT3_OPCODE; 1606 i.imm_operands = 0; 1607 } 1608 1609 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) 1610 && i.op[0].disps->X_op == O_constant) 1611 { 1612 /* Convert "jmp constant" (and "call constant") to a jump (call) to 1613 the absolute address given by the constant. Since ix86 jumps and 1614 calls are pc relative, we need to generate a reloc. */ 1615 i.op[0].disps->X_add_symbol = &abs_symbol; 1616 i.op[0].disps->X_op = O_symbol; 1617 } 1618 1619 if ((i.tm.opcode_modifier & Rex64) != 0) 1620 i.rex |= REX_MODE64; 1621 1622 /* For 8 bit registers we need an empty rex prefix. Also if the 1623 instruction already has a prefix, we need to convert old 1624 registers to new ones. */ 1625 1626 if (((i.types[0] & Reg8) != 0 1627 && (i.op[0].regs->reg_flags & RegRex64) != 0) 1628 || ((i.types[1] & Reg8) != 0 1629 && (i.op[1].regs->reg_flags & RegRex64) != 0) 1630 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0) 1631 && i.rex != 0)) 1632 { 1633 int x; 1634 1635 i.rex |= REX_OPCODE; 1636 for (x = 0; x < 2; x++) 1637 { 1638 /* Look for 8 bit operand that uses old registers. */ 1639 if ((i.types[x] & Reg8) != 0 1640 && (i.op[x].regs->reg_flags & RegRex64) == 0) 1641 { 1642 /* In case it is "hi" register, give up. */ 1643 if (i.op[x].regs->reg_num > 3) 1644 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."), 1645 i.op[x].regs->reg_name); 1646 1647 /* Otherwise it is equivalent to the extended register. 1648 Since the encoding doesn't change this is merely 1649 cosmetic cleanup for debug output. */ 1650 1651 i.op[x].regs = i.op[x].regs + 8; 1652 } 1653 } 1654 } 1655 1656 if (i.rex != 0) 1657 add_prefix (REX_OPCODE | i.rex); 1658 1659 /* We are ready to output the insn. */ 1660 output_insn (); 1661 } 1662 1663 static char * 1664 parse_insn (line, mnemonic) 1665 char *line; 1666 char *mnemonic; 1667 { 1668 char *l = line; 1669 char *token_start = l; 1670 char *mnem_p; 1671 int supported; 1672 const template *t; 1673 1674 /* Non-zero if we found a prefix only acceptable with string insns. */ 1675 const char *expecting_string_instruction = NULL; 1676 1677 while (1) 1678 { 1679 mnem_p = mnemonic; 1680 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) 1681 { 1682 mnem_p++; 1683 if (mnem_p >= mnemonic + MAX_MNEM_SIZE) 1684 { 1685 as_bad (_("no such instruction: `%s'"), token_start); 1686 return NULL; 1687 } 1688 l++; 1689 } 1690 if (!is_space_char (*l) 1691 && *l != END_OF_INSN 1692 && (intel_syntax 1693 || (*l != PREFIX_SEPARATOR 1694 && *l != ','))) 1695 { 1696 as_bad (_("invalid character %s in mnemonic"), 1697 output_invalid (*l)); 1698 return NULL; 1699 } 1700 if (token_start == l) 1701 { 1702 if (!intel_syntax && *l == PREFIX_SEPARATOR) 1703 as_bad (_("expecting prefix; got nothing")); 1704 else 1705 as_bad (_("expecting mnemonic; got nothing")); 1706 return NULL; 1707 } 1708 1709 /* Look up instruction (or prefix) via hash table. */ 1710 current_templates = hash_find (op_hash, mnemonic); 1711 1712 if (*l != END_OF_INSN 1713 && (!is_space_char (*l) || l[1] != END_OF_INSN) 1714 && current_templates 1715 && (current_templates->start->opcode_modifier & IsPrefix)) 1716 { 1717 if (current_templates->start->cpu_flags 1718 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64)) 1719 { 1720 as_bad ((flag_code != CODE_64BIT 1721 ? _("`%s' is only supported in 64-bit mode") 1722 : _("`%s' is not supported in 64-bit mode")), 1723 current_templates->start->name); 1724 return NULL; 1725 } 1726 /* If we are in 16-bit mode, do not allow addr16 or data16. 1727 Similarly, in 32-bit mode, do not allow addr32 or data32. */ 1728 if ((current_templates->start->opcode_modifier & (Size16 | Size32)) 1729 && flag_code != CODE_64BIT 1730 && (((current_templates->start->opcode_modifier & Size32) != 0) 1731 ^ (flag_code == CODE_16BIT))) 1732 { 1733 as_bad (_("redundant %s prefix"), 1734 current_templates->start->name); 1735 return NULL; 1736 } 1737 /* Add prefix, checking for repeated prefixes. */ 1738 switch (add_prefix (current_templates->start->base_opcode)) 1739 { 1740 case 0: 1741 return NULL; 1742 case 2: 1743 expecting_string_instruction = current_templates->start->name; 1744 break; 1745 } 1746 /* Skip past PREFIX_SEPARATOR and reset token_start. */ 1747 token_start = ++l; 1748 } 1749 else 1750 break; 1751 } 1752 1753 if (!current_templates) 1754 { 1755 /* See if we can get a match by trimming off a suffix. */ 1756 switch (mnem_p[-1]) 1757 { 1758 case WORD_MNEM_SUFFIX: 1759 if (intel_syntax && (intel_float_operand (mnemonic) & 2)) 1760 i.suffix = SHORT_MNEM_SUFFIX; 1761 else 1762 case BYTE_MNEM_SUFFIX: 1763 case QWORD_MNEM_SUFFIX: 1764 i.suffix = mnem_p[-1]; 1765 mnem_p[-1] = '\0'; 1766 current_templates = hash_find (op_hash, mnemonic); 1767 break; 1768 case SHORT_MNEM_SUFFIX: 1769 case LONG_MNEM_SUFFIX: 1770 if (!intel_syntax) 1771 { 1772 i.suffix = mnem_p[-1]; 1773 mnem_p[-1] = '\0'; 1774 current_templates = hash_find (op_hash, mnemonic); 1775 } 1776 break; 1777 1778 /* Intel Syntax. */ 1779 case 'd': 1780 if (intel_syntax) 1781 { 1782 if (intel_float_operand (mnemonic) == 1) 1783 i.suffix = SHORT_MNEM_SUFFIX; 1784 else 1785 i.suffix = LONG_MNEM_SUFFIX; 1786 mnem_p[-1] = '\0'; 1787 current_templates = hash_find (op_hash, mnemonic); 1788 } 1789 break; 1790 } 1791 if (!current_templates) 1792 { 1793 as_bad (_("no such instruction: `%s'"), token_start); 1794 return NULL; 1795 } 1796 } 1797 1798 if (current_templates->start->opcode_modifier & (Jump | JumpByte)) 1799 { 1800 /* Check for a branch hint. We allow ",pt" and ",pn" for 1801 predict taken and predict not taken respectively. 1802 I'm not sure that branch hints actually do anything on loop 1803 and jcxz insns (JumpByte) for current Pentium4 chips. They 1804 may work in the future and it doesn't hurt to accept them 1805 now. */ 1806 if (l[0] == ',' && l[1] == 'p') 1807 { 1808 if (l[2] == 't') 1809 { 1810 if (!add_prefix (DS_PREFIX_OPCODE)) 1811 return NULL; 1812 l += 3; 1813 } 1814 else if (l[2] == 'n') 1815 { 1816 if (!add_prefix (CS_PREFIX_OPCODE)) 1817 return NULL; 1818 l += 3; 1819 } 1820 } 1821 } 1822 /* Any other comma loses. */ 1823 if (*l == ',') 1824 { 1825 as_bad (_("invalid character %s in mnemonic"), 1826 output_invalid (*l)); 1827 return NULL; 1828 } 1829 1830 /* Check if instruction is supported on specified architecture. */ 1831 supported = 0; 1832 for (t = current_templates->start; t < current_templates->end; ++t) 1833 { 1834 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64)) 1835 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))) 1836 supported |= 1; 1837 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64))) 1838 supported |= 2; 1839 } 1840 if (!(supported & 2)) 1841 { 1842 as_bad (flag_code == CODE_64BIT 1843 ? _("`%s' is not supported in 64-bit mode") 1844 : _("`%s' is only supported in 64-bit mode"), 1845 current_templates->start->name); 1846 return NULL; 1847 } 1848 if (!(supported & 1)) 1849 { 1850 as_warn (_("`%s' is not supported on `%s%s'"), 1851 current_templates->start->name, 1852 cpu_arch_name, 1853 cpu_sub_arch_name ? cpu_sub_arch_name : ""); 1854 } 1855 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT)) 1856 { 1857 as_warn (_("use .code16 to ensure correct addressing mode")); 1858 } 1859 1860 /* Check for rep/repne without a string instruction. */ 1861 if (expecting_string_instruction) 1862 { 1863 static templates override; 1864 1865 for (t = current_templates->start; t < current_templates->end; ++t) 1866 if (t->opcode_modifier & IsString) 1867 break; 1868 if (t >= current_templates->end) 1869 { 1870 as_bad (_("expecting string instruction after `%s'"), 1871 expecting_string_instruction); 1872 return NULL; 1873 } 1874 for (override.start = t; t < current_templates->end; ++t) 1875 if (!(t->opcode_modifier & IsString)) 1876 break; 1877 override.end = t; 1878 current_templates = &override; 1879 } 1880 1881 return l; 1882 } 1883 1884 static char * 1885 parse_operands (l, mnemonic) 1886 char *l; 1887 const char *mnemonic; 1888 { 1889 char *token_start; 1890 1891 /* 1 if operand is pending after ','. */ 1892 unsigned int expecting_operand = 0; 1893 1894 /* Non-zero if operand parens not balanced. */ 1895 unsigned int paren_not_balanced; 1896 1897 while (*l != END_OF_INSN) 1898 { 1899 /* Skip optional white space before operand. */ 1900 if (is_space_char (*l)) 1901 ++l; 1902 if (!is_operand_char (*l) && *l != END_OF_INSN) 1903 { 1904 as_bad (_("invalid character %s before operand %d"), 1905 output_invalid (*l), 1906 i.operands + 1); 1907 return NULL; 1908 } 1909 token_start = l; /* after white space */ 1910 paren_not_balanced = 0; 1911 while (paren_not_balanced || *l != ',') 1912 { 1913 if (*l == END_OF_INSN) 1914 { 1915 if (paren_not_balanced) 1916 { 1917 if (!intel_syntax) 1918 as_bad (_("unbalanced parenthesis in operand %d."), 1919 i.operands + 1); 1920 else 1921 as_bad (_("unbalanced brackets in operand %d."), 1922 i.operands + 1); 1923 return NULL; 1924 } 1925 else 1926 break; /* we are done */ 1927 } 1928 else if (!is_operand_char (*l) && !is_space_char (*l)) 1929 { 1930 as_bad (_("invalid character %s in operand %d"), 1931 output_invalid (*l), 1932 i.operands + 1); 1933 return NULL; 1934 } 1935 if (!intel_syntax) 1936 { 1937 if (*l == '(') 1938 ++paren_not_balanced; 1939 if (*l == ')') 1940 --paren_not_balanced; 1941 } 1942 else 1943 { 1944 if (*l == '[') 1945 ++paren_not_balanced; 1946 if (*l == ']') 1947 --paren_not_balanced; 1948 } 1949 l++; 1950 } 1951 if (l != token_start) 1952 { /* Yes, we've read in another operand. */ 1953 unsigned int operand_ok; 1954 this_operand = i.operands++; 1955 if (i.operands > MAX_OPERANDS) 1956 { 1957 as_bad (_("spurious operands; (%d operands/instruction max)"), 1958 MAX_OPERANDS); 1959 return NULL; 1960 } 1961 /* Now parse operand adding info to 'i' as we go along. */ 1962 END_STRING_AND_SAVE (l); 1963 1964 if (intel_syntax) 1965 operand_ok = 1966 i386_intel_operand (token_start, 1967 intel_float_operand (mnemonic)); 1968 else 1969 operand_ok = i386_operand (token_start); 1970 1971 RESTORE_END_STRING (l); 1972 if (!operand_ok) 1973 return NULL; 1974 } 1975 else 1976 { 1977 if (expecting_operand) 1978 { 1979 expecting_operand_after_comma: 1980 as_bad (_("expecting operand after ','; got nothing")); 1981 return NULL; 1982 } 1983 if (*l == ',') 1984 { 1985 as_bad (_("expecting operand before ','; got nothing")); 1986 return NULL; 1987 } 1988 } 1989 1990 /* Now *l must be either ',' or END_OF_INSN. */ 1991 if (*l == ',') 1992 { 1993 if (*++l == END_OF_INSN) 1994 { 1995 /* Just skip it, if it's \n complain. */ 1996 goto expecting_operand_after_comma; 1997 } 1998 expecting_operand = 1; 1999 } 2000 } 2001 return l; 2002 } 2003 2004 static void 2005 swap_operands () 2006 { 2007 union i386_op temp_op; 2008 unsigned int temp_type; 2009 enum bfd_reloc_code_real temp_reloc; 2010 int xchg1 = 0; 2011 int xchg2 = 0; 2012 2013 if (i.operands == 2) 2014 { 2015 xchg1 = 0; 2016 xchg2 = 1; 2017 } 2018 else if (i.operands == 3) 2019 { 2020 xchg1 = 0; 2021 xchg2 = 2; 2022 } 2023 temp_type = i.types[xchg2]; 2024 i.types[xchg2] = i.types[xchg1]; 2025 i.types[xchg1] = temp_type; 2026 temp_op = i.op[xchg2]; 2027 i.op[xchg2] = i.op[xchg1]; 2028 i.op[xchg1] = temp_op; 2029 temp_reloc = i.reloc[xchg2]; 2030 i.reloc[xchg2] = i.reloc[xchg1]; 2031 i.reloc[xchg1] = temp_reloc; 2032 2033 if (i.mem_operands == 2) 2034 { 2035 const seg_entry *temp_seg; 2036 temp_seg = i.seg[0]; 2037 i.seg[0] = i.seg[1]; 2038 i.seg[1] = temp_seg; 2039 } 2040 } 2041 2042 /* Try to ensure constant immediates are represented in the smallest 2043 opcode possible. */ 2044 static void 2045 optimize_imm () 2046 { 2047 char guess_suffix = 0; 2048 int op; 2049 2050 if (i.suffix) 2051 guess_suffix = i.suffix; 2052 else if (i.reg_operands) 2053 { 2054 /* Figure out a suffix from the last register operand specified. 2055 We can't do this properly yet, ie. excluding InOutPortReg, 2056 but the following works for instructions with immediates. 2057 In any case, we can't set i.suffix yet. */ 2058 for (op = i.operands; --op >= 0;) 2059 if (i.types[op] & Reg) 2060 { 2061 if (i.types[op] & Reg8) 2062 guess_suffix = BYTE_MNEM_SUFFIX; 2063 else if (i.types[op] & Reg16) 2064 guess_suffix = WORD_MNEM_SUFFIX; 2065 else if (i.types[op] & Reg32) 2066 guess_suffix = LONG_MNEM_SUFFIX; 2067 else if (i.types[op] & Reg64) 2068 guess_suffix = QWORD_MNEM_SUFFIX; 2069 break; 2070 } 2071 } 2072 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) 2073 guess_suffix = WORD_MNEM_SUFFIX; 2074 2075 for (op = i.operands; --op >= 0;) 2076 if (i.types[op] & Imm) 2077 { 2078 switch (i.op[op].imms->X_op) 2079 { 2080 case O_constant: 2081 /* If a suffix is given, this operand may be shortened. */ 2082 switch (guess_suffix) 2083 { 2084 case LONG_MNEM_SUFFIX: 2085 i.types[op] |= Imm32 | Imm64; 2086 break; 2087 case WORD_MNEM_SUFFIX: 2088 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64; 2089 break; 2090 case BYTE_MNEM_SUFFIX: 2091 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64; 2092 break; 2093 } 2094 2095 /* If this operand is at most 16 bits, convert it 2096 to a signed 16 bit number before trying to see 2097 whether it will fit in an even smaller size. 2098 This allows a 16-bit operand such as $0xffe0 to 2099 be recognised as within Imm8S range. */ 2100 if ((i.types[op] & Imm16) 2101 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) 2102 { 2103 i.op[op].imms->X_add_number = 2104 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); 2105 } 2106 if ((i.types[op] & Imm32) 2107 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) 2108 == 0)) 2109 { 2110 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number 2111 ^ ((offsetT) 1 << 31)) 2112 - ((offsetT) 1 << 31)); 2113 } 2114 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number); 2115 2116 /* We must avoid matching of Imm32 templates when 64bit 2117 only immediate is available. */ 2118 if (guess_suffix == QWORD_MNEM_SUFFIX) 2119 i.types[op] &= ~Imm32; 2120 break; 2121 2122 case O_absent: 2123 case O_register: 2124 abort (); 2125 2126 /* Symbols and expressions. */ 2127 default: 2128 /* Convert symbolic operand to proper sizes for matching, but don't 2129 prevent matching a set of insns that only supports sizes other 2130 than those matching the insn suffix. */ 2131 { 2132 unsigned int mask, allowed = 0; 2133 const template *t; 2134 2135 for (t = current_templates->start; t < current_templates->end; ++t) 2136 allowed |= t->operand_types[op]; 2137 switch (guess_suffix) 2138 { 2139 case QWORD_MNEM_SUFFIX: 2140 mask = Imm64 | Imm32S; 2141 break; 2142 case LONG_MNEM_SUFFIX: 2143 mask = Imm32; 2144 break; 2145 case WORD_MNEM_SUFFIX: 2146 mask = Imm16; 2147 break; 2148 case BYTE_MNEM_SUFFIX: 2149 mask = Imm8; 2150 break; 2151 default: 2152 mask = 0; 2153 break; 2154 } 2155 if (mask & allowed) 2156 i.types[op] &= mask; 2157 } 2158 break; 2159 } 2160 } 2161 } 2162 2163 /* Try to use the smallest displacement type too. */ 2164 static void 2165 optimize_disp () 2166 { 2167 int op; 2168 2169 for (op = i.operands; --op >= 0;) 2170 if (i.types[op] & Disp) 2171 { 2172 if (i.op[op].disps->X_op == O_constant) 2173 { 2174 offsetT disp = i.op[op].disps->X_add_number; 2175 2176 if ((i.types[op] & Disp16) 2177 && (disp & ~(offsetT) 0xffff) == 0) 2178 { 2179 /* If this operand is at most 16 bits, convert 2180 to a signed 16 bit number and don't use 64bit 2181 displacement. */ 2182 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); 2183 i.types[op] &= ~Disp64; 2184 } 2185 if ((i.types[op] & Disp32) 2186 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0) 2187 { 2188 /* If this operand is at most 32 bits, convert 2189 to a signed 32 bit number and don't use 64bit 2190 displacement. */ 2191 disp &= (((offsetT) 2 << 31) - 1); 2192 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); 2193 i.types[op] &= ~Disp64; 2194 } 2195 if (!disp && (i.types[op] & BaseIndex)) 2196 { 2197 i.types[op] &= ~Disp; 2198 i.op[op].disps = 0; 2199 i.disp_operands--; 2200 } 2201 else if (flag_code == CODE_64BIT) 2202 { 2203 if (fits_in_signed_long (disp)) 2204 { 2205 i.types[op] &= ~Disp64; 2206 i.types[op] |= Disp32S; 2207 } 2208 if (fits_in_unsigned_long (disp)) 2209 i.types[op] |= Disp32; 2210 } 2211 if ((i.types[op] & (Disp32 | Disp32S | Disp16)) 2212 && fits_in_signed_byte (disp)) 2213 i.types[op] |= Disp8; 2214 } 2215 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL 2216 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) 2217 { 2218 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, 2219 i.op[op].disps, 0, i.reloc[op]); 2220 i.types[op] &= ~Disp; 2221 } 2222 else 2223 /* We only support 64bit displacement on constants. */ 2224 i.types[op] &= ~Disp64; 2225 } 2226 } 2227 2228 static int 2229 match_template () 2230 { 2231 /* Points to template once we've found it. */ 2232 const template *t; 2233 unsigned int overlap0, overlap1, overlap2; 2234 unsigned int found_reverse_match; 2235 int suffix_check; 2236 2237 #define MATCH(overlap, given, template) \ 2238 ((overlap & ~JumpAbsolute) \ 2239 && (((given) & (BaseIndex | JumpAbsolute)) \ 2240 == ((overlap) & (BaseIndex | JumpAbsolute)))) 2241 2242 /* If given types r0 and r1 are registers they must be of the same type 2243 unless the expected operand type register overlap is null. 2244 Note that Acc in a template matches every size of reg. */ 2245 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ 2246 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \ 2247 || ((g0) & Reg) == ((g1) & Reg) \ 2248 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) 2249 2250 overlap0 = 0; 2251 overlap1 = 0; 2252 overlap2 = 0; 2253 found_reverse_match = 0; 2254 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX 2255 ? No_bSuf 2256 : (i.suffix == WORD_MNEM_SUFFIX 2257 ? No_wSuf 2258 : (i.suffix == SHORT_MNEM_SUFFIX 2259 ? No_sSuf 2260 : (i.suffix == LONG_MNEM_SUFFIX 2261 ? No_lSuf 2262 : (i.suffix == QWORD_MNEM_SUFFIX 2263 ? No_qSuf 2264 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX 2265 ? No_xSuf : 0)))))); 2266 2267 for (t = current_templates->start; t < current_templates->end; t++) 2268 { 2269 /* Must have right number of operands. */ 2270 if (i.operands != t->operands) 2271 continue; 2272 2273 /* Check the suffix, except for some instructions in intel mode. */ 2274 if ((t->opcode_modifier & suffix_check) 2275 && !(intel_syntax 2276 && (t->opcode_modifier & IgnoreSize))) 2277 continue; 2278 2279 /* In general, don't allow 64-bit operands in 32-bit mode. */ 2280 if (i.suffix == QWORD_MNEM_SUFFIX 2281 && flag_code != CODE_64BIT 2282 && (intel_syntax 2283 ? (!(t->opcode_modifier & IgnoreSize) 2284 && !intel_float_operand (t->name)) 2285 : intel_float_operand (t->name) != 2) 2286 && (!(t->operand_types[0] & (RegMMX | RegXMM)) 2287 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM))) 2288 && (t->base_opcode != 0x0fc7 2289 || t->extension_opcode != 1 /* cmpxchg8b */)) 2290 continue; 2291 2292 /* Do not verify operands when there are none. */ 2293 else if (!t->operands) 2294 { 2295 if (t->cpu_flags & ~cpu_arch_flags) 2296 continue; 2297 /* We've found a match; break out of loop. */ 2298 break; 2299 } 2300 2301 overlap0 = i.types[0] & t->operand_types[0]; 2302 switch (t->operands) 2303 { 2304 case 1: 2305 if (!MATCH (overlap0, i.types[0], t->operand_types[0])) 2306 continue; 2307 break; 2308 case 2: 2309 case 3: 2310 overlap1 = i.types[1] & t->operand_types[1]; 2311 if (!MATCH (overlap0, i.types[0], t->operand_types[0]) 2312 || !MATCH (overlap1, i.types[1], t->operand_types[1]) 2313 /* monitor in SSE3 is a very special case. The first 2314 register and the second register may have differnet 2315 sizes. */ 2316 || !((t->base_opcode == 0x0f01 2317 && t->extension_opcode == 0xc8) 2318 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], 2319 t->operand_types[0], 2320 overlap1, i.types[1], 2321 t->operand_types[1]))) 2322 { 2323 /* Check if other direction is valid ... */ 2324 if ((t->opcode_modifier & (D | FloatD)) == 0) 2325 continue; 2326 2327 /* Try reversing direction of operands. */ 2328 overlap0 = i.types[0] & t->operand_types[1]; 2329 overlap1 = i.types[1] & t->operand_types[0]; 2330 if (!MATCH (overlap0, i.types[0], t->operand_types[1]) 2331 || !MATCH (overlap1, i.types[1], t->operand_types[0]) 2332 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], 2333 t->operand_types[1], 2334 overlap1, i.types[1], 2335 t->operand_types[0])) 2336 { 2337 /* Does not match either direction. */ 2338 continue; 2339 } 2340 /* found_reverse_match holds which of D or FloatDR 2341 we've found. */ 2342 found_reverse_match = t->opcode_modifier & (D | FloatDR); 2343 } 2344 /* Found a forward 2 operand match here. */ 2345 else if (t->operands == 3) 2346 { 2347 /* Here we make use of the fact that there are no 2348 reverse match 3 operand instructions, and all 3 2349 operand instructions only need to be checked for 2350 register consistency between operands 2 and 3. */ 2351 overlap2 = i.types[2] & t->operand_types[2]; 2352 if (!MATCH (overlap2, i.types[2], t->operand_types[2]) 2353 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], 2354 t->operand_types[1], 2355 overlap2, i.types[2], 2356 t->operand_types[2])) 2357 2358 continue; 2359 } 2360 /* Found either forward/reverse 2 or 3 operand match here: 2361 slip through to break. */ 2362 } 2363 if (t->cpu_flags & ~cpu_arch_flags) 2364 { 2365 found_reverse_match = 0; 2366 continue; 2367 } 2368 /* We've found a match; break out of loop. */ 2369 break; 2370 } 2371 2372 if (t == current_templates->end) 2373 { 2374 /* We found no match. */ 2375 as_bad (_("suffix or operands invalid for `%s'"), 2376 current_templates->start->name); 2377 return 0; 2378 } 2379 2380 if (!quiet_warnings) 2381 { 2382 if (!intel_syntax 2383 && ((i.types[0] & JumpAbsolute) 2384 != (t->operand_types[0] & JumpAbsolute))) 2385 { 2386 as_warn (_("indirect %s without `*'"), t->name); 2387 } 2388 2389 if ((t->opcode_modifier & (IsPrefix | IgnoreSize)) 2390 == (IsPrefix | IgnoreSize)) 2391 { 2392 /* Warn them that a data or address size prefix doesn't 2393 affect assembly of the next line of code. */ 2394 as_warn (_("stand-alone `%s' prefix"), t->name); 2395 } 2396 } 2397 2398 /* Copy the template we found. */ 2399 i.tm = *t; 2400 if (found_reverse_match) 2401 { 2402 /* If we found a reverse match we must alter the opcode 2403 direction bit. found_reverse_match holds bits to change 2404 (different for int & float insns). */ 2405 2406 i.tm.base_opcode ^= found_reverse_match; 2407 2408 i.tm.operand_types[0] = t->operand_types[1]; 2409 i.tm.operand_types[1] = t->operand_types[0]; 2410 } 2411 2412 return 1; 2413 } 2414 2415 static int 2416 check_string () 2417 { 2418 int mem_op = (i.types[0] & AnyMem) ? 0 : 1; 2419 if ((i.tm.operand_types[mem_op] & EsSeg) != 0) 2420 { 2421 if (i.seg[0] != NULL && i.seg[0] != &es) 2422 { 2423 as_bad (_("`%s' operand %d must use `%%es' segment"), 2424 i.tm.name, 2425 mem_op + 1); 2426 return 0; 2427 } 2428 /* There's only ever one segment override allowed per instruction. 2429 This instruction possibly has a legal segment override on the 2430 second operand, so copy the segment to where non-string 2431 instructions store it, allowing common code. */ 2432 i.seg[0] = i.seg[1]; 2433 } 2434 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) 2435 { 2436 if (i.seg[1] != NULL && i.seg[1] != &es) 2437 { 2438 as_bad (_("`%s' operand %d must use `%%es' segment"), 2439 i.tm.name, 2440 mem_op + 2); 2441 return 0; 2442 } 2443 } 2444 return 1; 2445 } 2446 2447 static int 2448 process_suffix (void) 2449 { 2450 /* If matched instruction specifies an explicit instruction mnemonic 2451 suffix, use it. */ 2452 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64)) 2453 { 2454 if (i.tm.opcode_modifier & Size16) 2455 i.suffix = WORD_MNEM_SUFFIX; 2456 else if (i.tm.opcode_modifier & Size64) 2457 i.suffix = QWORD_MNEM_SUFFIX; 2458 else 2459 i.suffix = LONG_MNEM_SUFFIX; 2460 } 2461 else if (i.reg_operands) 2462 { 2463 /* If there's no instruction mnemonic suffix we try to invent one 2464 based on register operands. */ 2465 if (!i.suffix) 2466 { 2467 /* We take i.suffix from the last register operand specified, 2468 Destination register type is more significant than source 2469 register type. */ 2470 int op; 2471 2472 for (op = i.operands; --op >= 0;) 2473 if ((i.types[op] & Reg) 2474 && !(i.tm.operand_types[op] & InOutPortReg)) 2475 { 2476 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : 2477 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : 2478 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : 2479 LONG_MNEM_SUFFIX); 2480 break; 2481 } 2482 } 2483 else if (i.suffix == BYTE_MNEM_SUFFIX) 2484 { 2485 if (!check_byte_reg ()) 2486 return 0; 2487 } 2488 else if (i.suffix == LONG_MNEM_SUFFIX) 2489 { 2490 if (!check_long_reg ()) 2491 return 0; 2492 } 2493 else if (i.suffix == QWORD_MNEM_SUFFIX) 2494 { 2495 if (!check_qword_reg ()) 2496 return 0; 2497 } 2498 else if (i.suffix == WORD_MNEM_SUFFIX) 2499 { 2500 if (!check_word_reg ()) 2501 return 0; 2502 } 2503 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) 2504 /* Do nothing if the instruction is going to ignore the prefix. */ 2505 ; 2506 else 2507 abort (); 2508 } 2509 else if ((i.tm.opcode_modifier & DefaultSize) 2510 && !i.suffix 2511 /* exclude fldenv/frstor/fsave/fstenv */ 2512 && (i.tm.opcode_modifier & No_sSuf)) 2513 { 2514 i.suffix = stackop_size; 2515 } 2516 else if (intel_syntax 2517 && !i.suffix 2518 && ((i.tm.operand_types[0] & JumpAbsolute) 2519 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment)) 2520 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ 2521 && i.tm.extension_opcode <= 3))) 2522 { 2523 switch (flag_code) 2524 { 2525 case CODE_64BIT: 2526 if (!(i.tm.opcode_modifier & No_qSuf)) 2527 { 2528 i.suffix = QWORD_MNEM_SUFFIX; 2529 break; 2530 } 2531 case CODE_32BIT: 2532 if (!(i.tm.opcode_modifier & No_lSuf)) 2533 i.suffix = LONG_MNEM_SUFFIX; 2534 break; 2535 case CODE_16BIT: 2536 if (!(i.tm.opcode_modifier & No_wSuf)) 2537 i.suffix = WORD_MNEM_SUFFIX; 2538 break; 2539 } 2540 } 2541 2542 if (!i.suffix) 2543 { 2544 if (!intel_syntax) 2545 { 2546 if (i.tm.opcode_modifier & W) 2547 { 2548 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); 2549 return 0; 2550 } 2551 } 2552 else 2553 { 2554 unsigned int suffixes = ~i.tm.opcode_modifier 2555 & (No_bSuf 2556 | No_wSuf 2557 | No_lSuf 2558 | No_sSuf 2559 | No_xSuf 2560 | No_qSuf); 2561 2562 if ((i.tm.opcode_modifier & W) 2563 || ((suffixes & (suffixes - 1)) 2564 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize)))) 2565 { 2566 as_bad (_("ambiguous operand size for `%s'"), i.tm.name); 2567 return 0; 2568 } 2569 } 2570 } 2571 2572 /* Change the opcode based on the operand size given by i.suffix; 2573 We don't need to change things for byte insns. */ 2574 2575 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) 2576 { 2577 /* It's not a byte, select word/dword operation. */ 2578 if (i.tm.opcode_modifier & W) 2579 { 2580 if (i.tm.opcode_modifier & ShortForm) 2581 i.tm.base_opcode |= 8; 2582 else 2583 i.tm.base_opcode |= 1; 2584 } 2585 2586 /* Now select between word & dword operations via the operand 2587 size prefix, except for instructions that will ignore this 2588 prefix anyway. */ 2589 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8) 2590 { 2591 /* monitor in SSE3 is a very special case. The default size 2592 of AX is the size of mode. The address size override 2593 prefix will change the size of AX. */ 2594 if (i.op->regs[0].reg_type & 2595 (flag_code == CODE_32BIT ? Reg16 : Reg32)) 2596 if (!add_prefix (ADDR_PREFIX_OPCODE)) 2597 return 0; 2598 } 2599 else if (i.suffix != QWORD_MNEM_SUFFIX 2600 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX 2601 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF)) 2602 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) 2603 || (flag_code == CODE_64BIT 2604 && (i.tm.opcode_modifier & JumpByte)))) 2605 { 2606 unsigned int prefix = DATA_PREFIX_OPCODE; 2607 2608 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ 2609 prefix = ADDR_PREFIX_OPCODE; 2610 2611 if (!add_prefix (prefix)) 2612 return 0; 2613 } 2614 2615 /* Set mode64 for an operand. */ 2616 if (i.suffix == QWORD_MNEM_SUFFIX 2617 && flag_code == CODE_64BIT 2618 && (i.tm.opcode_modifier & NoRex64) == 0) 2619 i.rex |= REX_MODE64; 2620 2621 /* Size floating point instruction. */ 2622 if (i.suffix == LONG_MNEM_SUFFIX) 2623 if (i.tm.opcode_modifier & FloatMF) 2624 i.tm.base_opcode ^= 4; 2625 } 2626 2627 return 1; 2628 } 2629 2630 static int 2631 check_byte_reg (void) 2632 { 2633 int op; 2634 2635 for (op = i.operands; --op >= 0;) 2636 { 2637 /* If this is an eight bit register, it's OK. If it's the 16 or 2638 32 bit version of an eight bit register, we will just use the 2639 low portion, and that's OK too. */ 2640 if (i.types[op] & Reg8) 2641 continue; 2642 2643 /* movzx and movsx should not generate this warning. */ 2644 if (intel_syntax 2645 && (i.tm.base_opcode == 0xfb7 2646 || i.tm.base_opcode == 0xfb6 2647 || i.tm.base_opcode == 0x63 2648 || i.tm.base_opcode == 0xfbe 2649 || i.tm.base_opcode == 0xfbf)) 2650 continue; 2651 2652 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4) 2653 { 2654 /* Prohibit these changes in the 64bit mode, since the 2655 lowering is more complicated. */ 2656 if (flag_code == CODE_64BIT 2657 && (i.tm.operand_types[op] & InOutPortReg) == 0) 2658 { 2659 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2660 i.op[op].regs->reg_name, 2661 i.suffix); 2662 return 0; 2663 } 2664 #if REGISTER_WARNINGS 2665 if (!quiet_warnings 2666 && (i.tm.operand_types[op] & InOutPortReg) == 0) 2667 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), 2668 (i.op[op].regs + (i.types[op] & Reg16 2669 ? REGNAM_AL - REGNAM_AX 2670 : REGNAM_AL - REGNAM_EAX))->reg_name, 2671 i.op[op].regs->reg_name, 2672 i.suffix); 2673 #endif 2674 continue; 2675 } 2676 /* Any other register is bad. */ 2677 if (i.types[op] & (Reg | RegMMX | RegXMM 2678 | SReg2 | SReg3 2679 | Control | Debug | Test 2680 | FloatReg | FloatAcc)) 2681 { 2682 as_bad (_("`%%%s' not allowed with `%s%c'"), 2683 i.op[op].regs->reg_name, 2684 i.tm.name, 2685 i.suffix); 2686 return 0; 2687 } 2688 } 2689 return 1; 2690 } 2691 2692 static int 2693 check_long_reg () 2694 { 2695 int op; 2696 2697 for (op = i.operands; --op >= 0;) 2698 /* Reject eight bit registers, except where the template requires 2699 them. (eg. movzb) */ 2700 if ((i.types[op] & Reg8) != 0 2701 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) 2702 { 2703 as_bad (_("`%%%s' not allowed with `%s%c'"), 2704 i.op[op].regs->reg_name, 2705 i.tm.name, 2706 i.suffix); 2707 return 0; 2708 } 2709 /* Warn if the e prefix on a general reg is missing. */ 2710 else if ((!quiet_warnings || flag_code == CODE_64BIT) 2711 && (i.types[op] & Reg16) != 0 2712 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) 2713 { 2714 /* Prohibit these changes in the 64bit mode, since the 2715 lowering is more complicated. */ 2716 if (flag_code == CODE_64BIT) 2717 { 2718 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2719 i.op[op].regs->reg_name, 2720 i.suffix); 2721 return 0; 2722 } 2723 #if REGISTER_WARNINGS 2724 else 2725 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), 2726 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, 2727 i.op[op].regs->reg_name, 2728 i.suffix); 2729 #endif 2730 } 2731 /* Warn if the r prefix on a general reg is missing. */ 2732 else if ((i.types[op] & Reg64) != 0 2733 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) 2734 { 2735 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2736 i.op[op].regs->reg_name, 2737 i.suffix); 2738 return 0; 2739 } 2740 return 1; 2741 } 2742 2743 static int 2744 check_qword_reg () 2745 { 2746 int op; 2747 2748 for (op = i.operands; --op >= 0; ) 2749 /* Reject eight bit registers, except where the template requires 2750 them. (eg. movzb) */ 2751 if ((i.types[op] & Reg8) != 0 2752 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) 2753 { 2754 as_bad (_("`%%%s' not allowed with `%s%c'"), 2755 i.op[op].regs->reg_name, 2756 i.tm.name, 2757 i.suffix); 2758 return 0; 2759 } 2760 /* Warn if the e prefix on a general reg is missing. */ 2761 else if (((i.types[op] & Reg16) != 0 2762 || (i.types[op] & Reg32) != 0) 2763 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) 2764 { 2765 /* Prohibit these changes in the 64bit mode, since the 2766 lowering is more complicated. */ 2767 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2768 i.op[op].regs->reg_name, 2769 i.suffix); 2770 return 0; 2771 } 2772 return 1; 2773 } 2774 2775 static int 2776 check_word_reg () 2777 { 2778 int op; 2779 for (op = i.operands; --op >= 0;) 2780 /* Reject eight bit registers, except where the template requires 2781 them. (eg. movzb) */ 2782 if ((i.types[op] & Reg8) != 0 2783 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) 2784 { 2785 as_bad (_("`%%%s' not allowed with `%s%c'"), 2786 i.op[op].regs->reg_name, 2787 i.tm.name, 2788 i.suffix); 2789 return 0; 2790 } 2791 /* Warn if the e prefix on a general reg is present. */ 2792 else if ((!quiet_warnings || flag_code == CODE_64BIT) 2793 && (i.types[op] & Reg32) != 0 2794 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0) 2795 { 2796 /* Prohibit these changes in the 64bit mode, since the 2797 lowering is more complicated. */ 2798 if (flag_code == CODE_64BIT) 2799 { 2800 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2801 i.op[op].regs->reg_name, 2802 i.suffix); 2803 return 0; 2804 } 2805 else 2806 #if REGISTER_WARNINGS 2807 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), 2808 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, 2809 i.op[op].regs->reg_name, 2810 i.suffix); 2811 #endif 2812 } 2813 return 1; 2814 } 2815 2816 static int 2817 finalize_imm () 2818 { 2819 unsigned int overlap0, overlap1, overlap2; 2820 2821 overlap0 = i.types[0] & i.tm.operand_types[0]; 2822 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64)) 2823 && overlap0 != Imm8 && overlap0 != Imm8S 2824 && overlap0 != Imm16 && overlap0 != Imm32S 2825 && overlap0 != Imm32 && overlap0 != Imm64) 2826 { 2827 if (i.suffix) 2828 { 2829 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX 2830 ? Imm8 | Imm8S 2831 : (i.suffix == WORD_MNEM_SUFFIX 2832 ? Imm16 2833 : (i.suffix == QWORD_MNEM_SUFFIX 2834 ? Imm64 | Imm32S 2835 : Imm32))); 2836 } 2837 else if (overlap0 == (Imm16 | Imm32S | Imm32) 2838 || overlap0 == (Imm16 | Imm32) 2839 || overlap0 == (Imm16 | Imm32S)) 2840 { 2841 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) 2842 ? Imm16 : Imm32S); 2843 } 2844 if (overlap0 != Imm8 && overlap0 != Imm8S 2845 && overlap0 != Imm16 && overlap0 != Imm32S 2846 && overlap0 != Imm32 && overlap0 != Imm64) 2847 { 2848 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); 2849 return 0; 2850 } 2851 } 2852 i.types[0] = overlap0; 2853 2854 overlap1 = i.types[1] & i.tm.operand_types[1]; 2855 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64)) 2856 && overlap1 != Imm8 && overlap1 != Imm8S 2857 && overlap1 != Imm16 && overlap1 != Imm32S 2858 && overlap1 != Imm32 && overlap1 != Imm64) 2859 { 2860 if (i.suffix) 2861 { 2862 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX 2863 ? Imm8 | Imm8S 2864 : (i.suffix == WORD_MNEM_SUFFIX 2865 ? Imm16 2866 : (i.suffix == QWORD_MNEM_SUFFIX 2867 ? Imm64 | Imm32S 2868 : Imm32))); 2869 } 2870 else if (overlap1 == (Imm16 | Imm32 | Imm32S) 2871 || overlap1 == (Imm16 | Imm32) 2872 || overlap1 == (Imm16 | Imm32S)) 2873 { 2874 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) 2875 ? Imm16 : Imm32S); 2876 } 2877 if (overlap1 != Imm8 && overlap1 != Imm8S 2878 && overlap1 != Imm16 && overlap1 != Imm32S 2879 && overlap1 != Imm32 && overlap1 != Imm64) 2880 { 2881 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix); 2882 return 0; 2883 } 2884 } 2885 i.types[1] = overlap1; 2886 2887 overlap2 = i.types[2] & i.tm.operand_types[2]; 2888 assert ((overlap2 & Imm) == 0); 2889 i.types[2] = overlap2; 2890 2891 return 1; 2892 } 2893 2894 static int 2895 process_operands () 2896 { 2897 /* Default segment register this instruction will use for memory 2898 accesses. 0 means unknown. This is only for optimizing out 2899 unnecessary segment overrides. */ 2900 const seg_entry *default_seg = 0; 2901 2902 /* The imul $imm, %reg instruction is converted into 2903 imul $imm, %reg, %reg, and the clr %reg instruction 2904 is converted into xor %reg, %reg. */ 2905 if (i.tm.opcode_modifier & regKludge) 2906 { 2907 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; 2908 /* Pretend we saw the extra register operand. */ 2909 assert (i.op[first_reg_op + 1].regs == 0); 2910 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; 2911 i.types[first_reg_op + 1] = i.types[first_reg_op]; 2912 i.reg_operands = 2; 2913 } 2914 2915 if (i.tm.opcode_modifier & ShortForm) 2916 { 2917 /* The register or float register operand is in operand 0 or 1. */ 2918 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; 2919 /* Register goes in low 3 bits of opcode. */ 2920 i.tm.base_opcode |= i.op[op].regs->reg_num; 2921 if ((i.op[op].regs->reg_flags & RegRex) != 0) 2922 i.rex |= REX_EXTZ; 2923 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) 2924 { 2925 /* Warn about some common errors, but press on regardless. 2926 The first case can be generated by gcc (<= 2.8.1). */ 2927 if (i.operands == 2) 2928 { 2929 /* Reversed arguments on faddp, fsubp, etc. */ 2930 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, 2931 i.op[1].regs->reg_name, 2932 i.op[0].regs->reg_name); 2933 } 2934 else 2935 { 2936 /* Extraneous `l' suffix on fp insn. */ 2937 as_warn (_("translating to `%s %%%s'"), i.tm.name, 2938 i.op[0].regs->reg_name); 2939 } 2940 } 2941 } 2942 else if (i.tm.opcode_modifier & Modrm) 2943 { 2944 /* The opcode is completed (modulo i.tm.extension_opcode which 2945 must be put into the modrm byte). Now, we make the modrm and 2946 index base bytes based on all the info we've collected. */ 2947 2948 default_seg = build_modrm_byte (); 2949 } 2950 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) 2951 { 2952 if (i.tm.base_opcode == POP_SEG_SHORT 2953 && i.op[0].regs->reg_num == 1) 2954 { 2955 as_bad (_("you can't `pop %%cs'")); 2956 return 0; 2957 } 2958 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); 2959 if ((i.op[0].regs->reg_flags & RegRex) != 0) 2960 i.rex |= REX_EXTZ; 2961 } 2962 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32) 2963 { 2964 default_seg = &ds; 2965 } 2966 else if ((i.tm.opcode_modifier & IsString) != 0) 2967 { 2968 /* For the string instructions that allow a segment override 2969 on one of their operands, the default segment is ds. */ 2970 default_seg = &ds; 2971 } 2972 2973 if ((i.tm.base_opcode == 0x8d /* lea */ 2974 || (i.tm.cpu_flags & CpuSVME)) 2975 && i.seg[0] && !quiet_warnings) 2976 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); 2977 2978 /* If a segment was explicitly specified, and the specified segment 2979 is not the default, use an opcode prefix to select it. If we 2980 never figured out what the default segment is, then default_seg 2981 will be zero at this point, and the specified segment prefix will 2982 always be used. */ 2983 if ((i.seg[0]) && (i.seg[0] != default_seg)) 2984 { 2985 if (!add_prefix (i.seg[0]->seg_prefix)) 2986 return 0; 2987 } 2988 return 1; 2989 } 2990 2991 static const seg_entry * 2992 build_modrm_byte () 2993 { 2994 const seg_entry *default_seg = 0; 2995 2996 /* i.reg_operands MUST be the number of real register operands; 2997 implicit registers do not count. */ 2998 if (i.reg_operands == 2) 2999 { 3000 unsigned int source, dest; 3001 source = ((i.types[0] 3002 & (Reg | RegMMX | RegXMM 3003 | SReg2 | SReg3 3004 | Control | Debug | Test)) 3005 ? 0 : 1); 3006 dest = source + 1; 3007 3008 i.rm.mode = 3; 3009 /* One of the register operands will be encoded in the i.tm.reg 3010 field, the other in the combined i.tm.mode and i.tm.regmem 3011 fields. If no form of this instruction supports a memory 3012 destination operand, then we assume the source operand may 3013 sometimes be a memory operand and so we need to store the 3014 destination in the i.rm.reg field. */ 3015 if ((i.tm.operand_types[dest] & AnyMem) == 0) 3016 { 3017 i.rm.reg = i.op[dest].regs->reg_num; 3018 i.rm.regmem = i.op[source].regs->reg_num; 3019 if ((i.op[dest].regs->reg_flags & RegRex) != 0) 3020 i.rex |= REX_EXTX; 3021 if ((i.op[source].regs->reg_flags & RegRex) != 0) 3022 i.rex |= REX_EXTZ; 3023 } 3024 else 3025 { 3026 i.rm.reg = i.op[source].regs->reg_num; 3027 i.rm.regmem = i.op[dest].regs->reg_num; 3028 if ((i.op[dest].regs->reg_flags & RegRex) != 0) 3029 i.rex |= REX_EXTZ; 3030 if ((i.op[source].regs->reg_flags & RegRex) != 0) 3031 i.rex |= REX_EXTX; 3032 } 3033 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ))) 3034 { 3035 if (!((i.types[0] | i.types[1]) & Control)) 3036 abort (); 3037 i.rex &= ~(REX_EXTX | REX_EXTZ); 3038 add_prefix (LOCK_PREFIX_OPCODE); 3039 } 3040 } 3041 else 3042 { /* If it's not 2 reg operands... */ 3043 if (i.mem_operands) 3044 { 3045 unsigned int fake_zero_displacement = 0; 3046 unsigned int op = ((i.types[0] & AnyMem) 3047 ? 0 3048 : (i.types[1] & AnyMem) ? 1 : 2); 3049 3050 default_seg = &ds; 3051 3052 if (i.base_reg == 0) 3053 { 3054 i.rm.mode = 0; 3055 if (!i.disp_operands) 3056 fake_zero_displacement = 1; 3057 if (i.index_reg == 0) 3058 { 3059 /* Operand is just <disp> */ 3060 if (flag_code == CODE_64BIT) 3061 { 3062 /* 64bit mode overwrites the 32bit absolute 3063 addressing by RIP relative addressing and 3064 absolute addressing is encoded by one of the 3065 redundant SIB forms. */ 3066 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 3067 i.sib.base = NO_BASE_REGISTER; 3068 i.sib.index = NO_INDEX_REGISTER; 3069 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32); 3070 } 3071 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) 3072 { 3073 i.rm.regmem = NO_BASE_REGISTER_16; 3074 i.types[op] = Disp16; 3075 } 3076 else 3077 { 3078 i.rm.regmem = NO_BASE_REGISTER; 3079 i.types[op] = Disp32; 3080 } 3081 } 3082 else /* !i.base_reg && i.index_reg */ 3083 { 3084 i.sib.index = i.index_reg->reg_num; 3085 i.sib.base = NO_BASE_REGISTER; 3086 i.sib.scale = i.log2_scale_factor; 3087 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 3088 i.types[op] &= ~Disp; 3089 if (flag_code != CODE_64BIT) 3090 i.types[op] |= Disp32; /* Must be 32 bit */ 3091 else 3092 i.types[op] |= Disp32S; 3093 if ((i.index_reg->reg_flags & RegRex) != 0) 3094 i.rex |= REX_EXTY; 3095 } 3096 } 3097 /* RIP addressing for 64bit mode. */ 3098 else if (i.base_reg->reg_type == BaseIndex) 3099 { 3100 i.rm.regmem = NO_BASE_REGISTER; 3101 i.types[op] &= ~ Disp; 3102 i.types[op] |= Disp32S; 3103 i.flags[op] = Operand_PCrel; 3104 if (! i.disp_operands) 3105 fake_zero_displacement = 1; 3106 } 3107 else if (i.base_reg->reg_type & Reg16) 3108 { 3109 switch (i.base_reg->reg_num) 3110 { 3111 case 3: /* (%bx) */ 3112 if (i.index_reg == 0) 3113 i.rm.regmem = 7; 3114 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ 3115 i.rm.regmem = i.index_reg->reg_num - 6; 3116 break; 3117 case 5: /* (%bp) */ 3118 default_seg = &ss; 3119 if (i.index_reg == 0) 3120 { 3121 i.rm.regmem = 6; 3122 if ((i.types[op] & Disp) == 0) 3123 { 3124 /* fake (%bp) into 0(%bp) */ 3125 i.types[op] |= Disp8; 3126 fake_zero_displacement = 1; 3127 } 3128 } 3129 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ 3130 i.rm.regmem = i.index_reg->reg_num - 6 + 2; 3131 break; 3132 default: /* (%si) -> 4 or (%di) -> 5 */ 3133 i.rm.regmem = i.base_reg->reg_num - 6 + 4; 3134 } 3135 i.rm.mode = mode_from_disp_size (i.types[op]); 3136 } 3137 else /* i.base_reg and 32/64 bit mode */ 3138 { 3139 if (flag_code == CODE_64BIT 3140 && (i.types[op] & Disp)) 3141 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32); 3142 3143 i.rm.regmem = i.base_reg->reg_num; 3144 if ((i.base_reg->reg_flags & RegRex) != 0) 3145 i.rex |= REX_EXTZ; 3146 i.sib.base = i.base_reg->reg_num; 3147 /* x86-64 ignores REX prefix bit here to avoid decoder 3148 complications. */ 3149 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) 3150 { 3151 default_seg = &ss; 3152 if (i.disp_operands == 0) 3153 { 3154 fake_zero_displacement = 1; 3155 i.types[op] |= Disp8; 3156 } 3157 } 3158 else if (i.base_reg->reg_num == ESP_REG_NUM) 3159 { 3160 default_seg = &ss; 3161 } 3162 i.sib.scale = i.log2_scale_factor; 3163 if (i.index_reg == 0) 3164 { 3165 /* <disp>(%esp) becomes two byte modrm with no index 3166 register. We've already stored the code for esp 3167 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. 3168 Any base register besides %esp will not use the 3169 extra modrm byte. */ 3170 i.sib.index = NO_INDEX_REGISTER; 3171 #if !SCALE1_WHEN_NO_INDEX 3172 /* Another case where we force the second modrm byte. */ 3173 if (i.log2_scale_factor) 3174 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 3175 #endif 3176 } 3177 else 3178 { 3179 i.sib.index = i.index_reg->reg_num; 3180 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 3181 if ((i.index_reg->reg_flags & RegRex) != 0) 3182 i.rex |= REX_EXTY; 3183 } 3184 3185 if (i.disp_operands 3186 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL 3187 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) 3188 i.rm.mode = 0; 3189 else 3190 i.rm.mode = mode_from_disp_size (i.types[op]); 3191 } 3192 3193 if (fake_zero_displacement) 3194 { 3195 /* Fakes a zero displacement assuming that i.types[op] 3196 holds the correct displacement size. */ 3197 expressionS *exp; 3198 3199 assert (i.op[op].disps == 0); 3200 exp = &disp_expressions[i.disp_operands++]; 3201 i.op[op].disps = exp; 3202 exp->X_op = O_constant; 3203 exp->X_add_number = 0; 3204 exp->X_add_symbol = (symbolS *) 0; 3205 exp->X_op_symbol = (symbolS *) 0; 3206 } 3207 } 3208 3209 /* Fill in i.rm.reg or i.rm.regmem field with register operand 3210 (if any) based on i.tm.extension_opcode. Again, we must be 3211 careful to make sure that segment/control/debug/test/MMX 3212 registers are coded into the i.rm.reg field. */ 3213 if (i.reg_operands) 3214 { 3215 unsigned int op = 3216 ((i.types[0] 3217 & (Reg | RegMMX | RegXMM 3218 | SReg2 | SReg3 3219 | Control | Debug | Test)) 3220 ? 0 3221 : ((i.types[1] 3222 & (Reg | RegMMX | RegXMM 3223 | SReg2 | SReg3 3224 | Control | Debug | Test)) 3225 ? 1 3226 : 2)); 3227 /* If there is an extension opcode to put here, the register 3228 number must be put into the regmem field. */ 3229 if (i.tm.extension_opcode != None) 3230 { 3231 i.rm.regmem = i.op[op].regs->reg_num; 3232 if ((i.op[op].regs->reg_flags & RegRex) != 0) 3233 i.rex |= REX_EXTZ; 3234 } 3235 else 3236 { 3237 i.rm.reg = i.op[op].regs->reg_num; 3238 if ((i.op[op].regs->reg_flags & RegRex) != 0) 3239 i.rex |= REX_EXTX; 3240 } 3241 3242 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we 3243 must set it to 3 to indicate this is a register operand 3244 in the regmem field. */ 3245 if (!i.mem_operands) 3246 i.rm.mode = 3; 3247 } 3248 3249 /* Fill in i.rm.reg field with extension opcode (if any). */ 3250 if (i.tm.extension_opcode != None) 3251 i.rm.reg = i.tm.extension_opcode; 3252 } 3253 return default_seg; 3254 } 3255 3256 static void 3257 output_branch () 3258 { 3259 char *p; 3260 int code16; 3261 int prefix; 3262 relax_substateT subtype; 3263 symbolS *sym; 3264 offsetT off; 3265 3266 code16 = 0; 3267 if (flag_code == CODE_16BIT) 3268 code16 = CODE16; 3269 3270 prefix = 0; 3271 if (i.prefix[DATA_PREFIX] != 0) 3272 { 3273 prefix = 1; 3274 i.prefixes -= 1; 3275 code16 ^= CODE16; 3276 } 3277 /* Pentium4 branch hints. */ 3278 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ 3279 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) 3280 { 3281 prefix++; 3282 i.prefixes--; 3283 } 3284 if (i.prefix[REX_PREFIX] != 0) 3285 { 3286 prefix++; 3287 i.prefixes--; 3288 } 3289 3290 if (i.prefixes != 0 && !intel_syntax) 3291 as_warn (_("skipping prefixes on this instruction")); 3292 3293 /* It's always a symbol; End frag & setup for relax. 3294 Make sure there is enough room in this frag for the largest 3295 instruction we may generate in md_convert_frag. This is 2 3296 bytes for the opcode and room for the prefix and largest 3297 displacement. */ 3298 frag_grow (prefix + 2 + 4); 3299 /* Prefix and 1 opcode byte go in fr_fix. */ 3300 p = frag_more (prefix + 1); 3301 if (i.prefix[DATA_PREFIX] != 0) 3302 *p++ = DATA_PREFIX_OPCODE; 3303 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE 3304 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) 3305 *p++ = i.prefix[SEG_PREFIX]; 3306 if (i.prefix[REX_PREFIX] != 0) 3307 *p++ = i.prefix[REX_PREFIX]; 3308 *p = i.tm.base_opcode; 3309 3310 if ((unsigned char) *p == JUMP_PC_RELATIVE) 3311 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); 3312 else if ((cpu_arch_flags & Cpu386) != 0) 3313 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); 3314 else 3315 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); 3316 subtype |= code16; 3317 3318 sym = i.op[0].disps->X_add_symbol; 3319 off = i.op[0].disps->X_add_number; 3320 3321 if (i.op[0].disps->X_op != O_constant 3322 && i.op[0].disps->X_op != O_symbol) 3323 { 3324 /* Handle complex expressions. */ 3325 sym = make_expr_symbol (i.op[0].disps); 3326 off = 0; 3327 } 3328 3329 /* 1 possible extra opcode + 4 byte displacement go in var part. 3330 Pass reloc in fr_var. */ 3331 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); 3332 } 3333 3334 static void 3335 output_jump () 3336 { 3337 char *p; 3338 int size; 3339 fixS *fixP; 3340 3341 if (i.tm.opcode_modifier & JumpByte) 3342 { 3343 /* This is a loop or jecxz type instruction. */ 3344 size = 1; 3345 if (i.prefix[ADDR_PREFIX] != 0) 3346 { 3347 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); 3348 i.prefixes -= 1; 3349 } 3350 /* Pentium4 branch hints. */ 3351 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ 3352 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) 3353 { 3354 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); 3355 i.prefixes--; 3356 } 3357 } 3358 else 3359 { 3360 int code16; 3361 3362 code16 = 0; 3363 if (flag_code == CODE_16BIT) 3364 code16 = CODE16; 3365 3366 if (i.prefix[DATA_PREFIX] != 0) 3367 { 3368 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); 3369 i.prefixes -= 1; 3370 code16 ^= CODE16; 3371 } 3372 3373 size = 4; 3374 if (code16) 3375 size = 2; 3376 } 3377 3378 if (i.prefix[REX_PREFIX] != 0) 3379 { 3380 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); 3381 i.prefixes -= 1; 3382 } 3383 3384 if (i.prefixes != 0 && !intel_syntax) 3385 as_warn (_("skipping prefixes on this instruction")); 3386 3387 p = frag_more (1 + size); 3388 *p++ = i.tm.base_opcode; 3389 3390 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, 3391 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); 3392 3393 /* All jumps handled here are signed, but don't use a signed limit 3394 check for 32 and 16 bit jumps as we want to allow wrap around at 3395 4G and 64k respectively. */ 3396 if (size == 1) 3397 fixP->fx_signed = 1; 3398 } 3399 3400 static void 3401 output_interseg_jump () 3402 { 3403 char *p; 3404 int size; 3405 int prefix; 3406 int code16; 3407 3408 code16 = 0; 3409 if (flag_code == CODE_16BIT) 3410 code16 = CODE16; 3411 3412 prefix = 0; 3413 if (i.prefix[DATA_PREFIX] != 0) 3414 { 3415 prefix = 1; 3416 i.prefixes -= 1; 3417 code16 ^= CODE16; 3418 } 3419 if (i.prefix[REX_PREFIX] != 0) 3420 { 3421 prefix++; 3422 i.prefixes -= 1; 3423 } 3424 3425 size = 4; 3426 if (code16) 3427 size = 2; 3428 3429 if (i.prefixes != 0 && !intel_syntax) 3430 as_warn (_("skipping prefixes on this instruction")); 3431 3432 /* 1 opcode; 2 segment; offset */ 3433 p = frag_more (prefix + 1 + 2 + size); 3434 3435 if (i.prefix[DATA_PREFIX] != 0) 3436 *p++ = DATA_PREFIX_OPCODE; 3437 3438 if (i.prefix[REX_PREFIX] != 0) 3439 *p++ = i.prefix[REX_PREFIX]; 3440 3441 *p++ = i.tm.base_opcode; 3442 if (i.op[1].imms->X_op == O_constant) 3443 { 3444 offsetT n = i.op[1].imms->X_add_number; 3445 3446 if (size == 2 3447 && !fits_in_unsigned_word (n) 3448 && !fits_in_signed_word (n)) 3449 { 3450 as_bad (_("16-bit jump out of range")); 3451 return; 3452 } 3453 md_number_to_chars (p, n, size); 3454 } 3455 else 3456 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 3457 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); 3458 if (i.op[0].imms->X_op != O_constant) 3459 as_bad (_("can't handle non absolute segment in `%s'"), 3460 i.tm.name); 3461 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); 3462 } 3463 3464 static void 3465 output_insn () 3466 { 3467 fragS *insn_start_frag; 3468 offsetT insn_start_off; 3469 3470 /* Tie dwarf2 debug info to the address at the start of the insn. 3471 We can't do this after the insn has been output as the current 3472 frag may have been closed off. eg. by frag_var. */ 3473 dwarf2_emit_insn (0); 3474 3475 insn_start_frag = frag_now; 3476 insn_start_off = frag_now_fix (); 3477 3478 /* Output jumps. */ 3479 if (i.tm.opcode_modifier & Jump) 3480 output_branch (); 3481 else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) 3482 output_jump (); 3483 else if (i.tm.opcode_modifier & JumpInterSegment) 3484 output_interseg_jump (); 3485 else 3486 { 3487 /* Output normal instructions here. */ 3488 char *p; 3489 unsigned char *q; 3490 unsigned int prefix; 3491 3492 /* All opcodes on i386 have either 1 or 2 bytes. Merom New 3493 Instructions have 3 bytes. We may use one more higher byte 3494 to specify a prefix the instruction requires. */ 3495 if ((i.tm.cpu_flags & (CpuMNI|CpuAES|CpuPCLMUL)) != 0) 3496 { 3497 if (i.tm.base_opcode & 0xff000000) 3498 { 3499 prefix = (i.tm.base_opcode >> 24) & 0xff; 3500 goto check_prefix; 3501 } 3502 } 3503 else if ((i.tm.base_opcode & 0xff0000) != 0) 3504 { 3505 prefix = (i.tm.base_opcode >> 16) & 0xff; 3506 if ((i.tm.cpu_flags & CpuPadLock) != 0) 3507 { 3508 check_prefix: 3509 if (prefix != REPE_PREFIX_OPCODE 3510 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE) 3511 add_prefix (prefix); 3512 } 3513 else 3514 add_prefix (prefix); 3515 } 3516 3517 /* The prefix bytes. */ 3518 for (q = i.prefix; 3519 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); 3520 q++) 3521 { 3522 if (*q) 3523 { 3524 p = frag_more (1); 3525 md_number_to_chars (p, (valueT) *q, 1); 3526 } 3527 } 3528 3529 /* Now the opcode; be careful about word order here! */ 3530 if (fits_in_unsigned_byte (i.tm.base_opcode)) 3531 { 3532 FRAG_APPEND_1_CHAR (i.tm.base_opcode); 3533 } 3534 else 3535 { 3536 if ((i.tm.cpu_flags & (CpuMNI|CpuAES|CpuPCLMUL)) != 0) 3537 { 3538 p = frag_more (3); 3539 *p++ = (i.tm.base_opcode >> 16) & 0xff; 3540 } 3541 else 3542 p = frag_more (2); 3543 3544 /* Put out high byte first: can't use md_number_to_chars! */ 3545 *p++ = (i.tm.base_opcode >> 8) & 0xff; 3546 *p = i.tm.base_opcode & 0xff; 3547 } 3548 3549 /* Now the modrm byte and sib byte (if present). */ 3550 if (i.tm.opcode_modifier & Modrm) 3551 { 3552 p = frag_more (1); 3553 md_number_to_chars (p, 3554 (valueT) (i.rm.regmem << 0 3555 | i.rm.reg << 3 3556 | i.rm.mode << 6), 3557 1); 3558 /* If i.rm.regmem == ESP (4) 3559 && i.rm.mode != (Register mode) 3560 && not 16 bit 3561 ==> need second modrm byte. */ 3562 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING 3563 && i.rm.mode != 3 3564 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) 3565 { 3566 p = frag_more (1); 3567 md_number_to_chars (p, 3568 (valueT) (i.sib.base << 0 3569 | i.sib.index << 3 3570 | i.sib.scale << 6), 3571 1); 3572 } 3573 } 3574 3575 if (i.disp_operands) 3576 output_disp (insn_start_frag, insn_start_off); 3577 3578 if (i.imm_operands) 3579 output_imm (insn_start_frag, insn_start_off); 3580 } 3581 3582 #ifdef DEBUG386 3583 if (flag_debug) 3584 { 3585 pi ("" /*line*/, &i); 3586 } 3587 #endif /* DEBUG386 */ 3588 } 3589 3590 static void 3591 output_disp (insn_start_frag, insn_start_off) 3592 fragS *insn_start_frag; 3593 offsetT insn_start_off; 3594 { 3595 char *p; 3596 unsigned int n; 3597 3598 for (n = 0; n < i.operands; n++) 3599 { 3600 if (i.types[n] & Disp) 3601 { 3602 if (i.op[n].disps->X_op == O_constant) 3603 { 3604 int size; 3605 offsetT val; 3606 3607 size = 4; 3608 if (i.types[n] & (Disp8 | Disp16 | Disp64)) 3609 { 3610 size = 2; 3611 if (i.types[n] & Disp8) 3612 size = 1; 3613 if (i.types[n] & Disp64) 3614 size = 8; 3615 } 3616 val = offset_in_range (i.op[n].disps->X_add_number, 3617 size); 3618 p = frag_more (size); 3619 md_number_to_chars (p, val, size); 3620 } 3621 else 3622 { 3623 enum bfd_reloc_code_real reloc_type; 3624 int size = 4; 3625 int sign = 0; 3626 int pcrel = (i.flags[n] & Operand_PCrel) != 0; 3627 3628 /* The PC relative address is computed relative 3629 to the instruction boundary, so in case immediate 3630 fields follows, we need to adjust the value. */ 3631 if (pcrel && i.imm_operands) 3632 { 3633 int imm_size = 4; 3634 unsigned int n1; 3635 3636 for (n1 = 0; n1 < i.operands; n1++) 3637 if (i.types[n1] & Imm) 3638 { 3639 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64)) 3640 { 3641 imm_size = 2; 3642 if (i.types[n1] & (Imm8 | Imm8S)) 3643 imm_size = 1; 3644 if (i.types[n1] & Imm64) 3645 imm_size = 8; 3646 } 3647 break; 3648 } 3649 /* We should find the immediate. */ 3650 if (n1 == i.operands) 3651 abort (); 3652 i.op[n].disps->X_add_number -= imm_size; 3653 } 3654 3655 if (i.types[n] & Disp32S) 3656 sign = 1; 3657 3658 if (i.types[n] & (Disp16 | Disp64)) 3659 { 3660 size = 2; 3661 if (i.types[n] & Disp64) 3662 size = 8; 3663 } 3664 3665 p = frag_more (size); 3666 reloc_type = reloc (size, pcrel, sign, i.reloc[n]); 3667 if (GOT_symbol 3668 && GOT_symbol == i.op[n].disps->X_add_symbol 3669 && (((reloc_type == BFD_RELOC_32 3670 || reloc_type == BFD_RELOC_X86_64_32S 3671 || (reloc_type == BFD_RELOC_64 3672 && object_64bit)) 3673 && (i.op[n].disps->X_op == O_symbol 3674 || (i.op[n].disps->X_op == O_add 3675 && ((symbol_get_value_expression 3676 (i.op[n].disps->X_op_symbol)->X_op) 3677 == O_subtract)))) 3678 || reloc_type == BFD_RELOC_32_PCREL)) 3679 { 3680 offsetT add; 3681 3682 if (insn_start_frag == frag_now) 3683 add = (p - frag_now->fr_literal) - insn_start_off; 3684 else 3685 { 3686 fragS *fr; 3687 3688 add = insn_start_frag->fr_fix - insn_start_off; 3689 for (fr = insn_start_frag->fr_next; 3690 fr && fr != frag_now; fr = fr->fr_next) 3691 add += fr->fr_fix; 3692 add += p - frag_now->fr_literal; 3693 } 3694 3695 if (!object_64bit) 3696 { 3697 reloc_type = BFD_RELOC_386_GOTPC; 3698 i.op[n].imms->X_add_number += add; 3699 } 3700 else if (reloc_type == BFD_RELOC_64) 3701 reloc_type = BFD_RELOC_X86_64_GOTPC64; 3702 else 3703 /* Don't do the adjustment for x86-64, as there 3704 the pcrel addressing is relative to the _next_ 3705 insn, and that is taken care of in other code. */ 3706 reloc_type = BFD_RELOC_X86_64_GOTPC32; 3707 } 3708 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 3709 i.op[n].disps, pcrel, reloc_type); 3710 } 3711 } 3712 } 3713 } 3714 3715 static void 3716 output_imm (insn_start_frag, insn_start_off) 3717 fragS *insn_start_frag; 3718 offsetT insn_start_off; 3719 { 3720 char *p; 3721 unsigned int n; 3722 3723 for (n = 0; n < i.operands; n++) 3724 { 3725 if (i.types[n] & Imm) 3726 { 3727 if (i.op[n].imms->X_op == O_constant) 3728 { 3729 int size; 3730 offsetT val; 3731 3732 size = 4; 3733 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) 3734 { 3735 size = 2; 3736 if (i.types[n] & (Imm8 | Imm8S)) 3737 size = 1; 3738 else if (i.types[n] & Imm64) 3739 size = 8; 3740 } 3741 val = offset_in_range (i.op[n].imms->X_add_number, 3742 size); 3743 p = frag_more (size); 3744 md_number_to_chars (p, val, size); 3745 } 3746 else 3747 { 3748 /* Not absolute_section. 3749 Need a 32-bit fixup (don't support 8bit 3750 non-absolute imms). Try to support other 3751 sizes ... */ 3752 enum bfd_reloc_code_real reloc_type; 3753 int size = 4; 3754 int sign = 0; 3755 3756 if ((i.types[n] & (Imm32S)) 3757 && (i.suffix == QWORD_MNEM_SUFFIX 3758 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf)))) 3759 sign = 1; 3760 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) 3761 { 3762 size = 2; 3763 if (i.types[n] & (Imm8 | Imm8S)) 3764 size = 1; 3765 if (i.types[n] & Imm64) 3766 size = 8; 3767 } 3768 3769 p = frag_more (size); 3770 reloc_type = reloc (size, 0, sign, i.reloc[n]); 3771 3772 /* This is tough to explain. We end up with this one if we 3773 * have operands that look like 3774 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to 3775 * obtain the absolute address of the GOT, and it is strongly 3776 * preferable from a performance point of view to avoid using 3777 * a runtime relocation for this. The actual sequence of 3778 * instructions often look something like: 3779 * 3780 * call .L66 3781 * .L66: 3782 * popl %ebx 3783 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx 3784 * 3785 * The call and pop essentially return the absolute address 3786 * of the label .L66 and store it in %ebx. The linker itself 3787 * will ultimately change the first operand of the addl so 3788 * that %ebx points to the GOT, but to keep things simple, the 3789 * .o file must have this operand set so that it generates not 3790 * the absolute address of .L66, but the absolute address of 3791 * itself. This allows the linker itself simply treat a GOTPC 3792 * relocation as asking for a pcrel offset to the GOT to be 3793 * added in, and the addend of the relocation is stored in the 3794 * operand field for the instruction itself. 3795 * 3796 * Our job here is to fix the operand so that it would add 3797 * the correct offset so that %ebx would point to itself. The 3798 * thing that is tricky is that .-.L66 will point to the 3799 * beginning of the instruction, so we need to further modify 3800 * the operand so that it will point to itself. There are 3801 * other cases where you have something like: 3802 * 3803 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] 3804 * 3805 * and here no correction would be required. Internally in 3806 * the assembler we treat operands of this form as not being 3807 * pcrel since the '.' is explicitly mentioned, and I wonder 3808 * whether it would simplify matters to do it this way. Who 3809 * knows. In earlier versions of the PIC patches, the 3810 * pcrel_adjust field was used to store the correction, but 3811 * since the expression is not pcrel, I felt it would be 3812 * confusing to do it this way. */ 3813 3814 if ((reloc_type == BFD_RELOC_32 3815 || reloc_type == BFD_RELOC_X86_64_32S 3816 || reloc_type == BFD_RELOC_64) 3817 && GOT_symbol 3818 && GOT_symbol == i.op[n].imms->X_add_symbol 3819 && (i.op[n].imms->X_op == O_symbol 3820 || (i.op[n].imms->X_op == O_add 3821 && ((symbol_get_value_expression 3822 (i.op[n].imms->X_op_symbol)->X_op) 3823 == O_subtract)))) 3824 { 3825 offsetT add; 3826 3827 if (insn_start_frag == frag_now) 3828 add = (p - frag_now->fr_literal) - insn_start_off; 3829 else 3830 { 3831 fragS *fr; 3832 3833 add = insn_start_frag->fr_fix - insn_start_off; 3834 for (fr = insn_start_frag->fr_next; 3835 fr && fr != frag_now; fr = fr->fr_next) 3836 add += fr->fr_fix; 3837 add += p - frag_now->fr_literal; 3838 } 3839 3840 if (!object_64bit) 3841 reloc_type = BFD_RELOC_386_GOTPC; 3842 else if (size == 4) 3843 reloc_type = BFD_RELOC_X86_64_GOTPC32; 3844 else if (size == 8) 3845 reloc_type = BFD_RELOC_X86_64_GOTPC64; 3846 i.op[n].imms->X_add_number += add; 3847 } 3848 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 3849 i.op[n].imms, 0, reloc_type); 3850 } 3851 } 3852 } 3853 } 3854 3855 /* x86_cons_fix_new is called via the expression parsing code when a 3856 reloc is needed. We use this hook to get the correct .got reloc. */ 3857 static enum bfd_reloc_code_real got_reloc = NO_RELOC; 3858 static int cons_sign = -1; 3859 3860 void 3861 x86_cons_fix_new (fragS *frag, 3862 unsigned int off, 3863 unsigned int len, 3864 expressionS *exp) 3865 { 3866 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); 3867 3868 got_reloc = NO_RELOC; 3869 3870 #ifdef TE_PE 3871 if (exp->X_op == O_secrel) 3872 { 3873 exp->X_op = O_symbol; 3874 r = BFD_RELOC_32_SECREL; 3875 } 3876 #endif 3877 3878 fix_new_exp (frag, off, len, exp, 0, r); 3879 } 3880 3881 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT) 3882 # define lex_got(reloc, adjust, types) NULL 3883 #else 3884 /* Parse operands of the form 3885 <symbol>@GOTOFF+<nnn> 3886 and similar .plt or .got references. 3887 3888 If we find one, set up the correct relocation in RELOC and copy the 3889 input string, minus the `@GOTOFF' into a malloc'd buffer for 3890 parsing by the calling routine. Return this buffer, and if ADJUST 3891 is non-null set it to the length of the string we removed from the 3892 input line. Otherwise return NULL. */ 3893 static char * 3894 lex_got (enum bfd_reloc_code_real *reloc, 3895 int *adjust, 3896 unsigned int *types) 3897 { 3898 /* Some of the relocations depend on the size of what field is to 3899 be relocated. But in our callers i386_immediate and i386_displacement 3900 we don't yet know the operand size (this will be set by insn 3901 matching). Hence we record the word32 relocation here, 3902 and adjust the reloc according to the real size in reloc(). */ 3903 static const struct { 3904 const char *str; 3905 const enum bfd_reloc_code_real rel[2]; 3906 const unsigned int types64; 3907 } gotrel[] = { 3908 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 }, 3909 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 }, 3910 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 }, 3911 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 }, 3912 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 }, 3913 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 }, 3914 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 }, 3915 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 }, 3916 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 }, 3917 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 }, 3918 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 }, 3919 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 }, 3920 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 }, 3921 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 }, 3922 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 }, 3923 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 }, 3924 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 } 3925 }; 3926 char *cp; 3927 unsigned int j; 3928 3929 if (!IS_ELF) 3930 return NULL; 3931 3932 for (cp = input_line_pointer; *cp != '@'; cp++) 3933 if (is_end_of_line[(unsigned char) *cp]) 3934 return NULL; 3935 3936 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++) 3937 { 3938 int len; 3939 3940 len = strlen (gotrel[j].str); 3941 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) 3942 { 3943 if (gotrel[j].rel[object_64bit] != 0) 3944 { 3945 int first, second; 3946 char *tmpbuf, *past_reloc; 3947 3948 *reloc = gotrel[j].rel[object_64bit]; 3949 if (adjust) 3950 *adjust = len; 3951 3952 if (types) 3953 { 3954 if (flag_code != CODE_64BIT) 3955 *types = Imm32|Disp32; 3956 else 3957 *types = gotrel[j].types64; 3958 } 3959 3960 if (GOT_symbol == NULL) 3961 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 3962 3963 /* Replace the relocation token with ' ', so that 3964 errors like foo@GOTOFF1 will be detected. */ 3965 3966 /* The length of the first part of our input line. */ 3967 first = cp - input_line_pointer; 3968 3969 /* The second part goes from after the reloc token until 3970 (and including) an end_of_line char. Don't use strlen 3971 here as the end_of_line char may not be a NUL. */ 3972 past_reloc = cp + 1 + len; 3973 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; ) 3974 ; 3975 second = cp - past_reloc; 3976 3977 /* Allocate and copy string. The trailing NUL shouldn't 3978 be necessary, but be safe. */ 3979 tmpbuf = xmalloc (first + second + 2); 3980 memcpy (tmpbuf, input_line_pointer, first); 3981 tmpbuf[first] = ' '; 3982 memcpy (tmpbuf + first + 1, past_reloc, second); 3983 tmpbuf[first + second + 1] = '\0'; 3984 return tmpbuf; 3985 } 3986 3987 as_bad (_("@%s reloc is not supported with %d-bit output format"), 3988 gotrel[j].str, 1 << (5 + object_64bit)); 3989 return NULL; 3990 } 3991 } 3992 3993 /* Might be a symbol version string. Don't as_bad here. */ 3994 return NULL; 3995 } 3996 3997 void 3998 x86_cons (exp, size) 3999 expressionS *exp; 4000 int size; 4001 { 4002 if (size == 4 || (object_64bit && size == 8)) 4003 { 4004 /* Handle @GOTOFF and the like in an expression. */ 4005 char *save; 4006 char *gotfree_input_line; 4007 int adjust; 4008 4009 save = input_line_pointer; 4010 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); 4011 if (gotfree_input_line) 4012 input_line_pointer = gotfree_input_line; 4013 4014 expression (exp); 4015 4016 if (gotfree_input_line) 4017 { 4018 /* expression () has merrily parsed up to the end of line, 4019 or a comma - in the wrong buffer. Transfer how far 4020 input_line_pointer has moved to the right buffer. */ 4021 input_line_pointer = (save 4022 + (input_line_pointer - gotfree_input_line) 4023 + adjust); 4024 free (gotfree_input_line); 4025 } 4026 } 4027 else 4028 expression (exp); 4029 } 4030 #endif 4031 4032 static void signed_cons (int size) 4033 { 4034 if (flag_code == CODE_64BIT) 4035 cons_sign = 1; 4036 cons (size); 4037 cons_sign = -1; 4038 } 4039 4040 #ifdef TE_PE 4041 static void 4042 pe_directive_secrel (dummy) 4043 int dummy ATTRIBUTE_UNUSED; 4044 { 4045 expressionS exp; 4046 4047 do 4048 { 4049 expression (&exp); 4050 if (exp.X_op == O_symbol) 4051 exp.X_op = O_secrel; 4052 4053 emit_expr (&exp, 4); 4054 } 4055 while (*input_line_pointer++ == ','); 4056 4057 input_line_pointer--; 4058 demand_empty_rest_of_line (); 4059 } 4060 #endif 4061 4062 static int i386_immediate PARAMS ((char *)); 4063 4064 static int 4065 i386_immediate (imm_start) 4066 char *imm_start; 4067 { 4068 char *save_input_line_pointer; 4069 char *gotfree_input_line; 4070 segT exp_seg = 0; 4071 expressionS *exp; 4072 unsigned int types = ~0U; 4073 4074 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) 4075 { 4076 as_bad (_("only 1 or 2 immediate operands are allowed")); 4077 return 0; 4078 } 4079 4080 exp = &im_expressions[i.imm_operands++]; 4081 i.op[this_operand].imms = exp; 4082 4083 if (is_space_char (*imm_start)) 4084 ++imm_start; 4085 4086 save_input_line_pointer = input_line_pointer; 4087 input_line_pointer = imm_start; 4088 4089 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); 4090 if (gotfree_input_line) 4091 input_line_pointer = gotfree_input_line; 4092 4093 exp_seg = expression (exp); 4094 4095 SKIP_WHITESPACE (); 4096 if (*input_line_pointer) 4097 as_bad (_("junk `%s' after expression"), input_line_pointer); 4098 4099 input_line_pointer = save_input_line_pointer; 4100 if (gotfree_input_line) 4101 free (gotfree_input_line); 4102 4103 if (exp->X_op == O_absent || exp->X_op == O_big) 4104 { 4105 /* Missing or bad expr becomes absolute 0. */ 4106 as_bad (_("missing or invalid immediate expression `%s' taken as 0"), 4107 imm_start); 4108 exp->X_op = O_constant; 4109 exp->X_add_number = 0; 4110 exp->X_add_symbol = (symbolS *) 0; 4111 exp->X_op_symbol = (symbolS *) 0; 4112 } 4113 else if (exp->X_op == O_constant) 4114 { 4115 /* Size it properly later. */ 4116 i.types[this_operand] |= Imm64; 4117 /* If BFD64, sign extend val. */ 4118 if (!use_rela_relocations) 4119 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) 4120 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); 4121 } 4122 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 4123 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour 4124 && exp_seg != absolute_section 4125 && exp_seg != text_section 4126 && exp_seg != data_section 4127 && exp_seg != bss_section 4128 && exp_seg != undefined_section 4129 && !bfd_is_com_section (exp_seg)) 4130 { 4131 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 4132 return 0; 4133 } 4134 #endif 4135 else 4136 { 4137 /* This is an address. The size of the address will be 4138 determined later, depending on destination register, 4139 suffix, or the default for the section. */ 4140 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64; 4141 i.types[this_operand] &= types; 4142 } 4143 4144 return 1; 4145 } 4146 4147 static char *i386_scale PARAMS ((char *)); 4148 4149 static char * 4150 i386_scale (scale) 4151 char *scale; 4152 { 4153 offsetT val; 4154 char *save = input_line_pointer; 4155 4156 input_line_pointer = scale; 4157 val = get_absolute_expression (); 4158 4159 switch (val) 4160 { 4161 case 1: 4162 i.log2_scale_factor = 0; 4163 break; 4164 case 2: 4165 i.log2_scale_factor = 1; 4166 break; 4167 case 4: 4168 i.log2_scale_factor = 2; 4169 break; 4170 case 8: 4171 i.log2_scale_factor = 3; 4172 break; 4173 default: 4174 { 4175 char sep = *input_line_pointer; 4176 4177 *input_line_pointer = '\0'; 4178 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), 4179 scale); 4180 *input_line_pointer = sep; 4181 input_line_pointer = save; 4182 return NULL; 4183 } 4184 } 4185 if (i.log2_scale_factor != 0 && i.index_reg == 0) 4186 { 4187 as_warn (_("scale factor of %d without an index register"), 4188 1 << i.log2_scale_factor); 4189 #if SCALE1_WHEN_NO_INDEX 4190 i.log2_scale_factor = 0; 4191 #endif 4192 } 4193 scale = input_line_pointer; 4194 input_line_pointer = save; 4195 return scale; 4196 } 4197 4198 static int i386_displacement PARAMS ((char *, char *)); 4199 4200 static int 4201 i386_displacement (disp_start, disp_end) 4202 char *disp_start; 4203 char *disp_end; 4204 { 4205 expressionS *exp; 4206 segT exp_seg = 0; 4207 char *save_input_line_pointer; 4208 char *gotfree_input_line; 4209 int bigdisp, override; 4210 unsigned int types = Disp; 4211 4212 if ((i.types[this_operand] & JumpAbsolute) 4213 || !(current_templates->start->opcode_modifier & (Jump | JumpDword))) 4214 { 4215 bigdisp = Disp32; 4216 override = (i.prefix[ADDR_PREFIX] != 0); 4217 } 4218 else 4219 { 4220 /* For PC-relative branches, the width of the displacement 4221 is dependent upon data size, not address size. */ 4222 bigdisp = 0; 4223 override = (i.prefix[DATA_PREFIX] != 0); 4224 } 4225 if (flag_code == CODE_64BIT) 4226 { 4227 if (!bigdisp) 4228 bigdisp = (override || i.suffix == WORD_MNEM_SUFFIX) 4229 ? Disp16 4230 : Disp32S | Disp32; 4231 else if (!override) 4232 bigdisp = Disp64 | Disp32S | Disp32; 4233 } 4234 else 4235 { 4236 if (!bigdisp) 4237 { 4238 if (!override) 4239 override = (i.suffix == (flag_code != CODE_16BIT 4240 ? WORD_MNEM_SUFFIX 4241 : LONG_MNEM_SUFFIX)); 4242 bigdisp = Disp32; 4243 } 4244 if ((flag_code == CODE_16BIT) ^ override) 4245 bigdisp = Disp16; 4246 } 4247 i.types[this_operand] |= bigdisp; 4248 4249 exp = &disp_expressions[i.disp_operands]; 4250 i.op[this_operand].disps = exp; 4251 i.disp_operands++; 4252 save_input_line_pointer = input_line_pointer; 4253 input_line_pointer = disp_start; 4254 END_STRING_AND_SAVE (disp_end); 4255 4256 #ifndef GCC_ASM_O_HACK 4257 #define GCC_ASM_O_HACK 0 4258 #endif 4259 #if GCC_ASM_O_HACK 4260 END_STRING_AND_SAVE (disp_end + 1); 4261 if ((i.types[this_operand] & BaseIndex) != 0 4262 && displacement_string_end[-1] == '+') 4263 { 4264 /* This hack is to avoid a warning when using the "o" 4265 constraint within gcc asm statements. 4266 For instance: 4267 4268 #define _set_tssldt_desc(n,addr,limit,type) \ 4269 __asm__ __volatile__ ( \ 4270 "movw %w2,%0\n\t" \ 4271 "movw %w1,2+%0\n\t" \ 4272 "rorl $16,%1\n\t" \ 4273 "movb %b1,4+%0\n\t" \ 4274 "movb %4,5+%0\n\t" \ 4275 "movb $0,6+%0\n\t" \ 4276 "movb %h1,7+%0\n\t" \ 4277 "rorl $16,%1" \ 4278 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) 4279 4280 This works great except that the output assembler ends 4281 up looking a bit weird if it turns out that there is 4282 no offset. You end up producing code that looks like: 4283 4284 #APP 4285 movw $235,(%eax) 4286 movw %dx,2+(%eax) 4287 rorl $16,%edx 4288 movb %dl,4+(%eax) 4289 movb $137,5+(%eax) 4290 movb $0,6+(%eax) 4291 movb %dh,7+(%eax) 4292 rorl $16,%edx 4293 #NO_APP 4294 4295 So here we provide the missing zero. */ 4296 4297 *displacement_string_end = '0'; 4298 } 4299 #endif 4300 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); 4301 if (gotfree_input_line) 4302 input_line_pointer = gotfree_input_line; 4303 4304 exp_seg = expression (exp); 4305 4306 SKIP_WHITESPACE (); 4307 if (*input_line_pointer) 4308 as_bad (_("junk `%s' after expression"), input_line_pointer); 4309 #if GCC_ASM_O_HACK 4310 RESTORE_END_STRING (disp_end + 1); 4311 #endif 4312 RESTORE_END_STRING (disp_end); 4313 input_line_pointer = save_input_line_pointer; 4314 if (gotfree_input_line) 4315 free (gotfree_input_line); 4316 4317 /* We do this to make sure that the section symbol is in 4318 the symbol table. We will ultimately change the relocation 4319 to be relative to the beginning of the section. */ 4320 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF 4321 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL 4322 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) 4323 { 4324 if (exp->X_op != O_symbol) 4325 { 4326 as_bad (_("bad expression used with @%s"), 4327 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL 4328 ? "GOTPCREL" 4329 : "GOTOFF")); 4330 return 0; 4331 } 4332 4333 if (S_IS_LOCAL (exp->X_add_symbol) 4334 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) 4335 section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); 4336 exp->X_op = O_subtract; 4337 exp->X_op_symbol = GOT_symbol; 4338 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) 4339 i.reloc[this_operand] = BFD_RELOC_32_PCREL; 4340 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) 4341 i.reloc[this_operand] = BFD_RELOC_64; 4342 else 4343 i.reloc[this_operand] = BFD_RELOC_32; 4344 } 4345 4346 if (exp->X_op == O_absent || exp->X_op == O_big) 4347 { 4348 /* Missing or bad expr becomes absolute 0. */ 4349 as_bad (_("missing or invalid displacement expression `%s' taken as 0"), 4350 disp_start); 4351 exp->X_op = O_constant; 4352 exp->X_add_number = 0; 4353 exp->X_add_symbol = (symbolS *) 0; 4354 exp->X_op_symbol = (symbolS *) 0; 4355 } 4356 4357 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 4358 if (exp->X_op != O_constant 4359 && OUTPUT_FLAVOR == bfd_target_aout_flavour 4360 && exp_seg != absolute_section 4361 && exp_seg != text_section 4362 && exp_seg != data_section 4363 && exp_seg != bss_section 4364 && exp_seg != undefined_section 4365 && !bfd_is_com_section (exp_seg)) 4366 { 4367 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 4368 return 0; 4369 } 4370 #endif 4371 4372 if (!(i.types[this_operand] & ~Disp)) 4373 i.types[this_operand] &= types; 4374 4375 return 1; 4376 } 4377 4378 static int i386_index_check PARAMS ((const char *)); 4379 4380 /* Make sure the memory operand we've been dealt is valid. 4381 Return 1 on success, 0 on a failure. */ 4382 4383 static int 4384 i386_index_check (operand_string) 4385 const char *operand_string; 4386 { 4387 int ok; 4388 #if INFER_ADDR_PREFIX 4389 int fudged = 0; 4390 4391 tryprefix: 4392 #endif 4393 ok = 1; 4394 if ((current_templates->start->cpu_flags & CpuSVME) 4395 && current_templates->end[-1].operand_types[0] == AnyMem) 4396 { 4397 /* Memory operands of SVME insns are special in that they only allow 4398 rAX as their memory address and ignore any segment override. */ 4399 unsigned RegXX; 4400 4401 /* SKINIT is even more restrictive: it always requires EAX. */ 4402 if (strcmp (current_templates->start->name, "skinit") == 0) 4403 RegXX = Reg32; 4404 else if (flag_code == CODE_64BIT) 4405 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32; 4406 else 4407 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0) 4408 ? Reg16 4409 : Reg32; 4410 if (!i.base_reg 4411 || !(i.base_reg->reg_type & Acc) 4412 || !(i.base_reg->reg_type & RegXX) 4413 || i.index_reg 4414 || (i.types[0] & Disp)) 4415 ok = 0; 4416 } 4417 else if (flag_code == CODE_64BIT) 4418 { 4419 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32); 4420 4421 if ((i.base_reg 4422 && ((i.base_reg->reg_type & RegXX) == 0) 4423 && (i.base_reg->reg_type != BaseIndex 4424 || i.index_reg)) 4425 || (i.index_reg 4426 && ((i.index_reg->reg_type & (RegXX | BaseIndex)) 4427 != (RegXX | BaseIndex)))) 4428 ok = 0; 4429 } 4430 else 4431 { 4432 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) 4433 { 4434 /* 16bit checks. */ 4435 if ((i.base_reg 4436 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex)) 4437 != (Reg16 | BaseIndex))) 4438 || (i.index_reg 4439 && (((i.index_reg->reg_type & (Reg16 | BaseIndex)) 4440 != (Reg16 | BaseIndex)) 4441 || !(i.base_reg 4442 && i.base_reg->reg_num < 6 4443 && i.index_reg->reg_num >= 6 4444 && i.log2_scale_factor == 0)))) 4445 ok = 0; 4446 } 4447 else 4448 { 4449 /* 32bit checks. */ 4450 if ((i.base_reg 4451 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) 4452 || (i.index_reg 4453 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex)) 4454 != (Reg32 | BaseIndex)))) 4455 ok = 0; 4456 } 4457 } 4458 if (!ok) 4459 { 4460 #if INFER_ADDR_PREFIX 4461 if (i.prefix[ADDR_PREFIX] == 0) 4462 { 4463 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; 4464 i.prefixes += 1; 4465 /* Change the size of any displacement too. At most one of 4466 Disp16 or Disp32 is set. 4467 FIXME. There doesn't seem to be any real need for separate 4468 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. 4469 Removing them would probably clean up the code quite a lot. */ 4470 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32))) 4471 i.types[this_operand] ^= (Disp16 | Disp32); 4472 fudged = 1; 4473 goto tryprefix; 4474 } 4475 if (fudged) 4476 as_bad (_("`%s' is not a valid base/index expression"), 4477 operand_string); 4478 else 4479 #endif 4480 as_bad (_("`%s' is not a valid %s bit base/index expression"), 4481 operand_string, 4482 flag_code_names[flag_code]); 4483 } 4484 return ok; 4485 } 4486 4487 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero 4488 on error. */ 4489 4490 static int 4491 i386_operand (operand_string) 4492 char *operand_string; 4493 { 4494 const reg_entry *r; 4495 char *end_op; 4496 char *op_string = operand_string; 4497 4498 if (is_space_char (*op_string)) 4499 ++op_string; 4500 4501 /* We check for an absolute prefix (differentiating, 4502 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ 4503 if (*op_string == ABSOLUTE_PREFIX) 4504 { 4505 ++op_string; 4506 if (is_space_char (*op_string)) 4507 ++op_string; 4508 i.types[this_operand] |= JumpAbsolute; 4509 } 4510 4511 /* Check if operand is a register. */ 4512 if ((r = parse_register (op_string, &end_op)) != NULL) 4513 { 4514 /* Check for a segment override by searching for ':' after a 4515 segment register. */ 4516 op_string = end_op; 4517 if (is_space_char (*op_string)) 4518 ++op_string; 4519 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) 4520 { 4521 switch (r->reg_num) 4522 { 4523 case 0: 4524 i.seg[i.mem_operands] = &es; 4525 break; 4526 case 1: 4527 i.seg[i.mem_operands] = &cs; 4528 break; 4529 case 2: 4530 i.seg[i.mem_operands] = &ss; 4531 break; 4532 case 3: 4533 i.seg[i.mem_operands] = &ds; 4534 break; 4535 case 4: 4536 i.seg[i.mem_operands] = &fs; 4537 break; 4538 case 5: 4539 i.seg[i.mem_operands] = &gs; 4540 break; 4541 } 4542 4543 /* Skip the ':' and whitespace. */ 4544 ++op_string; 4545 if (is_space_char (*op_string)) 4546 ++op_string; 4547 4548 if (!is_digit_char (*op_string) 4549 && !is_identifier_char (*op_string) 4550 && *op_string != '(' 4551 && *op_string != ABSOLUTE_PREFIX) 4552 { 4553 as_bad (_("bad memory operand `%s'"), op_string); 4554 return 0; 4555 } 4556 /* Handle case of %es:*foo. */ 4557 if (*op_string == ABSOLUTE_PREFIX) 4558 { 4559 ++op_string; 4560 if (is_space_char (*op_string)) 4561 ++op_string; 4562 i.types[this_operand] |= JumpAbsolute; 4563 } 4564 goto do_memory_reference; 4565 } 4566 if (*op_string) 4567 { 4568 as_bad (_("junk `%s' after register"), op_string); 4569 return 0; 4570 } 4571 i.types[this_operand] |= r->reg_type & ~BaseIndex; 4572 i.op[this_operand].regs = r; 4573 i.reg_operands++; 4574 } 4575 else if (*op_string == REGISTER_PREFIX) 4576 { 4577 as_bad (_("bad register name `%s'"), op_string); 4578 return 0; 4579 } 4580 else if (*op_string == IMMEDIATE_PREFIX) 4581 { 4582 ++op_string; 4583 if (i.types[this_operand] & JumpAbsolute) 4584 { 4585 as_bad (_("immediate operand illegal with absolute jump")); 4586 return 0; 4587 } 4588 if (!i386_immediate (op_string)) 4589 return 0; 4590 } 4591 else if (is_digit_char (*op_string) 4592 || is_identifier_char (*op_string) 4593 || *op_string == '(') 4594 { 4595 /* This is a memory reference of some sort. */ 4596 char *base_string; 4597 4598 /* Start and end of displacement string expression (if found). */ 4599 char *displacement_string_start; 4600 char *displacement_string_end; 4601 4602 do_memory_reference: 4603 if ((i.mem_operands == 1 4604 && (current_templates->start->opcode_modifier & IsString) == 0) 4605 || i.mem_operands == 2) 4606 { 4607 as_bad (_("too many memory references for `%s'"), 4608 current_templates->start->name); 4609 return 0; 4610 } 4611 4612 /* Check for base index form. We detect the base index form by 4613 looking for an ')' at the end of the operand, searching 4614 for the '(' matching it, and finding a REGISTER_PREFIX or ',' 4615 after the '('. */ 4616 base_string = op_string + strlen (op_string); 4617 4618 --base_string; 4619 if (is_space_char (*base_string)) 4620 --base_string; 4621 4622 /* If we only have a displacement, set-up for it to be parsed later. */ 4623 displacement_string_start = op_string; 4624 displacement_string_end = base_string + 1; 4625 4626 if (*base_string == ')') 4627 { 4628 char *temp_string; 4629 unsigned int parens_balanced = 1; 4630 /* We've already checked that the number of left & right ()'s are 4631 equal, so this loop will not be infinite. */ 4632 do 4633 { 4634 base_string--; 4635 if (*base_string == ')') 4636 parens_balanced++; 4637 if (*base_string == '(') 4638 parens_balanced--; 4639 } 4640 while (parens_balanced); 4641 4642 temp_string = base_string; 4643 4644 /* Skip past '(' and whitespace. */ 4645 ++base_string; 4646 if (is_space_char (*base_string)) 4647 ++base_string; 4648 4649 if (*base_string == ',' 4650 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL)) 4651 { 4652 displacement_string_end = temp_string; 4653 4654 i.types[this_operand] |= BaseIndex; 4655 4656 if (i.base_reg) 4657 { 4658 base_string = end_op; 4659 if (is_space_char (*base_string)) 4660 ++base_string; 4661 } 4662 4663 /* There may be an index reg or scale factor here. */ 4664 if (*base_string == ',') 4665 { 4666 ++base_string; 4667 if (is_space_char (*base_string)) 4668 ++base_string; 4669 4670 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL) 4671 { 4672 base_string = end_op; 4673 if (is_space_char (*base_string)) 4674 ++base_string; 4675 if (*base_string == ',') 4676 { 4677 ++base_string; 4678 if (is_space_char (*base_string)) 4679 ++base_string; 4680 } 4681 else if (*base_string != ')') 4682 { 4683 as_bad (_("expecting `,' or `)' after index register in `%s'"), 4684 operand_string); 4685 return 0; 4686 } 4687 } 4688 else if (*base_string == REGISTER_PREFIX) 4689 { 4690 as_bad (_("bad register name `%s'"), base_string); 4691 return 0; 4692 } 4693 4694 /* Check for scale factor. */ 4695 if (*base_string != ')') 4696 { 4697 char *end_scale = i386_scale (base_string); 4698 4699 if (!end_scale) 4700 return 0; 4701 4702 base_string = end_scale; 4703 if (is_space_char (*base_string)) 4704 ++base_string; 4705 if (*base_string != ')') 4706 { 4707 as_bad (_("expecting `)' after scale factor in `%s'"), 4708 operand_string); 4709 return 0; 4710 } 4711 } 4712 else if (!i.index_reg) 4713 { 4714 as_bad (_("expecting index register or scale factor after `,'; got '%c'"), 4715 *base_string); 4716 return 0; 4717 } 4718 } 4719 else if (*base_string != ')') 4720 { 4721 as_bad (_("expecting `,' or `)' after base register in `%s'"), 4722 operand_string); 4723 return 0; 4724 } 4725 } 4726 else if (*base_string == REGISTER_PREFIX) 4727 { 4728 as_bad (_("bad register name `%s'"), base_string); 4729 return 0; 4730 } 4731 } 4732 4733 /* If there's an expression beginning the operand, parse it, 4734 assuming displacement_string_start and 4735 displacement_string_end are meaningful. */ 4736 if (displacement_string_start != displacement_string_end) 4737 { 4738 if (!i386_displacement (displacement_string_start, 4739 displacement_string_end)) 4740 return 0; 4741 } 4742 4743 /* Special case for (%dx) while doing input/output op. */ 4744 if (i.base_reg 4745 && i.base_reg->reg_type == (Reg16 | InOutPortReg) 4746 && i.index_reg == 0 4747 && i.log2_scale_factor == 0 4748 && i.seg[i.mem_operands] == 0 4749 && (i.types[this_operand] & Disp) == 0) 4750 { 4751 i.types[this_operand] = InOutPortReg; 4752 return 1; 4753 } 4754 4755 if (i386_index_check (operand_string) == 0) 4756 return 0; 4757 i.mem_operands++; 4758 } 4759 else 4760 { 4761 /* It's not a memory operand; argh! */ 4762 as_bad (_("invalid char %s beginning operand %d `%s'"), 4763 output_invalid (*op_string), 4764 this_operand + 1, 4765 op_string); 4766 return 0; 4767 } 4768 return 1; /* Normal return. */ 4769 } 4770 4771 /* md_estimate_size_before_relax() 4772 4773 Called just before relax() for rs_machine_dependent frags. The x86 4774 assembler uses these frags to handle variable size jump 4775 instructions. 4776 4777 Any symbol that is now undefined will not become defined. 4778 Return the correct fr_subtype in the frag. 4779 Return the initial "guess for variable size of frag" to caller. 4780 The guess is actually the growth beyond the fixed part. Whatever 4781 we do to grow the fixed or variable part contributes to our 4782 returned value. */ 4783 4784 int 4785 md_estimate_size_before_relax (fragP, segment) 4786 fragS *fragP; 4787 segT segment; 4788 { 4789 /* We've already got fragP->fr_subtype right; all we have to do is 4790 check for un-relaxable symbols. On an ELF system, we can't relax 4791 an externally visible symbol, because it may be overridden by a 4792 shared library. */ 4793 if (S_GET_SEGMENT (fragP->fr_symbol) != segment 4794 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 4795 || (IS_ELF 4796 && (S_IS_EXTERNAL (fragP->fr_symbol) 4797 || S_IS_WEAK (fragP->fr_symbol))) 4798 #endif 4799 ) 4800 { 4801 /* Symbol is undefined in this segment, or we need to keep a 4802 reloc so that weak symbols can be overridden. */ 4803 int size = (fragP->fr_subtype & CODE16) ? 2 : 4; 4804 enum bfd_reloc_code_real reloc_type; 4805 unsigned char *opcode; 4806 int old_fr_fix; 4807 4808 if (fragP->fr_var != NO_RELOC) 4809 reloc_type = fragP->fr_var; 4810 else if (size == 2) 4811 reloc_type = BFD_RELOC_16_PCREL; 4812 else 4813 reloc_type = BFD_RELOC_32_PCREL; 4814 4815 old_fr_fix = fragP->fr_fix; 4816 opcode = (unsigned char *) fragP->fr_opcode; 4817 4818 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) 4819 { 4820 case UNCOND_JUMP: 4821 /* Make jmp (0xeb) a (d)word displacement jump. */ 4822 opcode[0] = 0xe9; 4823 fragP->fr_fix += size; 4824 fix_new (fragP, old_fr_fix, size, 4825 fragP->fr_symbol, 4826 fragP->fr_offset, 1, 4827 reloc_type); 4828 break; 4829 4830 case COND_JUMP86: 4831 if (size == 2 4832 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) 4833 { 4834 /* Negate the condition, and branch past an 4835 unconditional jump. */ 4836 opcode[0] ^= 1; 4837 opcode[1] = 3; 4838 /* Insert an unconditional jump. */ 4839 opcode[2] = 0xe9; 4840 /* We added two extra opcode bytes, and have a two byte 4841 offset. */ 4842 fragP->fr_fix += 2 + 2; 4843 fix_new (fragP, old_fr_fix + 2, 2, 4844 fragP->fr_symbol, 4845 fragP->fr_offset, 1, 4846 reloc_type); 4847 break; 4848 } 4849 /* Fall through. */ 4850 4851 case COND_JUMP: 4852 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) 4853 { 4854 fixS *fixP; 4855 4856 fragP->fr_fix += 1; 4857 fixP = fix_new (fragP, old_fr_fix, 1, 4858 fragP->fr_symbol, 4859 fragP->fr_offset, 1, 4860 BFD_RELOC_8_PCREL); 4861 fixP->fx_signed = 1; 4862 break; 4863 } 4864 4865 /* This changes the byte-displacement jump 0x7N 4866 to the (d)word-displacement jump 0x0f,0x8N. */ 4867 opcode[1] = opcode[0] + 0x10; 4868 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 4869 /* We've added an opcode byte. */ 4870 fragP->fr_fix += 1 + size; 4871 fix_new (fragP, old_fr_fix + 1, size, 4872 fragP->fr_symbol, 4873 fragP->fr_offset, 1, 4874 reloc_type); 4875 break; 4876 4877 default: 4878 BAD_CASE (fragP->fr_subtype); 4879 break; 4880 } 4881 frag_wane (fragP); 4882 return fragP->fr_fix - old_fr_fix; 4883 } 4884 4885 /* Guess size depending on current relax state. Initially the relax 4886 state will correspond to a short jump and we return 1, because 4887 the variable part of the frag (the branch offset) is one byte 4888 long. However, we can relax a section more than once and in that 4889 case we must either set fr_subtype back to the unrelaxed state, 4890 or return the value for the appropriate branch. */ 4891 return md_relax_table[fragP->fr_subtype].rlx_length; 4892 } 4893 4894 /* Called after relax() is finished. 4895 4896 In: Address of frag. 4897 fr_type == rs_machine_dependent. 4898 fr_subtype is what the address relaxed to. 4899 4900 Out: Any fixSs and constants are set up. 4901 Caller will turn frag into a ".space 0". */ 4902 4903 void 4904 md_convert_frag (abfd, sec, fragP) 4905 bfd *abfd ATTRIBUTE_UNUSED; 4906 segT sec ATTRIBUTE_UNUSED; 4907 fragS *fragP; 4908 { 4909 unsigned char *opcode; 4910 unsigned char *where_to_put_displacement = NULL; 4911 offsetT target_address; 4912 offsetT opcode_address; 4913 unsigned int extension = 0; 4914 offsetT displacement_from_opcode_start; 4915 4916 opcode = (unsigned char *) fragP->fr_opcode; 4917 4918 /* Address we want to reach in file space. */ 4919 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; 4920 4921 /* Address opcode resides at in file space. */ 4922 opcode_address = fragP->fr_address + fragP->fr_fix; 4923 4924 /* Displacement from opcode start to fill into instruction. */ 4925 displacement_from_opcode_start = target_address - opcode_address; 4926 4927 if ((fragP->fr_subtype & BIG) == 0) 4928 { 4929 /* Don't have to change opcode. */ 4930 extension = 1; /* 1 opcode + 1 displacement */ 4931 where_to_put_displacement = &opcode[1]; 4932 } 4933 else 4934 { 4935 if (no_cond_jump_promotion 4936 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) 4937 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required")); 4938 4939 switch (fragP->fr_subtype) 4940 { 4941 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): 4942 extension = 4; /* 1 opcode + 4 displacement */ 4943 opcode[0] = 0xe9; 4944 where_to_put_displacement = &opcode[1]; 4945 break; 4946 4947 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): 4948 extension = 2; /* 1 opcode + 2 displacement */ 4949 opcode[0] = 0xe9; 4950 where_to_put_displacement = &opcode[1]; 4951 break; 4952 4953 case ENCODE_RELAX_STATE (COND_JUMP, BIG): 4954 case ENCODE_RELAX_STATE (COND_JUMP86, BIG): 4955 extension = 5; /* 2 opcode + 4 displacement */ 4956 opcode[1] = opcode[0] + 0x10; 4957 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 4958 where_to_put_displacement = &opcode[2]; 4959 break; 4960 4961 case ENCODE_RELAX_STATE (COND_JUMP, BIG16): 4962 extension = 3; /* 2 opcode + 2 displacement */ 4963 opcode[1] = opcode[0] + 0x10; 4964 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 4965 where_to_put_displacement = &opcode[2]; 4966 break; 4967 4968 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): 4969 extension = 4; 4970 opcode[0] ^= 1; 4971 opcode[1] = 3; 4972 opcode[2] = 0xe9; 4973 where_to_put_displacement = &opcode[3]; 4974 break; 4975 4976 default: 4977 BAD_CASE (fragP->fr_subtype); 4978 break; 4979 } 4980 } 4981 4982 /* If size if less then four we are sure that the operand fits, 4983 but if it's 4, then it could be that the displacement is larger 4984 then -/+ 2GB. */ 4985 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 4986 && object_64bit 4987 && ((addressT) (displacement_from_opcode_start - extension 4988 + ((addressT) 1 << 31)) 4989 > (((addressT) 2 << 31) - 1))) 4990 { 4991 as_bad_where (fragP->fr_file, fragP->fr_line, 4992 _("jump target out of range")); 4993 /* Make us emit 0. */ 4994 displacement_from_opcode_start = extension; 4995 } 4996 /* Now put displacement after opcode. */ 4997 md_number_to_chars ((char *) where_to_put_displacement, 4998 (valueT) (displacement_from_opcode_start - extension), 4999 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); 5000 fragP->fr_fix += extension; 5001 } 5002 5003 /* Size of byte displacement jmp. */ 5004 int md_short_jump_size = 2; 5005 5006 /* Size of dword displacement jmp. */ 5007 int md_long_jump_size = 5; 5008 5009 void 5010 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) 5011 char *ptr; 5012 addressT from_addr, to_addr; 5013 fragS *frag ATTRIBUTE_UNUSED; 5014 symbolS *to_symbol ATTRIBUTE_UNUSED; 5015 { 5016 offsetT offset; 5017 5018 offset = to_addr - (from_addr + 2); 5019 /* Opcode for byte-disp jump. */ 5020 md_number_to_chars (ptr, (valueT) 0xeb, 1); 5021 md_number_to_chars (ptr + 1, (valueT) offset, 1); 5022 } 5023 5024 void 5025 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) 5026 char *ptr; 5027 addressT from_addr, to_addr; 5028 fragS *frag ATTRIBUTE_UNUSED; 5029 symbolS *to_symbol ATTRIBUTE_UNUSED; 5030 { 5031 offsetT offset; 5032 5033 offset = to_addr - (from_addr + 5); 5034 md_number_to_chars (ptr, (valueT) 0xe9, 1); 5035 md_number_to_chars (ptr + 1, (valueT) offset, 4); 5036 } 5037 5038 /* Apply a fixup (fixS) to segment data, once it has been determined 5039 by our caller that we have all the info we need to fix it up. 5040 5041 On the 386, immediates, displacements, and data pointers are all in 5042 the same (little-endian) format, so we don't need to care about which 5043 we are handling. */ 5044 5045 void 5046 md_apply_fix (fixP, valP, seg) 5047 /* The fix we're to put in. */ 5048 fixS *fixP; 5049 /* Pointer to the value of the bits. */ 5050 valueT *valP; 5051 /* Segment fix is from. */ 5052 segT seg ATTRIBUTE_UNUSED; 5053 { 5054 char *p = fixP->fx_where + fixP->fx_frag->fr_literal; 5055 valueT value = *valP; 5056 5057 #if !defined (TE_Mach) 5058 if (fixP->fx_pcrel) 5059 { 5060 switch (fixP->fx_r_type) 5061 { 5062 default: 5063 break; 5064 5065 case BFD_RELOC_64: 5066 fixP->fx_r_type = BFD_RELOC_64_PCREL; 5067 break; 5068 case BFD_RELOC_32: 5069 case BFD_RELOC_X86_64_32S: 5070 fixP->fx_r_type = BFD_RELOC_32_PCREL; 5071 break; 5072 case BFD_RELOC_16: 5073 fixP->fx_r_type = BFD_RELOC_16_PCREL; 5074 break; 5075 case BFD_RELOC_8: 5076 fixP->fx_r_type = BFD_RELOC_8_PCREL; 5077 break; 5078 } 5079 } 5080 5081 if (fixP->fx_addsy != NULL 5082 && (fixP->fx_r_type == BFD_RELOC_32_PCREL 5083 || fixP->fx_r_type == BFD_RELOC_64_PCREL 5084 || fixP->fx_r_type == BFD_RELOC_16_PCREL 5085 || fixP->fx_r_type == BFD_RELOC_8_PCREL) 5086 && !use_rela_relocations) 5087 { 5088 /* This is a hack. There should be a better way to handle this. 5089 This covers for the fact that bfd_install_relocation will 5090 subtract the current location (for partial_inplace, PC relative 5091 relocations); see more below. */ 5092 #ifndef OBJ_AOUT 5093 if (IS_ELF 5094 #ifdef TE_PE 5095 || OUTPUT_FLAVOR == bfd_target_coff_flavour 5096 #endif 5097 ) 5098 value += fixP->fx_where + fixP->fx_frag->fr_address; 5099 #endif 5100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5101 if (IS_ELF) 5102 { 5103 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); 5104 5105 if ((sym_seg == seg 5106 || (symbol_section_p (fixP->fx_addsy) 5107 && sym_seg != absolute_section)) 5108 && !generic_force_reloc (fixP)) 5109 { 5110 /* Yes, we add the values in twice. This is because 5111 bfd_install_relocation subtracts them out again. I think 5112 bfd_install_relocation is broken, but I don't dare change 5113 it. FIXME. */ 5114 value += fixP->fx_where + fixP->fx_frag->fr_address; 5115 } 5116 } 5117 #endif 5118 #if defined (OBJ_COFF) && defined (TE_PE) 5119 /* For some reason, the PE format does not store a 5120 section address offset for a PC relative symbol. */ 5121 if (S_GET_SEGMENT (fixP->fx_addsy) != seg 5122 || S_IS_WEAK (fixP->fx_addsy)) 5123 value += md_pcrel_from (fixP); 5124 #endif 5125 } 5126 5127 /* Fix a few things - the dynamic linker expects certain values here, 5128 and we must not disappoint it. */ 5129 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5130 if (IS_ELF && fixP->fx_addsy) 5131 switch (fixP->fx_r_type) 5132 { 5133 case BFD_RELOC_386_PLT32: 5134 case BFD_RELOC_X86_64_PLT32: 5135 /* Make the jump instruction point to the address of the operand. At 5136 runtime we merely add the offset to the actual PLT entry. */ 5137 value = -4; 5138 break; 5139 5140 case BFD_RELOC_386_TLS_GD: 5141 case BFD_RELOC_386_TLS_LDM: 5142 case BFD_RELOC_386_TLS_IE_32: 5143 case BFD_RELOC_386_TLS_IE: 5144 case BFD_RELOC_386_TLS_GOTIE: 5145 case BFD_RELOC_386_TLS_GOTDESC: 5146 case BFD_RELOC_X86_64_TLSGD: 5147 case BFD_RELOC_X86_64_TLSLD: 5148 case BFD_RELOC_X86_64_GOTTPOFF: 5149 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 5150 value = 0; /* Fully resolved at runtime. No addend. */ 5151 /* Fallthrough */ 5152 case BFD_RELOC_386_TLS_LE: 5153 case BFD_RELOC_386_TLS_LDO_32: 5154 case BFD_RELOC_386_TLS_LE_32: 5155 case BFD_RELOC_X86_64_DTPOFF32: 5156 case BFD_RELOC_X86_64_DTPOFF64: 5157 case BFD_RELOC_X86_64_TPOFF32: 5158 case BFD_RELOC_X86_64_TPOFF64: 5159 S_SET_THREAD_LOCAL (fixP->fx_addsy); 5160 break; 5161 5162 case BFD_RELOC_386_TLS_DESC_CALL: 5163 case BFD_RELOC_X86_64_TLSDESC_CALL: 5164 value = 0; /* Fully resolved at runtime. No addend. */ 5165 S_SET_THREAD_LOCAL (fixP->fx_addsy); 5166 fixP->fx_done = 0; 5167 return; 5168 5169 case BFD_RELOC_386_GOT32: 5170 case BFD_RELOC_X86_64_GOT32: 5171 value = 0; /* Fully resolved at runtime. No addend. */ 5172 break; 5173 5174 case BFD_RELOC_VTABLE_INHERIT: 5175 case BFD_RELOC_VTABLE_ENTRY: 5176 fixP->fx_done = 0; 5177 return; 5178 5179 default: 5180 break; 5181 } 5182 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ 5183 *valP = value; 5184 #endif /* !defined (TE_Mach) */ 5185 5186 /* Are we finished with this relocation now? */ 5187 if (fixP->fx_addsy == NULL) 5188 fixP->fx_done = 1; 5189 else if (use_rela_relocations) 5190 { 5191 fixP->fx_no_overflow = 1; 5192 /* Remember value for tc_gen_reloc. */ 5193 fixP->fx_addnumber = value; 5194 value = 0; 5195 } 5196 5197 md_number_to_chars (p, value, fixP->fx_size); 5198 } 5199 5200 #define MAX_LITTLENUMS 6 5201 5202 /* Turn the string pointed to by litP into a floating point constant 5203 of type TYPE, and emit the appropriate bytes. The number of 5204 LITTLENUMS emitted is stored in *SIZEP. An error message is 5205 returned, or NULL on OK. */ 5206 5207 char * 5208 md_atof (type, litP, sizeP) 5209 int type; 5210 char *litP; 5211 int *sizeP; 5212 { 5213 int prec; 5214 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 5215 LITTLENUM_TYPE *wordP; 5216 char *t; 5217 5218 switch (type) 5219 { 5220 case 'f': 5221 case 'F': 5222 prec = 2; 5223 break; 5224 5225 case 'd': 5226 case 'D': 5227 prec = 4; 5228 break; 5229 5230 case 'x': 5231 case 'X': 5232 prec = 5; 5233 break; 5234 5235 default: 5236 *sizeP = 0; 5237 return _("Bad call to md_atof ()"); 5238 } 5239 t = atof_ieee (input_line_pointer, type, words); 5240 if (t) 5241 input_line_pointer = t; 5242 5243 *sizeP = prec * sizeof (LITTLENUM_TYPE); 5244 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with 5245 the bigendian 386. */ 5246 for (wordP = words + prec - 1; prec--;) 5247 { 5248 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); 5249 litP += sizeof (LITTLENUM_TYPE); 5250 } 5251 return 0; 5252 } 5253 5254 static char output_invalid_buf[8]; 5255 5256 static char * 5257 output_invalid (c) 5258 int c; 5259 { 5260 if (ISPRINT (c)) 5261 sprintf (output_invalid_buf, "'%c'", c); 5262 else 5263 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); 5264 return output_invalid_buf; 5265 } 5266 5267 /* REG_STRING starts *before* REGISTER_PREFIX. */ 5268 5269 static const reg_entry * 5270 parse_real_register (char *reg_string, char **end_op) 5271 { 5272 char *s = reg_string; 5273 char *p; 5274 char reg_name_given[MAX_REG_NAME_SIZE + 1]; 5275 const reg_entry *r; 5276 5277 /* Skip possible REGISTER_PREFIX and possible whitespace. */ 5278 if (*s == REGISTER_PREFIX) 5279 ++s; 5280 5281 if (is_space_char (*s)) 5282 ++s; 5283 5284 p = reg_name_given; 5285 while ((*p++ = register_chars[(unsigned char) *s]) != '\0') 5286 { 5287 if (p >= reg_name_given + MAX_REG_NAME_SIZE) 5288 return (const reg_entry *) NULL; 5289 s++; 5290 } 5291 5292 /* For naked regs, make sure that we are not dealing with an identifier. 5293 This prevents confusing an identifier like `eax_var' with register 5294 `eax'. */ 5295 if (allow_naked_reg && identifier_chars[(unsigned char) *s]) 5296 return (const reg_entry *) NULL; 5297 5298 *end_op = s; 5299 5300 r = (const reg_entry *) hash_find (reg_hash, reg_name_given); 5301 5302 /* Handle floating point regs, allowing spaces in the (i) part. */ 5303 if (r == i386_regtab /* %st is first entry of table */) 5304 { 5305 if (is_space_char (*s)) 5306 ++s; 5307 if (*s == '(') 5308 { 5309 ++s; 5310 if (is_space_char (*s)) 5311 ++s; 5312 if (*s >= '0' && *s <= '7') 5313 { 5314 r = &i386_float_regtab[*s - '0']; 5315 ++s; 5316 if (is_space_char (*s)) 5317 ++s; 5318 if (*s == ')') 5319 { 5320 *end_op = s + 1; 5321 return r; 5322 } 5323 } 5324 /* We have "%st(" then garbage. */ 5325 return (const reg_entry *) NULL; 5326 } 5327 } 5328 5329 if (r != NULL 5330 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0 5331 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer)) 5332 && flag_code != CODE_64BIT) 5333 return (const reg_entry *) NULL; 5334 5335 return r; 5336 } 5337 5338 /* REG_STRING starts *before* REGISTER_PREFIX. */ 5339 5340 static const reg_entry * 5341 parse_register (char *reg_string, char **end_op) 5342 { 5343 const reg_entry *r; 5344 5345 if (*reg_string == REGISTER_PREFIX || allow_naked_reg) 5346 r = parse_real_register (reg_string, end_op); 5347 else 5348 r = NULL; 5349 if (!r) 5350 { 5351 char *save = input_line_pointer; 5352 char c; 5353 symbolS *symbolP; 5354 5355 input_line_pointer = reg_string; 5356 c = get_symbol_end (); 5357 symbolP = symbol_find (reg_string); 5358 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) 5359 { 5360 const expressionS *e = symbol_get_value_expression (symbolP); 5361 5362 know (e->X_op == O_register); 5363 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab)); 5364 r = i386_regtab + e->X_add_number; 5365 *end_op = input_line_pointer; 5366 } 5367 *input_line_pointer = c; 5368 input_line_pointer = save; 5369 } 5370 return r; 5371 } 5372 5373 int 5374 i386_parse_name (char *name, expressionS *e, char *nextcharP) 5375 { 5376 const reg_entry *r; 5377 char *end = input_line_pointer; 5378 5379 *end = *nextcharP; 5380 r = parse_register (name, &input_line_pointer); 5381 if (r && end <= input_line_pointer) 5382 { 5383 *nextcharP = *input_line_pointer; 5384 *input_line_pointer = 0; 5385 e->X_op = O_register; 5386 e->X_add_number = r - i386_regtab; 5387 return 1; 5388 } 5389 input_line_pointer = end; 5390 *end = 0; 5391 return 0; 5392 } 5393 5394 void 5395 md_operand (expressionS *e) 5396 { 5397 if (*input_line_pointer == REGISTER_PREFIX) 5398 { 5399 char *end; 5400 const reg_entry *r = parse_real_register (input_line_pointer, &end); 5401 5402 if (r) 5403 { 5404 e->X_op = O_register; 5405 e->X_add_number = r - i386_regtab; 5406 input_line_pointer = end; 5407 } 5408 } 5409 } 5410 5411 5412 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5413 const char *md_shortopts = "kVQ:sqn"; 5414 #else 5415 const char *md_shortopts = "qn"; 5416 #endif 5417 5418 #define OPTION_32 (OPTION_MD_BASE + 0) 5419 #define OPTION_64 (OPTION_MD_BASE + 1) 5420 #define OPTION_DIVIDE (OPTION_MD_BASE + 2) 5421 5422 struct option md_longopts[] = { 5423 {"32", no_argument, NULL, OPTION_32}, 5424 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5425 {"64", no_argument, NULL, OPTION_64}, 5426 #endif 5427 {"divide", no_argument, NULL, OPTION_DIVIDE}, 5428 {NULL, no_argument, NULL, 0} 5429 }; 5430 size_t md_longopts_size = sizeof (md_longopts); 5431 5432 int 5433 md_parse_option (c, arg) 5434 int c; 5435 char *arg ATTRIBUTE_UNUSED; 5436 { 5437 switch (c) 5438 { 5439 case 'n': 5440 optimize_align_code = 0; 5441 break; 5442 5443 case 'q': 5444 quiet_warnings = 1; 5445 break; 5446 5447 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5448 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 5449 should be emitted or not. FIXME: Not implemented. */ 5450 case 'Q': 5451 break; 5452 5453 /* -V: SVR4 argument to print version ID. */ 5454 case 'V': 5455 print_version_id (); 5456 break; 5457 5458 /* -k: Ignore for FreeBSD compatibility. */ 5459 case 'k': 5460 break; 5461 5462 case 's': 5463 /* -s: On i386 Solaris, this tells the native assembler to use 5464 .stab instead of .stab.excl. We always use .stab anyhow. */ 5465 break; 5466 5467 case OPTION_64: 5468 { 5469 const char **list, **l; 5470 5471 list = bfd_target_list (); 5472 for (l = list; *l != NULL; l++) 5473 if (strcmp (*l, "elf64-x86-64") == 0) 5474 { 5475 default_arch = "x86_64"; 5476 break; 5477 } 5478 if (*l == NULL) 5479 as_fatal (_("No compiled in support for x86_64")); 5480 free (list); 5481 } 5482 break; 5483 #endif 5484 5485 case OPTION_32: 5486 default_arch = "i386"; 5487 break; 5488 5489 case OPTION_DIVIDE: 5490 #ifdef SVR4_COMMENT_CHARS 5491 { 5492 char *n, *t; 5493 const char *s; 5494 5495 n = (char *) xmalloc (strlen (i386_comment_chars) + 1); 5496 t = n; 5497 for (s = i386_comment_chars; *s != '\0'; s++) 5498 if (*s != '/') 5499 *t++ = *s; 5500 *t = '\0'; 5501 i386_comment_chars = n; 5502 } 5503 #endif 5504 break; 5505 5506 default: 5507 return 0; 5508 } 5509 return 1; 5510 } 5511 5512 void 5513 md_show_usage (stream) 5514 FILE *stream; 5515 { 5516 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5517 fprintf (stream, _("\ 5518 -Q ignored\n\ 5519 -V print assembler version number\n\ 5520 -k ignored\n")); 5521 #endif 5522 fprintf (stream, _("\ 5523 -n Do not optimize code alignment\n\ 5524 -q quieten some warnings\n")); 5525 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5526 fprintf (stream, _("\ 5527 -s ignored\n")); 5528 #endif 5529 #ifdef SVR4_COMMENT_CHARS 5530 fprintf (stream, _("\ 5531 --divide do not treat `/' as a comment character\n")); 5532 #else 5533 fprintf (stream, _("\ 5534 --divide ignored\n")); 5535 #endif 5536 } 5537 5538 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 5539 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 5540 5541 /* Pick the target format to use. */ 5542 5543 const char * 5544 i386_target_format () 5545 { 5546 if (!strcmp (default_arch, "x86_64")) 5547 set_code_flag (CODE_64BIT); 5548 else if (!strcmp (default_arch, "i386")) 5549 set_code_flag (CODE_32BIT); 5550 else 5551 as_fatal (_("Unknown architecture")); 5552 switch (OUTPUT_FLAVOR) 5553 { 5554 #ifdef OBJ_MAYBE_AOUT 5555 case bfd_target_aout_flavour: 5556 return AOUT_TARGET_FORMAT; 5557 #endif 5558 #ifdef OBJ_MAYBE_COFF 5559 case bfd_target_coff_flavour: 5560 return "coff-i386"; 5561 #endif 5562 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) 5563 case bfd_target_elf_flavour: 5564 { 5565 if (flag_code == CODE_64BIT) 5566 { 5567 object_64bit = 1; 5568 use_rela_relocations = 1; 5569 } 5570 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT; 5571 } 5572 #endif 5573 default: 5574 abort (); 5575 return NULL; 5576 } 5577 } 5578 5579 #endif /* OBJ_MAYBE_ more than one */ 5580 5581 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 5582 void i386_elf_emit_arch_note () 5583 { 5584 if (IS_ELF && cpu_arch_name != NULL) 5585 { 5586 char *p; 5587 asection *seg = now_seg; 5588 subsegT subseg = now_subseg; 5589 Elf_Internal_Note i_note; 5590 Elf_External_Note e_note; 5591 asection *note_secp; 5592 int len; 5593 5594 /* Create the .note section. */ 5595 note_secp = subseg_new (".note", 0); 5596 bfd_set_section_flags (stdoutput, 5597 note_secp, 5598 SEC_HAS_CONTENTS | SEC_READONLY); 5599 5600 /* Process the arch string. */ 5601 len = strlen (cpu_arch_name); 5602 5603 i_note.namesz = len + 1; 5604 i_note.descsz = 0; 5605 i_note.type = NT_ARCH; 5606 p = frag_more (sizeof (e_note.namesz)); 5607 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); 5608 p = frag_more (sizeof (e_note.descsz)); 5609 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); 5610 p = frag_more (sizeof (e_note.type)); 5611 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); 5612 p = frag_more (len + 1); 5613 strcpy (p, cpu_arch_name); 5614 5615 frag_align (2, 0, 0); 5616 5617 subseg_set (seg, subseg); 5618 } 5619 } 5620 #endif 5621 5622 symbolS * 5623 md_undefined_symbol (name) 5624 char *name; 5625 { 5626 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] 5627 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] 5628 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] 5629 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) 5630 { 5631 if (!GOT_symbol) 5632 { 5633 if (symbol_find (name)) 5634 as_bad (_("GOT already in symbol table")); 5635 GOT_symbol = symbol_new (name, undefined_section, 5636 (valueT) 0, &zero_address_frag); 5637 }; 5638 return GOT_symbol; 5639 } 5640 return 0; 5641 } 5642 5643 /* Round up a section size to the appropriate boundary. */ 5644 5645 valueT 5646 md_section_align (segment, size) 5647 segT segment ATTRIBUTE_UNUSED; 5648 valueT size; 5649 { 5650 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 5651 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 5652 { 5653 /* For a.out, force the section size to be aligned. If we don't do 5654 this, BFD will align it for us, but it will not write out the 5655 final bytes of the section. This may be a bug in BFD, but it is 5656 easier to fix it here since that is how the other a.out targets 5657 work. */ 5658 int align; 5659 5660 align = bfd_get_section_alignment (stdoutput, segment); 5661 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 5662 } 5663 #endif 5664 5665 return size; 5666 } 5667 5668 /* On the i386, PC-relative offsets are relative to the start of the 5669 next instruction. That is, the address of the offset, plus its 5670 size, since the offset is always the last part of the insn. */ 5671 5672 long 5673 md_pcrel_from (fixP) 5674 fixS *fixP; 5675 { 5676 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; 5677 } 5678 5679 #ifndef I386COFF 5680 5681 static void 5682 s_bss (ignore) 5683 int ignore ATTRIBUTE_UNUSED; 5684 { 5685 int temp; 5686 5687 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 5688 if (IS_ELF) 5689 obj_elf_section_change_hook (); 5690 #endif 5691 temp = get_absolute_expression (); 5692 subseg_set (bss_section, (subsegT) temp); 5693 demand_empty_rest_of_line (); 5694 } 5695 5696 #endif 5697 5698 void 5699 i386_validate_fix (fixp) 5700 fixS *fixp; 5701 { 5702 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) 5703 { 5704 if (fixp->fx_r_type == BFD_RELOC_32_PCREL) 5705 { 5706 if (!object_64bit) 5707 abort (); 5708 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; 5709 } 5710 else 5711 { 5712 if (!object_64bit) 5713 fixp->fx_r_type = BFD_RELOC_386_GOTOFF; 5714 else 5715 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; 5716 } 5717 fixp->fx_subsy = 0; 5718 } 5719 } 5720 5721 arelent * 5722 tc_gen_reloc (section, fixp) 5723 asection *section ATTRIBUTE_UNUSED; 5724 fixS *fixp; 5725 { 5726 arelent *rel; 5727 bfd_reloc_code_real_type code; 5728 5729 switch (fixp->fx_r_type) 5730 { 5731 case BFD_RELOC_X86_64_PLT32: 5732 case BFD_RELOC_X86_64_GOT32: 5733 case BFD_RELOC_X86_64_GOTPCREL: 5734 case BFD_RELOC_386_PLT32: 5735 case BFD_RELOC_386_GOT32: 5736 case BFD_RELOC_386_GOTOFF: 5737 case BFD_RELOC_386_GOTPC: 5738 case BFD_RELOC_386_TLS_GD: 5739 case BFD_RELOC_386_TLS_LDM: 5740 case BFD_RELOC_386_TLS_LDO_32: 5741 case BFD_RELOC_386_TLS_IE_32: 5742 case BFD_RELOC_386_TLS_IE: 5743 case BFD_RELOC_386_TLS_GOTIE: 5744 case BFD_RELOC_386_TLS_LE_32: 5745 case BFD_RELOC_386_TLS_LE: 5746 case BFD_RELOC_386_TLS_GOTDESC: 5747 case BFD_RELOC_386_TLS_DESC_CALL: 5748 case BFD_RELOC_X86_64_TLSGD: 5749 case BFD_RELOC_X86_64_TLSLD: 5750 case BFD_RELOC_X86_64_DTPOFF32: 5751 case BFD_RELOC_X86_64_DTPOFF64: 5752 case BFD_RELOC_X86_64_GOTTPOFF: 5753 case BFD_RELOC_X86_64_TPOFF32: 5754 case BFD_RELOC_X86_64_TPOFF64: 5755 case BFD_RELOC_X86_64_GOTOFF64: 5756 case BFD_RELOC_X86_64_GOTPC32: 5757 case BFD_RELOC_X86_64_GOT64: 5758 case BFD_RELOC_X86_64_GOTPCREL64: 5759 case BFD_RELOC_X86_64_GOTPC64: 5760 case BFD_RELOC_X86_64_GOTPLT64: 5761 case BFD_RELOC_X86_64_PLTOFF64: 5762 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 5763 case BFD_RELOC_X86_64_TLSDESC_CALL: 5764 case BFD_RELOC_RVA: 5765 case BFD_RELOC_VTABLE_ENTRY: 5766 case BFD_RELOC_VTABLE_INHERIT: 5767 #ifdef TE_PE 5768 case BFD_RELOC_32_SECREL: 5769 #endif 5770 code = fixp->fx_r_type; 5771 break; 5772 case BFD_RELOC_X86_64_32S: 5773 if (!fixp->fx_pcrel) 5774 { 5775 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ 5776 code = fixp->fx_r_type; 5777 break; 5778 } 5779 default: 5780 if (fixp->fx_pcrel) 5781 { 5782 switch (fixp->fx_size) 5783 { 5784 default: 5785 as_bad_where (fixp->fx_file, fixp->fx_line, 5786 _("can not do %d byte pc-relative relocation"), 5787 fixp->fx_size); 5788 code = BFD_RELOC_32_PCREL; 5789 break; 5790 case 1: code = BFD_RELOC_8_PCREL; break; 5791 case 2: code = BFD_RELOC_16_PCREL; break; 5792 case 4: code = BFD_RELOC_32_PCREL; break; 5793 #ifdef BFD64 5794 case 8: code = BFD_RELOC_64_PCREL; break; 5795 #endif 5796 } 5797 } 5798 else 5799 { 5800 switch (fixp->fx_size) 5801 { 5802 default: 5803 as_bad_where (fixp->fx_file, fixp->fx_line, 5804 _("can not do %d byte relocation"), 5805 fixp->fx_size); 5806 code = BFD_RELOC_32; 5807 break; 5808 case 1: code = BFD_RELOC_8; break; 5809 case 2: code = BFD_RELOC_16; break; 5810 case 4: code = BFD_RELOC_32; break; 5811 #ifdef BFD64 5812 case 8: code = BFD_RELOC_64; break; 5813 #endif 5814 } 5815 } 5816 break; 5817 } 5818 5819 if ((code == BFD_RELOC_32 5820 || code == BFD_RELOC_32_PCREL 5821 || code == BFD_RELOC_X86_64_32S) 5822 && GOT_symbol 5823 && fixp->fx_addsy == GOT_symbol) 5824 { 5825 if (!object_64bit) 5826 code = BFD_RELOC_386_GOTPC; 5827 else 5828 code = BFD_RELOC_X86_64_GOTPC32; 5829 } 5830 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) 5831 && GOT_symbol 5832 && fixp->fx_addsy == GOT_symbol) 5833 { 5834 code = BFD_RELOC_X86_64_GOTPC64; 5835 } 5836 5837 rel = (arelent *) xmalloc (sizeof (arelent)); 5838 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 5839 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 5840 5841 rel->address = fixp->fx_frag->fr_address + fixp->fx_where; 5842 5843 if (!use_rela_relocations) 5844 { 5845 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the 5846 vtable entry to be used in the relocation's section offset. */ 5847 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 5848 rel->address = fixp->fx_offset; 5849 5850 rel->addend = 0; 5851 } 5852 /* Use the rela in 64bit mode. */ 5853 else 5854 { 5855 if (!fixp->fx_pcrel) 5856 rel->addend = fixp->fx_offset; 5857 else 5858 switch (code) 5859 { 5860 case BFD_RELOC_X86_64_PLT32: 5861 case BFD_RELOC_X86_64_GOT32: 5862 case BFD_RELOC_X86_64_GOTPCREL: 5863 case BFD_RELOC_X86_64_TLSGD: 5864 case BFD_RELOC_X86_64_TLSLD: 5865 case BFD_RELOC_X86_64_GOTTPOFF: 5866 case BFD_RELOC_X86_64_GOTPC32_TLSDESC: 5867 case BFD_RELOC_X86_64_TLSDESC_CALL: 5868 rel->addend = fixp->fx_offset - fixp->fx_size; 5869 break; 5870 default: 5871 rel->addend = (section->vma 5872 - fixp->fx_size 5873 + fixp->fx_addnumber 5874 + md_pcrel_from (fixp)); 5875 break; 5876 } 5877 } 5878 5879 rel->howto = bfd_reloc_type_lookup (stdoutput, code); 5880 if (rel->howto == NULL) 5881 { 5882 as_bad_where (fixp->fx_file, fixp->fx_line, 5883 _("cannot represent relocation type %s"), 5884 bfd_get_reloc_code_name (code)); 5885 /* Set howto to a garbage value so that we can keep going. */ 5886 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); 5887 assert (rel->howto != NULL); 5888 } 5889 5890 return rel; 5891 } 5892 5893 5894 /* Parse operands using Intel syntax. This implements a recursive descent 5895 parser based on the BNF grammar published in Appendix B of the MASM 6.1 5896 Programmer's Guide. 5897 5898 FIXME: We do not recognize the full operand grammar defined in the MASM 5899 documentation. In particular, all the structure/union and 5900 high-level macro operands are missing. 5901 5902 Uppercase words are terminals, lower case words are non-terminals. 5903 Objects surrounded by double brackets '[[' ']]' are optional. Vertical 5904 bars '|' denote choices. Most grammar productions are implemented in 5905 functions called 'intel_<production>'. 5906 5907 Initial production is 'expr'. 5908 5909 addOp + | - 5910 5911 alpha [a-zA-Z] 5912 5913 binOp & | AND | \| | OR | ^ | XOR 5914 5915 byteRegister AL | AH | BL | BH | CL | CH | DL | DH 5916 5917 constant digits [[ radixOverride ]] 5918 5919 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD 5920 5921 digits decdigit 5922 | digits decdigit 5923 | digits hexdigit 5924 5925 decdigit [0-9] 5926 5927 e04 e04 addOp e05 5928 | e05 5929 5930 e05 e05 binOp e06 5931 | e06 5932 5933 e06 e06 mulOp e09 5934 | e09 5935 5936 e09 OFFSET e10 5937 | SHORT e10 5938 | + e10 5939 | - e10 5940 | ~ e10 5941 | NOT e10 5942 | e09 PTR e10 5943 | e09 : e10 5944 | e10 5945 5946 e10 e10 [ expr ] 5947 | e11 5948 5949 e11 ( expr ) 5950 | [ expr ] 5951 | constant 5952 | dataType 5953 | id 5954 | $ 5955 | register 5956 5957 => expr expr cmpOp e04 5958 | e04 5959 5960 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX 5961 | BP | EBP | SP | ESP | DI | EDI | SI | ESI 5962 5963 hexdigit a | b | c | d | e | f 5964 | A | B | C | D | E | F 5965 5966 id alpha 5967 | id alpha 5968 | id decdigit 5969 5970 mulOp * | / | % | MOD | << | SHL | >> | SHR 5971 5972 quote " | ' 5973 5974 register specialRegister 5975 | gpRegister 5976 | byteRegister 5977 5978 segmentRegister CS | DS | ES | FS | GS | SS 5979 5980 specialRegister CR0 | CR2 | CR3 | CR4 5981 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 5982 | TR3 | TR4 | TR5 | TR6 | TR7 5983 5984 We simplify the grammar in obvious places (e.g., register parsing is 5985 done by calling parse_register) and eliminate immediate left recursion 5986 to implement a recursive-descent parser. 5987 5988 expr e04 expr' 5989 5990 expr' cmpOp e04 expr' 5991 | Empty 5992 5993 e04 e05 e04' 5994 5995 e04' addOp e05 e04' 5996 | Empty 5997 5998 e05 e06 e05' 5999 6000 e05' binOp e06 e05' 6001 | Empty 6002 6003 e06 e09 e06' 6004 6005 e06' mulOp e09 e06' 6006 | Empty 6007 6008 e09 OFFSET e10 e09' 6009 | SHORT e10' 6010 | + e10' 6011 | - e10' 6012 | ~ e10' 6013 | NOT e10' 6014 | e10 e09' 6015 6016 e09' PTR e10 e09' 6017 | : e10 e09' 6018 | Empty 6019 6020 e10 e11 e10' 6021 6022 e10' [ expr ] e10' 6023 | Empty 6024 6025 e11 ( expr ) 6026 | [ expr ] 6027 | BYTE 6028 | WORD 6029 | DWORD 6030 | FWORD 6031 | QWORD 6032 | TBYTE 6033 | OWORD 6034 | XMMWORD 6035 | . 6036 | $ 6037 | register 6038 | id 6039 | constant */ 6040 6041 /* Parsing structure for the intel syntax parser. Used to implement the 6042 semantic actions for the operand grammar. */ 6043 struct intel_parser_s 6044 { 6045 char *op_string; /* The string being parsed. */ 6046 int got_a_float; /* Whether the operand is a float. */ 6047 int op_modifier; /* Operand modifier. */ 6048 int is_mem; /* 1 if operand is memory reference. */ 6049 int in_offset; /* >=1 if parsing operand of offset. */ 6050 int in_bracket; /* >=1 if parsing operand in brackets. */ 6051 const reg_entry *reg; /* Last register reference found. */ 6052 char *disp; /* Displacement string being built. */ 6053 char *next_operand; /* Resume point when splitting operands. */ 6054 }; 6055 6056 static struct intel_parser_s intel_parser; 6057 6058 /* Token structure for parsing intel syntax. */ 6059 struct intel_token 6060 { 6061 int code; /* Token code. */ 6062 const reg_entry *reg; /* Register entry for register tokens. */ 6063 char *str; /* String representation. */ 6064 }; 6065 6066 static struct intel_token cur_token, prev_token; 6067 6068 /* Token codes for the intel parser. Since T_SHORT is already used 6069 by COFF, undefine it first to prevent a warning. */ 6070 #define T_NIL -1 6071 #define T_CONST 1 6072 #define T_REG 2 6073 #define T_BYTE 3 6074 #define T_WORD 4 6075 #define T_DWORD 5 6076 #define T_FWORD 6 6077 #define T_QWORD 7 6078 #define T_TBYTE 8 6079 #define T_XMMWORD 9 6080 #undef T_SHORT 6081 #define T_SHORT 10 6082 #define T_OFFSET 11 6083 #define T_PTR 12 6084 #define T_ID 13 6085 #define T_SHL 14 6086 #define T_SHR 15 6087 6088 /* Prototypes for intel parser functions. */ 6089 static int intel_match_token PARAMS ((int code)); 6090 static void intel_get_token PARAMS ((void)); 6091 static void intel_putback_token PARAMS ((void)); 6092 static int intel_expr PARAMS ((void)); 6093 static int intel_e04 PARAMS ((void)); 6094 static int intel_e05 PARAMS ((void)); 6095 static int intel_e06 PARAMS ((void)); 6096 static int intel_e09 PARAMS ((void)); 6097 static int intel_bracket_expr PARAMS ((void)); 6098 static int intel_e10 PARAMS ((void)); 6099 static int intel_e11 PARAMS ((void)); 6100 6101 static int 6102 i386_intel_operand (operand_string, got_a_float) 6103 char *operand_string; 6104 int got_a_float; 6105 { 6106 int ret; 6107 char *p; 6108 6109 p = intel_parser.op_string = xstrdup (operand_string); 6110 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1); 6111 6112 for (;;) 6113 { 6114 /* Initialize token holders. */ 6115 cur_token.code = prev_token.code = T_NIL; 6116 cur_token.reg = prev_token.reg = NULL; 6117 cur_token.str = prev_token.str = NULL; 6118 6119 /* Initialize parser structure. */ 6120 intel_parser.got_a_float = got_a_float; 6121 intel_parser.op_modifier = 0; 6122 intel_parser.is_mem = 0; 6123 intel_parser.in_offset = 0; 6124 intel_parser.in_bracket = 0; 6125 intel_parser.reg = NULL; 6126 intel_parser.disp[0] = '\0'; 6127 intel_parser.next_operand = NULL; 6128 6129 /* Read the first token and start the parser. */ 6130 intel_get_token (); 6131 ret = intel_expr (); 6132 6133 if (!ret) 6134 break; 6135 6136 if (cur_token.code != T_NIL) 6137 { 6138 as_bad (_("invalid operand for '%s' ('%s' unexpected)"), 6139 current_templates->start->name, cur_token.str); 6140 ret = 0; 6141 } 6142 /* If we found a memory reference, hand it over to i386_displacement 6143 to fill in the rest of the operand fields. */ 6144 else if (intel_parser.is_mem) 6145 { 6146 if ((i.mem_operands == 1 6147 && (current_templates->start->opcode_modifier & IsString) == 0) 6148 || i.mem_operands == 2) 6149 { 6150 as_bad (_("too many memory references for '%s'"), 6151 current_templates->start->name); 6152 ret = 0; 6153 } 6154 else 6155 { 6156 char *s = intel_parser.disp; 6157 i.mem_operands++; 6158 6159 if (!quiet_warnings && intel_parser.is_mem < 0) 6160 /* See the comments in intel_bracket_expr. */ 6161 as_warn (_("Treating `%s' as memory reference"), operand_string); 6162 6163 /* Add the displacement expression. */ 6164 if (*s != '\0') 6165 ret = i386_displacement (s, s + strlen (s)); 6166 if (ret) 6167 { 6168 /* Swap base and index in 16-bit memory operands like 6169 [si+bx]. Since i386_index_check is also used in AT&T 6170 mode we have to do that here. */ 6171 if (i.base_reg 6172 && i.index_reg 6173 && (i.base_reg->reg_type & Reg16) 6174 && (i.index_reg->reg_type & Reg16) 6175 && i.base_reg->reg_num >= 6 6176 && i.index_reg->reg_num < 6) 6177 { 6178 const reg_entry *base = i.index_reg; 6179 6180 i.index_reg = i.base_reg; 6181 i.base_reg = base; 6182 } 6183 ret = i386_index_check (operand_string); 6184 } 6185 } 6186 } 6187 6188 /* Constant and OFFSET expressions are handled by i386_immediate. */ 6189 else if ((intel_parser.op_modifier & (1 << T_OFFSET)) 6190 || intel_parser.reg == NULL) 6191 ret = i386_immediate (intel_parser.disp); 6192 6193 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1) 6194 ret = 0; 6195 if (!ret || !intel_parser.next_operand) 6196 break; 6197 intel_parser.op_string = intel_parser.next_operand; 6198 this_operand = i.operands++; 6199 } 6200 6201 free (p); 6202 free (intel_parser.disp); 6203 6204 return ret; 6205 } 6206 6207 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg) 6208 6209 /* expr e04 expr' 6210 6211 expr' cmpOp e04 expr' 6212 | Empty */ 6213 static int 6214 intel_expr () 6215 { 6216 /* XXX Implement the comparison operators. */ 6217 return intel_e04 (); 6218 } 6219 6220 /* e04 e05 e04' 6221 6222 e04' addOp e05 e04' 6223 | Empty */ 6224 static int 6225 intel_e04 () 6226 { 6227 int nregs = -1; 6228 6229 for (;;) 6230 { 6231 if (!intel_e05()) 6232 return 0; 6233 6234 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) 6235 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */ 6236 6237 if (cur_token.code == '+') 6238 nregs = -1; 6239 else if (cur_token.code == '-') 6240 nregs = NUM_ADDRESS_REGS; 6241 else 6242 return 1; 6243 6244 strcat (intel_parser.disp, cur_token.str); 6245 intel_match_token (cur_token.code); 6246 } 6247 } 6248 6249 /* e05 e06 e05' 6250 6251 e05' binOp e06 e05' 6252 | Empty */ 6253 static int 6254 intel_e05 () 6255 { 6256 int nregs = ~NUM_ADDRESS_REGS; 6257 6258 for (;;) 6259 { 6260 if (!intel_e06()) 6261 return 0; 6262 6263 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^') 6264 { 6265 char str[2]; 6266 6267 str[0] = cur_token.code; 6268 str[1] = 0; 6269 strcat (intel_parser.disp, str); 6270 } 6271 else 6272 break; 6273 6274 intel_match_token (cur_token.code); 6275 6276 if (nregs < 0) 6277 nregs = ~nregs; 6278 } 6279 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) 6280 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */ 6281 return 1; 6282 } 6283 6284 /* e06 e09 e06' 6285 6286 e06' mulOp e09 e06' 6287 | Empty */ 6288 static int 6289 intel_e06 () 6290 { 6291 int nregs = ~NUM_ADDRESS_REGS; 6292 6293 for (;;) 6294 { 6295 if (!intel_e09()) 6296 return 0; 6297 6298 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%') 6299 { 6300 char str[2]; 6301 6302 str[0] = cur_token.code; 6303 str[1] = 0; 6304 strcat (intel_parser.disp, str); 6305 } 6306 else if (cur_token.code == T_SHL) 6307 strcat (intel_parser.disp, "<<"); 6308 else if (cur_token.code == T_SHR) 6309 strcat (intel_parser.disp, ">>"); 6310 else 6311 break; 6312 6313 intel_match_token (cur_token.code); 6314 6315 if (nregs < 0) 6316 nregs = ~nregs; 6317 } 6318 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) 6319 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */ 6320 return 1; 6321 } 6322 6323 /* e09 OFFSET e09 6324 | SHORT e09 6325 | + e09 6326 | - e09 6327 | ~ e09 6328 | NOT e09 6329 | e10 e09' 6330 6331 e09' PTR e10 e09' 6332 | : e10 e09' 6333 | Empty */ 6334 static int 6335 intel_e09 () 6336 { 6337 int nregs = ~NUM_ADDRESS_REGS; 6338 int in_offset = 0; 6339 6340 for (;;) 6341 { 6342 /* Don't consume constants here. */ 6343 if (cur_token.code == '+' || cur_token.code == '-') 6344 { 6345 /* Need to look one token ahead - if the next token 6346 is a constant, the current token is its sign. */ 6347 int next_code; 6348 6349 intel_match_token (cur_token.code); 6350 next_code = cur_token.code; 6351 intel_putback_token (); 6352 if (next_code == T_CONST) 6353 break; 6354 } 6355 6356 /* e09 OFFSET e09 */ 6357 if (cur_token.code == T_OFFSET) 6358 { 6359 if (!in_offset++) 6360 ++intel_parser.in_offset; 6361 } 6362 6363 /* e09 SHORT e09 */ 6364 else if (cur_token.code == T_SHORT) 6365 intel_parser.op_modifier |= 1 << T_SHORT; 6366 6367 /* e09 + e09 */ 6368 else if (cur_token.code == '+') 6369 strcat (intel_parser.disp, "+"); 6370 6371 /* e09 - e09 6372 | ~ e09 6373 | NOT e09 */ 6374 else if (cur_token.code == '-' || cur_token.code == '~') 6375 { 6376 char str[2]; 6377 6378 if (nregs < 0) 6379 nregs = ~nregs; 6380 str[0] = cur_token.code; 6381 str[1] = 0; 6382 strcat (intel_parser.disp, str); 6383 } 6384 6385 /* e09 e10 e09' */ 6386 else 6387 break; 6388 6389 intel_match_token (cur_token.code); 6390 } 6391 6392 for (;;) 6393 { 6394 if (!intel_e10 ()) 6395 return 0; 6396 6397 /* e09' PTR e10 e09' */ 6398 if (cur_token.code == T_PTR) 6399 { 6400 char suffix; 6401 6402 if (prev_token.code == T_BYTE) 6403 suffix = BYTE_MNEM_SUFFIX; 6404 6405 else if (prev_token.code == T_WORD) 6406 { 6407 if (current_templates->start->name[0] == 'l' 6408 && current_templates->start->name[2] == 's' 6409 && current_templates->start->name[3] == 0) 6410 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ 6411 else if (intel_parser.got_a_float == 2) /* "fi..." */ 6412 suffix = SHORT_MNEM_SUFFIX; 6413 else 6414 suffix = WORD_MNEM_SUFFIX; 6415 } 6416 6417 else if (prev_token.code == T_DWORD) 6418 { 6419 if (current_templates->start->name[0] == 'l' 6420 && current_templates->start->name[2] == 's' 6421 && current_templates->start->name[3] == 0) 6422 suffix = WORD_MNEM_SUFFIX; 6423 else if (flag_code == CODE_16BIT 6424 && (current_templates->start->opcode_modifier 6425 & (Jump | JumpDword))) 6426 suffix = LONG_DOUBLE_MNEM_SUFFIX; 6427 else if (intel_parser.got_a_float == 1) /* "f..." */ 6428 suffix = SHORT_MNEM_SUFFIX; 6429 else 6430 suffix = LONG_MNEM_SUFFIX; 6431 } 6432 6433 else if (prev_token.code == T_FWORD) 6434 { 6435 if (current_templates->start->name[0] == 'l' 6436 && current_templates->start->name[2] == 's' 6437 && current_templates->start->name[3] == 0) 6438 suffix = LONG_MNEM_SUFFIX; 6439 else if (!intel_parser.got_a_float) 6440 { 6441 if (flag_code == CODE_16BIT) 6442 add_prefix (DATA_PREFIX_OPCODE); 6443 suffix = LONG_DOUBLE_MNEM_SUFFIX; 6444 } 6445 else 6446 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ 6447 } 6448 6449 else if (prev_token.code == T_QWORD) 6450 { 6451 if (intel_parser.got_a_float == 1) /* "f..." */ 6452 suffix = LONG_MNEM_SUFFIX; 6453 else 6454 suffix = QWORD_MNEM_SUFFIX; 6455 } 6456 6457 else if (prev_token.code == T_TBYTE) 6458 { 6459 if (intel_parser.got_a_float == 1) 6460 suffix = LONG_DOUBLE_MNEM_SUFFIX; 6461 else 6462 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ 6463 } 6464 6465 else if (prev_token.code == T_XMMWORD) 6466 { 6467 /* XXX ignored for now, but accepted since gcc uses it */ 6468 suffix = 0; 6469 } 6470 6471 else 6472 { 6473 as_bad (_("Unknown operand modifier `%s'"), prev_token.str); 6474 return 0; 6475 } 6476 6477 /* Operands for jump/call using 'ptr' notation denote absolute 6478 addresses. */ 6479 if (current_templates->start->opcode_modifier & (Jump | JumpDword)) 6480 i.types[this_operand] |= JumpAbsolute; 6481 6482 if (current_templates->start->base_opcode == 0x8d /* lea */) 6483 ; 6484 else if (!i.suffix) 6485 i.suffix = suffix; 6486 else if (i.suffix != suffix) 6487 { 6488 as_bad (_("Conflicting operand modifiers")); 6489 return 0; 6490 } 6491 6492 } 6493 6494 /* e09' : e10 e09' */ 6495 else if (cur_token.code == ':') 6496 { 6497 if (prev_token.code != T_REG) 6498 { 6499 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a 6500 segment/group identifier (which we don't have), using comma 6501 as the operand separator there is even less consistent, since 6502 there all branches only have a single operand. */ 6503 if (this_operand != 0 6504 || intel_parser.in_offset 6505 || intel_parser.in_bracket 6506 || (!(current_templates->start->opcode_modifier 6507 & (Jump|JumpDword|JumpInterSegment)) 6508 && !(current_templates->start->operand_types[0] 6509 & JumpAbsolute))) 6510 return intel_match_token (T_NIL); 6511 /* Remember the start of the 2nd operand and terminate 1st 6512 operand here. 6513 XXX This isn't right, yet (when SSSS:OOOO is right operand of 6514 another expression), but it gets at least the simplest case 6515 (a plain number or symbol on the left side) right. */ 6516 intel_parser.next_operand = intel_parser.op_string; 6517 *--intel_parser.op_string = '\0'; 6518 return intel_match_token (':'); 6519 } 6520 } 6521 6522 /* e09' Empty */ 6523 else 6524 break; 6525 6526 intel_match_token (cur_token.code); 6527 6528 } 6529 6530 if (in_offset) 6531 { 6532 --intel_parser.in_offset; 6533 if (nregs < 0) 6534 nregs = ~nregs; 6535 if (NUM_ADDRESS_REGS > nregs) 6536 { 6537 as_bad (_("Invalid operand to `OFFSET'")); 6538 return 0; 6539 } 6540 intel_parser.op_modifier |= 1 << T_OFFSET; 6541 } 6542 6543 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) 6544 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */ 6545 return 1; 6546 } 6547 6548 static int 6549 intel_bracket_expr () 6550 { 6551 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET); 6552 const char *start = intel_parser.op_string; 6553 int len; 6554 6555 if (i.op[this_operand].regs) 6556 return intel_match_token (T_NIL); 6557 6558 intel_match_token ('['); 6559 6560 /* Mark as a memory operand only if it's not already known to be an 6561 offset expression. If it's an offset expression, we need to keep 6562 the brace in. */ 6563 if (!intel_parser.in_offset) 6564 { 6565 ++intel_parser.in_bracket; 6566 6567 /* Operands for jump/call inside brackets denote absolute addresses. */ 6568 if (current_templates->start->opcode_modifier & (Jump | JumpDword)) 6569 i.types[this_operand] |= JumpAbsolute; 6570 6571 /* Unfortunately gas always diverged from MASM in a respect that can't 6572 be easily fixed without risking to break code sequences likely to be 6573 encountered (the testsuite even check for this): MASM doesn't consider 6574 an expression inside brackets unconditionally as a memory reference. 6575 When that is e.g. a constant, an offset expression, or the sum of the 6576 two, this is still taken as a constant load. gas, however, always 6577 treated these as memory references. As a compromise, we'll try to make 6578 offset expressions inside brackets work the MASM way (since that's 6579 less likely to be found in real world code), but make constants alone 6580 continue to work the traditional gas way. In either case, issue a 6581 warning. */ 6582 intel_parser.op_modifier &= ~was_offset; 6583 } 6584 else 6585 strcat (intel_parser.disp, "["); 6586 6587 /* Add a '+' to the displacement string if necessary. */ 6588 if (*intel_parser.disp != '\0' 6589 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') 6590 strcat (intel_parser.disp, "+"); 6591 6592 if (intel_expr () 6593 && (len = intel_parser.op_string - start - 1, 6594 intel_match_token (']'))) 6595 { 6596 /* Preserve brackets when the operand is an offset expression. */ 6597 if (intel_parser.in_offset) 6598 strcat (intel_parser.disp, "]"); 6599 else 6600 { 6601 --intel_parser.in_bracket; 6602 if (i.base_reg || i.index_reg) 6603 intel_parser.is_mem = 1; 6604 if (!intel_parser.is_mem) 6605 { 6606 if (!(intel_parser.op_modifier & (1 << T_OFFSET))) 6607 /* Defer the warning until all of the operand was parsed. */ 6608 intel_parser.is_mem = -1; 6609 else if (!quiet_warnings) 6610 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start); 6611 } 6612 } 6613 intel_parser.op_modifier |= was_offset; 6614 6615 return 1; 6616 } 6617 return 0; 6618 } 6619 6620 /* e10 e11 e10' 6621 6622 e10' [ expr ] e10' 6623 | Empty */ 6624 static int 6625 intel_e10 () 6626 { 6627 if (!intel_e11 ()) 6628 return 0; 6629 6630 while (cur_token.code == '[') 6631 { 6632 if (!intel_bracket_expr ()) 6633 return 0; 6634 } 6635 6636 return 1; 6637 } 6638 6639 /* e11 ( expr ) 6640 | [ expr ] 6641 | BYTE 6642 | WORD 6643 | DWORD 6644 | FWORD 6645 | QWORD 6646 | TBYTE 6647 | OWORD 6648 | XMMWORD 6649 | $ 6650 | . 6651 | register 6652 | id 6653 | constant */ 6654 static int 6655 intel_e11 () 6656 { 6657 switch (cur_token.code) 6658 { 6659 /* e11 ( expr ) */ 6660 case '(': 6661 intel_match_token ('('); 6662 strcat (intel_parser.disp, "("); 6663 6664 if (intel_expr () && intel_match_token (')')) 6665 { 6666 strcat (intel_parser.disp, ")"); 6667 return 1; 6668 } 6669 return 0; 6670 6671 /* e11 [ expr ] */ 6672 case '[': 6673 return intel_bracket_expr (); 6674 6675 /* e11 $ 6676 | . */ 6677 case '.': 6678 strcat (intel_parser.disp, cur_token.str); 6679 intel_match_token (cur_token.code); 6680 6681 /* Mark as a memory operand only if it's not already known to be an 6682 offset expression. */ 6683 if (!intel_parser.in_offset) 6684 intel_parser.is_mem = 1; 6685 6686 return 1; 6687 6688 /* e11 register */ 6689 case T_REG: 6690 { 6691 const reg_entry *reg = intel_parser.reg = cur_token.reg; 6692 6693 intel_match_token (T_REG); 6694 6695 /* Check for segment change. */ 6696 if (cur_token.code == ':') 6697 { 6698 if (!(reg->reg_type & (SReg2 | SReg3))) 6699 { 6700 as_bad (_("`%s' is not a valid segment register"), reg->reg_name); 6701 return 0; 6702 } 6703 else if (i.seg[i.mem_operands]) 6704 as_warn (_("Extra segment override ignored")); 6705 else 6706 { 6707 if (!intel_parser.in_offset) 6708 intel_parser.is_mem = 1; 6709 switch (reg->reg_num) 6710 { 6711 case 0: 6712 i.seg[i.mem_operands] = &es; 6713 break; 6714 case 1: 6715 i.seg[i.mem_operands] = &cs; 6716 break; 6717 case 2: 6718 i.seg[i.mem_operands] = &ss; 6719 break; 6720 case 3: 6721 i.seg[i.mem_operands] = &ds; 6722 break; 6723 case 4: 6724 i.seg[i.mem_operands] = &fs; 6725 break; 6726 case 5: 6727 i.seg[i.mem_operands] = &gs; 6728 break; 6729 } 6730 } 6731 } 6732 6733 /* Not a segment register. Check for register scaling. */ 6734 else if (cur_token.code == '*') 6735 { 6736 if (!intel_parser.in_bracket) 6737 { 6738 as_bad (_("Register scaling only allowed in memory operands")); 6739 return 0; 6740 } 6741 6742 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */ 6743 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */ 6744 else if (i.index_reg) 6745 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */ 6746 6747 /* What follows must be a valid scale. */ 6748 intel_match_token ('*'); 6749 i.index_reg = reg; 6750 i.types[this_operand] |= BaseIndex; 6751 6752 /* Set the scale after setting the register (otherwise, 6753 i386_scale will complain) */ 6754 if (cur_token.code == '+' || cur_token.code == '-') 6755 { 6756 char *str, sign = cur_token.code; 6757 intel_match_token (cur_token.code); 6758 if (cur_token.code != T_CONST) 6759 { 6760 as_bad (_("Syntax error: Expecting a constant, got `%s'"), 6761 cur_token.str); 6762 return 0; 6763 } 6764 str = (char *) xmalloc (strlen (cur_token.str) + 2); 6765 strcpy (str + 1, cur_token.str); 6766 *str = sign; 6767 if (!i386_scale (str)) 6768 return 0; 6769 free (str); 6770 } 6771 else if (!i386_scale (cur_token.str)) 6772 return 0; 6773 intel_match_token (cur_token.code); 6774 } 6775 6776 /* No scaling. If this is a memory operand, the register is either a 6777 base register (first occurrence) or an index register (second 6778 occurrence). */ 6779 else if (intel_parser.in_bracket) 6780 { 6781 6782 if (!i.base_reg) 6783 i.base_reg = reg; 6784 else if (!i.index_reg) 6785 i.index_reg = reg; 6786 else 6787 { 6788 as_bad (_("Too many register references in memory operand")); 6789 return 0; 6790 } 6791 6792 i.types[this_operand] |= BaseIndex; 6793 } 6794 6795 /* It's neither base nor index. */ 6796 else if (!intel_parser.in_offset && !intel_parser.is_mem) 6797 { 6798 i.types[this_operand] |= reg->reg_type & ~BaseIndex; 6799 i.op[this_operand].regs = reg; 6800 i.reg_operands++; 6801 } 6802 else 6803 { 6804 as_bad (_("Invalid use of register")); 6805 return 0; 6806 } 6807 6808 /* Since registers are not part of the displacement string (except 6809 when we're parsing offset operands), we may need to remove any 6810 preceding '+' from the displacement string. */ 6811 if (*intel_parser.disp != '\0' 6812 && !intel_parser.in_offset) 6813 { 6814 char *s = intel_parser.disp; 6815 s += strlen (s) - 1; 6816 if (*s == '+') 6817 *s = '\0'; 6818 } 6819 6820 return 1; 6821 } 6822 6823 /* e11 BYTE 6824 | WORD 6825 | DWORD 6826 | FWORD 6827 | QWORD 6828 | TBYTE 6829 | OWORD 6830 | XMMWORD */ 6831 case T_BYTE: 6832 case T_WORD: 6833 case T_DWORD: 6834 case T_FWORD: 6835 case T_QWORD: 6836 case T_TBYTE: 6837 case T_XMMWORD: 6838 intel_match_token (cur_token.code); 6839 6840 if (cur_token.code == T_PTR) 6841 return 1; 6842 6843 /* It must have been an identifier. */ 6844 intel_putback_token (); 6845 cur_token.code = T_ID; 6846 /* FALLTHRU */ 6847 6848 /* e11 id 6849 | constant */ 6850 case T_ID: 6851 if (!intel_parser.in_offset && intel_parser.is_mem <= 0) 6852 { 6853 symbolS *symbolP; 6854 6855 /* The identifier represents a memory reference only if it's not 6856 preceded by an offset modifier and if it's not an equate. */ 6857 symbolP = symbol_find(cur_token.str); 6858 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section) 6859 intel_parser.is_mem = 1; 6860 } 6861 /* FALLTHRU */ 6862 6863 case T_CONST: 6864 case '-': 6865 case '+': 6866 { 6867 char *save_str, sign = 0; 6868 6869 /* Allow constants that start with `+' or `-'. */ 6870 if (cur_token.code == '-' || cur_token.code == '+') 6871 { 6872 sign = cur_token.code; 6873 intel_match_token (cur_token.code); 6874 if (cur_token.code != T_CONST) 6875 { 6876 as_bad (_("Syntax error: Expecting a constant, got `%s'"), 6877 cur_token.str); 6878 return 0; 6879 } 6880 } 6881 6882 save_str = (char *) xmalloc (strlen (cur_token.str) + 2); 6883 strcpy (save_str + !!sign, cur_token.str); 6884 if (sign) 6885 *save_str = sign; 6886 6887 /* Get the next token to check for register scaling. */ 6888 intel_match_token (cur_token.code); 6889 6890 /* Check if this constant is a scaling factor for an index register. */ 6891 if (cur_token.code == '*') 6892 { 6893 if (intel_match_token ('*') && cur_token.code == T_REG) 6894 { 6895 const reg_entry *reg = cur_token.reg; 6896 6897 if (!intel_parser.in_bracket) 6898 { 6899 as_bad (_("Register scaling only allowed in memory operands")); 6900 return 0; 6901 } 6902 6903 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */ 6904 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */ 6905 else if (i.index_reg) 6906 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */ 6907 6908 /* The constant is followed by `* reg', so it must be 6909 a valid scale. */ 6910 i.index_reg = reg; 6911 i.types[this_operand] |= BaseIndex; 6912 6913 /* Set the scale after setting the register (otherwise, 6914 i386_scale will complain) */ 6915 if (!i386_scale (save_str)) 6916 return 0; 6917 intel_match_token (T_REG); 6918 6919 /* Since registers are not part of the displacement 6920 string, we may need to remove any preceding '+' from 6921 the displacement string. */ 6922 if (*intel_parser.disp != '\0') 6923 { 6924 char *s = intel_parser.disp; 6925 s += strlen (s) - 1; 6926 if (*s == '+') 6927 *s = '\0'; 6928 } 6929 6930 free (save_str); 6931 6932 return 1; 6933 } 6934 6935 /* The constant was not used for register scaling. Since we have 6936 already consumed the token following `*' we now need to put it 6937 back in the stream. */ 6938 intel_putback_token (); 6939 } 6940 6941 /* Add the constant to the displacement string. */ 6942 strcat (intel_parser.disp, save_str); 6943 free (save_str); 6944 6945 return 1; 6946 } 6947 } 6948 6949 as_bad (_("Unrecognized token '%s'"), cur_token.str); 6950 return 0; 6951 } 6952 6953 /* Match the given token against cur_token. If they match, read the next 6954 token from the operand string. */ 6955 static int 6956 intel_match_token (code) 6957 int code; 6958 { 6959 if (cur_token.code == code) 6960 { 6961 intel_get_token (); 6962 return 1; 6963 } 6964 else 6965 { 6966 as_bad (_("Unexpected token `%s'"), cur_token.str); 6967 return 0; 6968 } 6969 } 6970 6971 /* Read a new token from intel_parser.op_string and store it in cur_token. */ 6972 static void 6973 intel_get_token () 6974 { 6975 char *end_op; 6976 const reg_entry *reg; 6977 struct intel_token new_token; 6978 6979 new_token.code = T_NIL; 6980 new_token.reg = NULL; 6981 new_token.str = NULL; 6982 6983 /* Free the memory allocated to the previous token and move 6984 cur_token to prev_token. */ 6985 if (prev_token.str) 6986 free (prev_token.str); 6987 6988 prev_token = cur_token; 6989 6990 /* Skip whitespace. */ 6991 while (is_space_char (*intel_parser.op_string)) 6992 intel_parser.op_string++; 6993 6994 /* Return an empty token if we find nothing else on the line. */ 6995 if (*intel_parser.op_string == '\0') 6996 { 6997 cur_token = new_token; 6998 return; 6999 } 7000 7001 /* The new token cannot be larger than the remainder of the operand 7002 string. */ 7003 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1); 7004 new_token.str[0] = '\0'; 7005 7006 if (strchr ("0123456789", *intel_parser.op_string)) 7007 { 7008 char *p = new_token.str; 7009 char *q = intel_parser.op_string; 7010 new_token.code = T_CONST; 7011 7012 /* Allow any kind of identifier char to encompass floating point and 7013 hexadecimal numbers. */ 7014 while (is_identifier_char (*q)) 7015 *p++ = *q++; 7016 *p = '\0'; 7017 7018 /* Recognize special symbol names [0-9][bf]. */ 7019 if (strlen (intel_parser.op_string) == 2 7020 && (intel_parser.op_string[1] == 'b' 7021 || intel_parser.op_string[1] == 'f')) 7022 new_token.code = T_ID; 7023 } 7024 7025 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL) 7026 { 7027 size_t len = end_op - intel_parser.op_string; 7028 7029 new_token.code = T_REG; 7030 new_token.reg = reg; 7031 7032 memcpy (new_token.str, intel_parser.op_string, len); 7033 new_token.str[len] = '\0'; 7034 } 7035 7036 else if (is_identifier_char (*intel_parser.op_string)) 7037 { 7038 char *p = new_token.str; 7039 char *q = intel_parser.op_string; 7040 7041 /* A '.' or '$' followed by an identifier char is an identifier. 7042 Otherwise, it's operator '.' followed by an expression. */ 7043 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) 7044 { 7045 new_token.code = '.'; 7046 new_token.str[0] = '.'; 7047 new_token.str[1] = '\0'; 7048 } 7049 else 7050 { 7051 while (is_identifier_char (*q) || *q == '@') 7052 *p++ = *q++; 7053 *p = '\0'; 7054 7055 if (strcasecmp (new_token.str, "NOT") == 0) 7056 new_token.code = '~'; 7057 7058 else if (strcasecmp (new_token.str, "MOD") == 0) 7059 new_token.code = '%'; 7060 7061 else if (strcasecmp (new_token.str, "AND") == 0) 7062 new_token.code = '&'; 7063 7064 else if (strcasecmp (new_token.str, "OR") == 0) 7065 new_token.code = '|'; 7066 7067 else if (strcasecmp (new_token.str, "XOR") == 0) 7068 new_token.code = '^'; 7069 7070 else if (strcasecmp (new_token.str, "SHL") == 0) 7071 new_token.code = T_SHL; 7072 7073 else if (strcasecmp (new_token.str, "SHR") == 0) 7074 new_token.code = T_SHR; 7075 7076 else if (strcasecmp (new_token.str, "BYTE") == 0) 7077 new_token.code = T_BYTE; 7078 7079 else if (strcasecmp (new_token.str, "WORD") == 0) 7080 new_token.code = T_WORD; 7081 7082 else if (strcasecmp (new_token.str, "DWORD") == 0) 7083 new_token.code = T_DWORD; 7084 7085 else if (strcasecmp (new_token.str, "FWORD") == 0) 7086 new_token.code = T_FWORD; 7087 7088 else if (strcasecmp (new_token.str, "QWORD") == 0) 7089 new_token.code = T_QWORD; 7090 7091 else if (strcasecmp (new_token.str, "TBYTE") == 0 7092 /* XXX remove (gcc still uses it) */ 7093 || strcasecmp (new_token.str, "XWORD") == 0) 7094 new_token.code = T_TBYTE; 7095 7096 else if (strcasecmp (new_token.str, "XMMWORD") == 0 7097 || strcasecmp (new_token.str, "OWORD") == 0) 7098 new_token.code = T_XMMWORD; 7099 7100 else if (strcasecmp (new_token.str, "PTR") == 0) 7101 new_token.code = T_PTR; 7102 7103 else if (strcasecmp (new_token.str, "SHORT") == 0) 7104 new_token.code = T_SHORT; 7105 7106 else if (strcasecmp (new_token.str, "OFFSET") == 0) 7107 { 7108 new_token.code = T_OFFSET; 7109 7110 /* ??? This is not mentioned in the MASM grammar but gcc 7111 makes use of it with -mintel-syntax. OFFSET may be 7112 followed by FLAT: */ 7113 if (strncasecmp (q, " FLAT:", 6) == 0) 7114 strcat (new_token.str, " FLAT:"); 7115 } 7116 7117 /* ??? This is not mentioned in the MASM grammar. */ 7118 else if (strcasecmp (new_token.str, "FLAT") == 0) 7119 { 7120 new_token.code = T_OFFSET; 7121 if (*q == ':') 7122 strcat (new_token.str, ":"); 7123 else 7124 as_bad (_("`:' expected")); 7125 } 7126 7127 else 7128 new_token.code = T_ID; 7129 } 7130 } 7131 7132 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string)) 7133 { 7134 new_token.code = *intel_parser.op_string; 7135 new_token.str[0] = *intel_parser.op_string; 7136 new_token.str[1] = '\0'; 7137 } 7138 7139 else if (strchr ("<>", *intel_parser.op_string) 7140 && *intel_parser.op_string == *(intel_parser.op_string + 1)) 7141 { 7142 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR; 7143 new_token.str[0] = *intel_parser.op_string; 7144 new_token.str[1] = *intel_parser.op_string; 7145 new_token.str[2] = '\0'; 7146 } 7147 7148 else 7149 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string); 7150 7151 intel_parser.op_string += strlen (new_token.str); 7152 cur_token = new_token; 7153 } 7154 7155 /* Put cur_token back into the token stream and make cur_token point to 7156 prev_token. */ 7157 static void 7158 intel_putback_token () 7159 { 7160 if (cur_token.code != T_NIL) 7161 { 7162 intel_parser.op_string -= strlen (cur_token.str); 7163 free (cur_token.str); 7164 } 7165 cur_token = prev_token; 7166 7167 /* Forget prev_token. */ 7168 prev_token.code = T_NIL; 7169 prev_token.reg = NULL; 7170 prev_token.str = NULL; 7171 } 7172 7173 int 7174 tc_x86_regname_to_dw2regnum (const char *regname) 7175 { 7176 unsigned int regnum; 7177 unsigned int regnames_count; 7178 static const char *const regnames_32[] = 7179 { 7180 "eax", "ecx", "edx", "ebx", 7181 "esp", "ebp", "esi", "edi", 7182 "eip", "eflags", NULL, 7183 "st0", "st1", "st2", "st3", 7184 "st4", "st5", "st6", "st7", 7185 NULL, NULL, 7186 "xmm0", "xmm1", "xmm2", "xmm3", 7187 "xmm4", "xmm5", "xmm6", "xmm7", 7188 "mm0", "mm1", "mm2", "mm3", 7189 "mm4", "mm5", "mm6", "mm7", 7190 "fcw", "fsw", "mxcsr", 7191 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, 7192 "tr", "ldtr" 7193 }; 7194 static const char *const regnames_64[] = 7195 { 7196 "rax", "rdx", "rcx", "rbx", 7197 "rsi", "rdi", "rbp", "rsp", 7198 "r8", "r9", "r10", "r11", 7199 "r12", "r13", "r14", "r15", 7200 "rip", 7201 "xmm0", "xmm1", "xmm2", "xmm3", 7202 "xmm4", "xmm5", "xmm6", "xmm7", 7203 "xmm8", "xmm9", "xmm10", "xmm11", 7204 "xmm12", "xmm13", "xmm14", "xmm15", 7205 "st0", "st1", "st2", "st3", 7206 "st4", "st5", "st6", "st7", 7207 "mm0", "mm1", "mm2", "mm3", 7208 "mm4", "mm5", "mm6", "mm7", 7209 "rflags", 7210 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, 7211 "fs.base", "gs.base", NULL, NULL, 7212 "tr", "ldtr", 7213 "mxcsr", "fcw", "fsw" 7214 }; 7215 const char *const *regnames; 7216 7217 if (flag_code == CODE_64BIT) 7218 { 7219 regnames = regnames_64; 7220 regnames_count = ARRAY_SIZE (regnames_64); 7221 } 7222 else 7223 { 7224 regnames = regnames_32; 7225 regnames_count = ARRAY_SIZE (regnames_32); 7226 } 7227 7228 for (regnum = 0; regnum < regnames_count; regnum++) 7229 if (regnames[regnum] != NULL 7230 && strcmp (regname, regnames[regnum]) == 0) 7231 return regnum; 7232 7233 return -1; 7234 } 7235 7236 void 7237 tc_x86_frame_initial_instructions (void) 7238 { 7239 static unsigned int sp_regno; 7240 7241 if (!sp_regno) 7242 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT 7243 ? "rsp" : "esp"); 7244 7245 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment); 7246 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); 7247 } 7248 7249 int 7250 i386_elf_section_type (const char *str, size_t len) 7251 { 7252 if (flag_code == CODE_64BIT 7253 && len == sizeof ("unwind") - 1 7254 && strncmp (str, "unwind", 6) == 0) 7255 return SHT_X86_64_UNWIND; 7256 7257 return -1; 7258 } 7259 7260 #ifdef TE_PE 7261 void 7262 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) 7263 { 7264 expressionS expr; 7265 7266 expr.X_op = O_secrel; 7267 expr.X_add_symbol = symbol; 7268 expr.X_add_number = 0; 7269 emit_expr (&expr, size); 7270 } 7271 #endif 7272 7273 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 7274 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ 7275 7276 int 7277 x86_64_section_letter (int letter, char **ptr_msg) 7278 { 7279 if (flag_code == CODE_64BIT) 7280 { 7281 if (letter == 'l') 7282 return SHF_X86_64_LARGE; 7283 7284 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string"); 7285 } 7286 else 7287 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string"); 7288 return -1; 7289 } 7290 7291 int 7292 x86_64_section_word (char *str, size_t len) 7293 { 7294 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0) 7295 return SHF_X86_64_LARGE; 7296 7297 return -1; 7298 } 7299 7300 static void 7301 handle_large_common (int small ATTRIBUTE_UNUSED) 7302 { 7303 if (flag_code != CODE_64BIT) 7304 { 7305 s_comm_internal (0, elf_common_parse); 7306 as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); 7307 } 7308 else 7309 { 7310 static segT lbss_section; 7311 asection *saved_com_section_ptr = elf_com_section_ptr; 7312 asection *saved_bss_section = bss_section; 7313 7314 if (lbss_section == NULL) 7315 { 7316 flagword applicable; 7317 segT seg = now_seg; 7318 subsegT subseg = now_subseg; 7319 7320 /* The .lbss section is for local .largecomm symbols. */ 7321 lbss_section = subseg_new (".lbss", 0); 7322 applicable = bfd_applicable_section_flags (stdoutput); 7323 bfd_set_section_flags (stdoutput, lbss_section, 7324 applicable & SEC_ALLOC); 7325 seg_info (lbss_section)->bss = 1; 7326 7327 subseg_set (seg, subseg); 7328 } 7329 7330 elf_com_section_ptr = &_bfd_elf_large_com_section; 7331 bss_section = lbss_section; 7332 7333 s_comm_internal (0, elf_common_parse); 7334 7335 elf_com_section_ptr = saved_com_section_ptr; 7336 bss_section = saved_bss_section; 7337 } 7338 } 7339 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ 7340