1@c Copyright (C) 1997 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4@ifset GENERIC 5@page 6@node D30V-Dependent 7@chapter D30V Dependent Features 8@end ifset 9@ifclear GENERIC 10@node Machine Dependencies 11@chapter D30V Dependent Features 12@end ifclear 13 14@cindex D30V support 15@menu 16* D30V-Opts:: D30V Options 17* D30V-Syntax:: Syntax 18* D30V-Float:: Floating Point 19* D30V-Opcodes:: Opcodes 20@end menu 21 22@node D30V-Opts 23@section D30V Options 24@cindex options, D30V 25@cindex D30V options 26The Mitsubishi D30V version of @code{@value{AS}} has a few machine 27dependent options. 28 29@table @samp 30@item -O 31The D30V can often execute two sub-instructions in parallel. When this option 32is used, @code{@value{AS}} will attempt to optimize its output by detecting when 33instructions can be executed in parallel. 34 35@item -n 36When this option is used, @code{@value{AS}} will issue a warning every 37time it adds a nop instruction. 38 39@item -N 40When this option is used, @code{@value{AS}} will issue a warning if it 41needs to insert a nop after a 32-bit multiply before a load or 16-bit 42multiply instruction. 43@end table 44 45@node D30V-Syntax 46@section Syntax 47@cindex D30V syntax 48@cindex syntax, D30V 49 50The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual. 51The differences are detailed below. 52 53@menu 54* D30V-Size:: Size Modifiers 55* D30V-Subs:: Sub-Instructions 56* D30V-Chars:: Special Characters 57* D30V-Guarded:: Guarded Execution 58* D30V-Regs:: Register Names 59* D30V-Addressing:: Addressing Modes 60@end menu 61 62 63@node D30V-Size 64@subsection Size Modifiers 65@cindex D30V size modifiers 66@cindex size modifiers, D30V 67The D30V version of @code{@value{AS}} uses the instruction names in the D30V 68Architecture Manual. However, the names in the manual are sometimes ambiguous. 69There are instruction names that can assemble to a short or long form opcode. 70How does the assembler pick the correct form? @code{@value{AS}} will always pick the 71smallest form if it can. When dealing with a symbol that is not defined yet when a 72line is being assembled, it will always use the long form. If you need to force the 73assembler to use either the short or long form of the instruction, you can append 74either @samp{.s} (short) or @samp{.l} (long) to it. For example, if you are writing 75an assembly program and you want to do a branch to a symbol that is defined later 76in your program, you can write @samp{bra.s foo}. 77Objdump and GDB will always append @samp{.s} or @samp{.l} to instructions which 78have both short and long forms. 79 80@node D30V-Subs 81@subsection Sub-Instructions 82@cindex D30V sub-instructions 83@cindex sub-instructions, D30V 84The D30V assembler takes as input a series of instructions, either one-per-line, 85or in the special two-per-line format described in the next section. Some of these 86instructions will be short-form or sub-instructions. These sub-instructions can be packed 87into a single instruction. The assembler will do this automatically. It will also detect 88when it should not pack instructions. For example, when a label is defined, the next 89instruction will never be packaged with the previous one. Whenever a branch and link 90instruction is called, it will not be packaged with the next instruction so the return 91address will be valid. Nops are automatically inserted when necessary. 92 93If you do not want the assembler automatically making these decisions, you can control 94the packaging and execution type (parallel or sequential) with the special execution 95symbols described in the next section. 96 97@node D30V-Chars 98@subsection Special Characters 99@cindex line comment character, D30V 100@cindex D30V line comment character 101@samp{;} and @samp{#} are the line comment characters. 102@cindex sub-instruction ordering, D30V 103@cindex D30V sub-instruction ordering 104Sub-instructions may be executed in order, in reverse-order, or in parallel. 105Instructions listed in the standard one-per-line format will be executed 106sequentially unless you use the @samp{-O} option. 107 108To specify the executing order, use the following symbols: 109@table @samp 110@item -> 111Sequential with instruction on the left first. 112 113@item <- 114Sequential with instruction on the right first. 115 116@item || 117Parallel 118@end table 119 120The D30V syntax allows either one instruction per line, one instruction per line with 121the execution symbol, or two instructions per line. For example 122@table @code 123@item abs r2,r3 -> abs r4,r5 124Execute these sequentially. The instruction on the right is in the right 125container and is executed second. 126 127@item abs r2,r3 <- abs r4,r5 128Execute these reverse-sequentially. The instruction on the right is in the right 129container, and is executed first. 130 131@item abs r2,r3 || abs r4,r5 132Execute these in parallel. 133 134@item ldw r2,@@(r3,r4) || 135@itemx mulx r6,r8,r9 136Two-line format. Execute these in parallel. 137 138@item mulx a0,r8,r9 139@itemx stw r2,@@(r3,r4) 140Two-line format. Execute these sequentially unless @samp{-O} option is 141used. If the @samp{-O} option is used, the assembler will determine if 142the instructions could be done in parallel (the above two instructions 143can be done in parallel), and if so, emit them as parallel instructions. 144The assembler will put them in the proper containers. In the above 145example, the assembler will put the @samp{stw} instruction in left 146container and the @samp{mulx} instruction in the right container. 147 148@item stw r2,@@(r3,r4) -> 149@itemx mulx a0,r8,r9 150Two-line format. Execute the @samp{stw} instruction followed by the 151@samp{mulx} instruction sequentially. The first instruction goes in the 152left container and the second instruction goes into right container. 153The assembler will give an error if the machine ordering constraints are 154violated. 155 156@item stw r2,@@(r3,r4) <- 157@itemx mulx a0,r8,r9 158Same as previous example, except that the @samp{mulx} instruction is 159executed before the @samp{stw} instruction. 160@end table 161 162@cindex symbol names, @samp{$} in 163@cindex @code{$} in symbol names 164Since @samp{$} has no special meaning, you may use it in symbol names. 165 166@node D30V-Guarded 167@subsection Guarded Execution 168@cindex D30V Guarded Execution 169@code{@value{AS}} supports the full range of guarded execution 170directives for each instruction. Just append the directive after the 171instruction proper. The directives are: 172 173@table @samp 174@item /tx 175Execute the instruction if flag f0 is true. 176@item /fx 177Execute the instruction if flag f0 is false. 178@item /xt 179Execute the instruction if flag f1 is true. 180@item /xf 181Execute the instruction if flag f1 is false. 182@item /tt 183Execute the instruction if both flags f0 and f1 are true. 184@item /tf 185Execute the instruction if flag f0 is true and flag f1 is false. 186@end table 187 188@node D30V-Regs 189@subsection Register Names 190@cindex D30V registers 191@cindex registers, D30V 192You can use the predefined symbols @samp{r0} through @samp{r63} to refer 193to the D30V registers. You can also use @samp{sp} as an alias for 194@samp{r63} and @samp{link} as an alias for @samp{r62}. The accumulators 195are @samp{a0} and @samp{a1}. 196 197The D30V also has predefined symbols for these control registers and status bits: 198@table @code 199@item psw 200Processor Status Word 201@item bpsw 202Backup Processor Status Word 203@item pc 204Program Counter 205@item bpc 206Backup Program Counter 207@item rpt_c 208Repeat Count 209@item rpt_s 210Repeat Start address 211@item rpt_e 212Repeat End address 213@item mod_s 214Modulo Start address 215@item mod_e 216Modulo End address 217@item iba 218Instruction Break Address 219@item f0 220Flag 0 221@item f1 222Flag 1 223@item f2 224Flag 2 225@item f3 226Flag 3 227@item f4 228Flag 4 229@item f5 230Flag 5 231@item f6 232Flag 6 233@item f7 234Flag 7 235@item s 236Same as flag 4 (saturation flag) 237@item v 238Same as flag 5 (overflow flag) 239@item va 240Same as flag 6 (sticky overflow flag) 241@item c 242Same as flag 7 (carry/borrow flag) 243@item b 244Same as flag 7 (carry/borrow flag) 245@end table 246 247@node D30V-Addressing 248@subsection Addressing Modes 249@cindex addressing modes, D30V 250@cindex D30V addressing modes 251@code{@value{AS}} understands the following addressing modes for the D30V. 252@code{R@var{n}} in the following refers to any of the numbered 253registers, but @emph{not} the control registers. 254@table @code 255@item R@var{n} 256Register direct 257@item @@R@var{n} 258Register indirect 259@item @@R@var{n}+ 260Register indirect with post-increment 261@item @@R@var{n}- 262Register indirect with post-decrement 263@item @@-SP 264Register indirect with pre-decrement 265@item @@(@var{disp}, R@var{n}) 266Register indirect with displacement 267@item @var{addr} 268PC relative address (for branch or rep). 269@item #@var{imm} 270Immediate data (the @samp{#} is optional and ignored) 271@end table 272 273@node D30V-Float 274@section Floating Point 275@cindex floating point, D30V 276@cindex D30V floating point 277The D30V has no hardware floating point, but the @code{.float} and @code{.double} 278directives generates @sc{ieee} floating-point numbers for compatibility 279with other development tools. 280 281@node D30V-Opcodes 282@section Opcodes 283@cindex D30V opcode summary 284@cindex opcode summary, D30V 285@cindex mnemonics, D30V 286@cindex instruction summary, D30V 287For detailed information on the D30V machine instruction set, see 288@cite{D30V Architecture: A VLIW Microprocessor for Multimedia Applications} 289(Mitsubishi Electric Corp.). 290@code{@value{AS}} implements all the standard D30V opcodes. The only changes are those 291described in the section on size modifiers 292 293