1 /* alpha.h -- Header file for Alpha opcode table 2 Copyright 1996, 1999, 2001, 2003 Free Software Foundation, Inc. 3 Contributed by Richard Henderson <rth@tamu.edu>, 4 patterned after the PPC opcode table written by Ian Lance Taylor. 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 11 1, or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 21 22 #ifndef OPCODE_ALPHA_H 23 #define OPCODE_ALPHA_H 24 25 /* The opcode table is an array of struct alpha_opcode. */ 26 27 struct alpha_opcode 28 { 29 /* The opcode name. */ 30 const char *name; 31 32 /* The opcode itself. Those bits which will be filled in with 33 operands are zeroes. */ 34 unsigned opcode; 35 36 /* The opcode mask. This is used by the disassembler. This is a 37 mask containing ones indicating those bits which must match the 38 opcode field, and zeroes indicating those bits which need not 39 match (and are presumably filled in by operands). */ 40 unsigned mask; 41 42 /* One bit flags for the opcode. These are primarily used to 43 indicate specific processors and environments support the 44 instructions. The defined values are listed below. */ 45 unsigned flags; 46 47 /* An array of operand codes. Each code is an index into the 48 operand table. They appear in the order which the operands must 49 appear in assembly code, and are terminated by a zero. */ 50 unsigned char operands[4]; 51 }; 52 53 /* The table itself is sorted by major opcode number, and is otherwise 54 in the order in which the disassembler should consider 55 instructions. */ 56 extern const struct alpha_opcode alpha_opcodes[]; 57 extern const unsigned alpha_num_opcodes; 58 59 /* Values defined for the flags field of a struct alpha_opcode. */ 60 61 /* CPU Availability */ 62 #define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */ 63 #define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */ 64 #define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */ 65 #define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */ 66 #define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */ 67 #define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */ 68 #define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */ 69 70 #define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6)) 71 72 /* A macro to extract the major opcode from an instruction. */ 73 #define AXP_OP(i) (((i) >> 26) & 0x3F) 74 75 /* The total number of major opcodes. */ 76 #define AXP_NOPS 0x40 77 78 79 /* The operands table is an array of struct alpha_operand. */ 80 81 struct alpha_operand 82 { 83 /* The number of bits in the operand. */ 84 unsigned int bits : 5; 85 86 /* How far the operand is left shifted in the instruction. */ 87 unsigned int shift : 5; 88 89 /* The default relocation type for this operand. */ 90 signed int default_reloc : 16; 91 92 /* One bit syntax flags. */ 93 unsigned int flags : 16; 94 95 /* Insertion function. This is used by the assembler. To insert an 96 operand value into an instruction, check this field. 97 98 If it is NULL, execute 99 i |= (op & ((1 << o->bits) - 1)) << o->shift; 100 (i is the instruction which we are filling in, o is a pointer to 101 this structure, and op is the opcode value; this assumes twos 102 complement arithmetic). 103 104 If this field is not NULL, then simply call it with the 105 instruction and the operand value. It will return the new value 106 of the instruction. If the ERRMSG argument is not NULL, then if 107 the operand value is illegal, *ERRMSG will be set to a warning 108 string (the operand will be inserted in any case). If the 109 operand value is legal, *ERRMSG will be unchanged (most operands 110 can accept any value). */ 111 unsigned (*insert) (unsigned instruction, int op, const char **errmsg); 112 113 /* Extraction function. This is used by the disassembler. To 114 extract this operand type from an instruction, check this field. 115 116 If it is NULL, compute 117 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 118 if ((o->flags & AXP_OPERAND_SIGNED) != 0 119 && (op & (1 << (o->bits - 1))) != 0) 120 op -= 1 << o->bits; 121 (i is the instruction, o is a pointer to this structure, and op 122 is the result; this assumes twos complement arithmetic). 123 124 If this field is not NULL, then simply call it with the 125 instruction value. It will return the value of the operand. If 126 the INVALID argument is not NULL, *INVALID will be set to 127 non-zero if this operand type can not actually be extracted from 128 this operand (i.e., the instruction does not match). If the 129 operand is valid, *INVALID will not be changed. */ 130 int (*extract) (unsigned instruction, int *invalid); 131 }; 132 133 /* Elements in the table are retrieved by indexing with values from 134 the operands field of the alpha_opcodes table. */ 135 136 extern const struct alpha_operand alpha_operands[]; 137 extern const unsigned alpha_num_operands; 138 139 /* Values defined for the flags field of a struct alpha_operand. */ 140 141 /* Mask for selecting the type for typecheck purposes */ 142 #define AXP_OPERAND_TYPECHECK_MASK \ 143 (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \ 144 AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \ 145 AXP_OPERAND_UNSIGNED) 146 147 /* This operand does not actually exist in the assembler input. This 148 is used to support extended mnemonics, for which two operands fields 149 are identical. The assembler should call the insert function with 150 any op value. The disassembler should call the extract function, 151 ignore the return value, and check the value placed in the invalid 152 argument. */ 153 #define AXP_OPERAND_FAKE 01 154 155 /* The operand should be wrapped in parentheses rather than separated 156 from the previous by a comma. This is used for the load and store 157 instructions which want their operands to look like "Ra,disp(Rb)". */ 158 #define AXP_OPERAND_PARENS 02 159 160 /* Used in combination with PARENS, this supresses the supression of 161 the comma. This is used for "jmp Ra,(Rb),hint". */ 162 #define AXP_OPERAND_COMMA 04 163 164 /* This operand names an integer register. */ 165 #define AXP_OPERAND_IR 010 166 167 /* This operand names a floating point register. */ 168 #define AXP_OPERAND_FPR 020 169 170 /* This operand is a relative branch displacement. The disassembler 171 prints these symbolically if possible. */ 172 #define AXP_OPERAND_RELATIVE 040 173 174 /* This operand takes signed values. */ 175 #define AXP_OPERAND_SIGNED 0100 176 177 /* This operand takes unsigned values. This exists primarily so that 178 a flags value of 0 can be treated as end-of-arguments. */ 179 #define AXP_OPERAND_UNSIGNED 0200 180 181 /* Supress overflow detection on this field. This is used for hints. */ 182 #define AXP_OPERAND_NOOVERFLOW 0400 183 184 /* Mask for optional argument default value. */ 185 #define AXP_OPERAND_OPTIONAL_MASK 07000 186 187 /* This operand defaults to zero. This is used for jump hints. */ 188 #define AXP_OPERAND_DEFAULT_ZERO 01000 189 190 /* This operand should default to the first (real) operand and is used 191 in conjunction with AXP_OPERAND_OPTIONAL. This allows 192 "and $0,3,$0" to be written as "and $0,3", etc. I don't like 193 it, but it's what DEC does. */ 194 #define AXP_OPERAND_DEFAULT_FIRST 02000 195 196 /* Similarly, this operand should default to the second (real) operand. 197 This allows "negl $0" instead of "negl $0,$0". */ 198 #define AXP_OPERAND_DEFAULT_SECOND 04000 199 200 201 /* Register common names */ 202 203 #define AXP_REG_V0 0 204 #define AXP_REG_T0 1 205 #define AXP_REG_T1 2 206 #define AXP_REG_T2 3 207 #define AXP_REG_T3 4 208 #define AXP_REG_T4 5 209 #define AXP_REG_T5 6 210 #define AXP_REG_T6 7 211 #define AXP_REG_T7 8 212 #define AXP_REG_S0 9 213 #define AXP_REG_S1 10 214 #define AXP_REG_S2 11 215 #define AXP_REG_S3 12 216 #define AXP_REG_S4 13 217 #define AXP_REG_S5 14 218 #define AXP_REG_FP 15 219 #define AXP_REG_A0 16 220 #define AXP_REG_A1 17 221 #define AXP_REG_A2 18 222 #define AXP_REG_A3 19 223 #define AXP_REG_A4 20 224 #define AXP_REG_A5 21 225 #define AXP_REG_T8 22 226 #define AXP_REG_T9 23 227 #define AXP_REG_T10 24 228 #define AXP_REG_T11 25 229 #define AXP_REG_RA 26 230 #define AXP_REG_PV 27 231 #define AXP_REG_T12 27 232 #define AXP_REG_AT 28 233 #define AXP_REG_GP 29 234 #define AXP_REG_SP 30 235 #define AXP_REG_ZERO 31 236 237 #endif /* OPCODE_ALPHA_H */ 238