1; Fujitsu FRV opcode support, for GNU Binutils. -*- Scheme -*- 2; 3; Copyright 2000, 2001, 2003, 2004 Free Software Foundation, Inc. 4; 5; Contributed by Red Hat Inc; developed under contract from Fujitsu. 6; 7; This file is part of the GNU Binutils. 8; 9; This program is free software; you can redistribute it and/or modify 10; it under the terms of the GNU General Public License as published by 11; the Free Software Foundation; either version 2 of the License, or 12; (at your option) any later version. 13; 14; This program is distributed in the hope that it will be useful, 15; but WITHOUT ANY WARRANTY; without even the implied warranty of 16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17; GNU General Public License for more details. 18; 19; You should have received a copy of the GNU General Public License 20; along with this program; if not, write to the Free Software 21; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 22 23(include "simplify.inc") 24 25; define-arch must appear first 26 27(define-arch 28 (name frv) ; name of cpu architecture 29 (comment "Fujitsu FRV") 30 (insn-lsb0? #t) 31 (machs frv fr550 fr500 fr400 tomcat simple) 32 (isas frv) 33) 34 35(define-isa 36 (name frv) 37 (base-insn-bitsize 32) 38 ; Initial bitnumbers to decode insns by. 39 (decode-assist (24 23 22 21 20 19 18)) 40 (liw-insns 1) ; The frv fetches up to 1 insns at a time. 41 (parallel-insns 8) ; The frv executes up to 8 insns at a time. 42) 43 44; Cpu family definitions. 45; 46(define-cpu 47 ; cpu names must be distinct from the architecture name and machine names. 48 ; The "b" suffix stands for "base" and is the convention. 49 ; The "f" suffix stands for "family" and is the convention. 50 (name frvbf) 51 (comment "Fujitsu FRV base family") 52 (endian big) 53 (word-bitsize 32) 54) 55 56; Generic FR-V machine. Supports the entire architecture 57(define-mach 58 (name frv) 59 (comment "Generic FRV cpu") 60 (cpu frvbf) 61) 62(define-model 63 (name frv) (comment "Generic FRV model") (attrs) 64 (mach frv) 65 66 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 67 68 ; `state' is a list of variables for recording model state 69 ; (state) 70 71 (unit u-exec "Execution Unit" () 72 1 1 ; issue done 73 () ; state 74 () ; inputs 75 () ; outputs 76 () ; profile action (default) 77 ) 78) 79 80; FR550 machine 81(define-mach 82 (name fr550) 83 (comment "FR550 cpu") 84 (cpu frvbf) 85) 86(define-model 87 (name fr550) (comment "FR550 model") (attrs) 88 (mach fr550) 89 90 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 91 92 ; `state' is a list of variables for recording model state 93 (state 94 ; State items 95 ; These are all masks with each bit representing one register. 96 (prev-fr-load DI) ; Previous use of FR register was target of a load 97 (prev-fr-complex-1 DI) ; Previous use of FR register has variable latency 98 (prev-fr-complex-2 DI) ; Previous use of FR register has variable latency 99 (prev-ccr-complex DI) ; Previous use of CCR register has variable latency 100 (prev-acc-mmac DI) ; Previous use of ACC register was a MMAC category 101 (cur-fr-load DI) ; Current use of FR register was target of a load 102 (cur-fr-complex-1 DI) ; Current use of FR register has variable latency 103 (cur-fr-complex-2 DI) ; Current use of FR register has variable latency 104 (cur-ccr-complex SI) ; Current use of CCR register has variable latency 105 (cur-acc-mmac DI) ; Current use of ACC register was a MMAC category 106 ) 107 ; Basic unit for instructions with no latency penalties 108 (unit u-exec "Execution Unit" () 109 1 1 ; issue done 110 () ; state 111 () ; inputs 112 () ; outputs 113 () ; profile action (default) 114 ) 115 ; Basic integer insn unit 116 (unit u-integer "Integer Unit" () 117 1 1 ; issue done 118 () ; state 119 ((GRi INT -1) (GRj INT -1)) ; inputs 120 ((GRk INT -1) (ICCi_1 INT -1)) ; outputs 121 () ; profile action (default) 122 ) 123 ; Integer multiplication unit 124 (unit u-imul "Integer Multiplication Unit" () 125 1 1 ; issue done 126 () ; state 127 ((GRi INT -1) (GRj INT -1)) ; inputs 128 ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs 129 () ; profile action (default) 130 ) 131 ; Integer division unit 132 (unit u-idiv "Integer Division Unit" () 133 1 1 ; issue done 134 () ; state 135 ((GRi INT -1) (GRj INT -1)) ; inputs 136 ((GRk INT -1) (ICCi_1 INT -1)) ; outputs 137 () ; profile action (default) 138 ) 139 ; Branch unit 140 (unit u-branch "Branch Unit" () 141 1 1 ; issue done 142 () ; state 143 ((GRi INT -1) (GRj INT -1) 144 (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs 145 ((pc)) ; outputs 146 () ; profile action (default) 147 ) 148 ; Trap unit 149 (unit u-trap "Trap Unit" () 150 1 1 ; issue done 151 () ; state 152 ((GRi INT -1) (GRj INT -1) 153 (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs 154 () ; outputs 155 () ; profile action (default) 156 ) 157 ; Condition code check unit 158 (unit u-check "Check Unit" () 159 1 1 ; issue done 160 () ; state 161 ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs 162 () ; outputs 163 () ; profile action (default) 164 ) 165 ; Float Arithmetic unit 166 (unit u-float-arith "Float Arithmetic unit" () 167 1 1 ; issue done 168 () ; state 169 ((FRi INT -1) (FRj INT -1) ; inputs 170 (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs 171 ((FRk INT -1) (FRdoublek INT -1)) ; outputs 172 () ; profile action (default) 173 ) 174 ; Float Dual Arithmetic unit 175 (unit u-float-dual-arith "Float Arithmetic unit" () 176 ; This unit has a 2 cycle penalty -- see table 14-14 in the fr550 LSI 177 1 3 ; issue done 178 () ; state 179 ((FRi INT -1) (FRj INT -1) ; inputs 180 (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs 181 ((FRk INT -1) (FRdoublek INT -1)) ; outputs 182 () ; profile action (default) 183 ) 184 ; Float Div unit 185 (unit u-float-div "Float Div unit" () 186 1 1 ; issue done 187 () ; state 188 ((FRi INT -1) (FRj INT -1)) ; inputs 189 ((FRk INT -1)) ; outputs 190 () ; profile action (default) 191 ) 192 ; Float Square Root unit 193 (unit u-float-sqrt "Float Square Root unit" () 194 1 1 ; issue done 195 () ; state 196 ((FRj INT -1) (FRdoublej INT -1)) ; inputs 197 ((FRk INT -1) (FRdoublek INT -1)) ; outputs 198 () ; profile action (default) 199 ) 200 ; Float Compare unit 201 (unit u-float-compare "Float Compare unit" () 202 1 1 ; issue done 203 () ; state 204 ((FRi INT -1) (FRj INT -1) 205 (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs 206 ((FCCi_2 INT -1)) ; outputs 207 () ; profile action (default) 208 ) 209 ; Dual Float Compare unit 210 (unit u-float-dual-compare "Float Dual Compare unit" () 211 ; This unit has a 2 cycle penalty -- see table 14-14 in the fr550 LSI 212 1 3 ; issue done 213 () ; state 214 ((FRi INT -1) (FRj INT -1)) ; inputs 215 ((FCCi_2 INT -1)) ; outputs 216 () ; profile action (default) 217 ) 218 ; FR Move to GR unit 219 (unit u-fr2gr "FR Move to GR Unit" () 220 1 1 ; issue done 221 () ; state 222 ((FRintk INT -1)) ; inputs 223 ((GRj INT -1)) ; outputs 224 () ; profile action (default) 225 ) 226 ; GR Move to FR unit 227 (unit u-gr2fr "GR Move to FR Unit" () 228 1 1 ; issue done 229 () ; state 230 ((GRj INT -1)) ; inputs 231 ((FRintk INT -1)) ; outputs 232 () ; profile action (default) 233 ) 234 ; SPR Move to GR unit 235 (unit u-spr2gr "SPR Move to GR Unit" () 236 1 1 ; issue done 237 () ; state 238 ((spr INT -1)) ; inputs 239 ((GRj INT -1)) ; outputs 240 () ; profile action (default) 241 ) 242 ; GR Move to SPR unit 243 (unit u-gr2spr "GR Move to SPR Unit" () 244 1 1 ; issue done 245 () ; state 246 ((GRj INT -1)) ; inputs 247 ((spr INT -1)) ; outputs 248 () ; profile action (default) 249 ) 250 ; GR set half unit 251 (unit u-set-hilo "GR Set Half" () 252 1 1 ; issue done 253 () ; state 254 () ; inputs 255 ((GRkhi INT -1) (GRklo INT -1)) ; outputs 256 () ; profile action (default) 257 ) 258 ; GR load unit 259 (unit u-gr-load "GR Load Unit" () 260 1 1 ; issue done 261 () ; state 262 ((GRi INT -1) (GRj INT -1)) ; inputs 263 ((GRk INT -1) (GRdoublek INT -1)) ; outputs 264 () ; profile action (default) 265 ) 266 ; GR store unit 267 (unit u-gr-store "GR Store Unit" () 268 1 1 ; issue done 269 () ; state 270 ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs 271 () ; outputs 272 () ; profile action (default) 273 ) 274 ; FR load unit 275 (unit u-fr-load "FR Load Unit" () 276 1 1 ; issue done 277 () ; state 278 ((GRi INT -1) (GRj INT -1)) ; inputs 279 ((FRintk INT -1) (FRdoublek INT -1)) ; outputs 280 () ; profile action (default) 281 ) 282 ; FR store unit 283 (unit u-fr-store "FR Store Unit" () 284 1 1 ; issue done 285 () ; state 286 ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs 287 () ; outputs 288 () ; profile action (default) 289 ) 290 ; Swap unit 291 (unit u-swap "Swap Unit" () 292 1 1 ; issue done 293 () ; state 294 ((GRi INT -1) (GRj INT -1)) ; inputs 295 ((GRk INT -1)) ; outputs 296 () ; profile action (default) 297 ) 298 ; FR Move to FR unit 299 (unit u-fr2fr "FR Move to FR Unit" () 300 1 1 ; issue done 301 () ; state 302 ((FRi INT -1)) ; inputs 303 ((FRk INT -1)) ; outputs 304 () ; profile action (default) 305 ) 306 ; Clrgr unit 307 (unit u-clrgr "Clrgr Unit" () 308 1 1 ; issue done 309 () ; state 310 ((GRk INT -1)) ; inputs 311 () ; outputs 312 () ; profile action (default) 313 ) 314 ; Clrfr unit 315 (unit u-clrfr "Clrfr Unit" () 316 1 1 ; issue done 317 () ; state 318 ((FRk INT -1)) ; inputs 319 () ; outputs 320 () ; profile action (default) 321 ) 322 ; Insn cache invalidate unit 323 (unit u-ici "Insn cache invalidate unit" () 324 1 1 ; issue done 325 () ; state 326 ((GRi INT -1) (GRj INT -1)) ; inputs 327 () ; outputs 328 () ; profile action (default) 329 ) 330 ; Data cache invalidate unit 331 (unit u-dci "Data cache invalidate unit" () 332 1 1 ; issue done 333 () ; state 334 ((GRi INT -1) (GRj INT -1)) ; inputs 335 () ; outputs 336 () ; profile action (default) 337 ) 338 ; Data cache flush unit 339 (unit u-dcf "Data cache flush unit" () 340 1 1 ; issue done 341 () ; state 342 ((GRi INT -1) (GRj INT -1)) ; inputs 343 () ; outputs 344 () ; profile action (default) 345 ) 346 ; Insn cache preload unit 347 (unit u-icpl "Insn cache preload unit" () 348 1 1 ; issue done 349 () ; state 350 ((GRi INT -1) (GRj INT -1)) ; inputs 351 () ; outputs 352 () ; profile action (default) 353 ) 354 ; Data cache preload unit 355 (unit u-dcpl "Data cache preload unit" () 356 1 1 ; issue done 357 () ; state 358 ((GRi INT -1) (GRj INT -1)) ; inputs 359 () ; outputs 360 () ; profile action (default) 361 ) 362 ; Insn cache unlock unit 363 (unit u-icul "Insn cache unlock unit" () 364 1 1 ; issue done 365 () ; state 366 ((GRi INT -1) (GRj INT -1)) ; inputs 367 () ; outputs 368 () ; profile action (default) 369 ) 370 ; Data cache unlock unit 371 (unit u-dcul "Data cache unlock unit" () 372 1 1 ; issue done 373 () ; state 374 ((GRi INT -1) (GRj INT -1)) ; inputs 375 () ; outputs 376 () ; profile action (default) 377 ) 378 ; commit unit 379 (unit u-commit "Commit Unit" () 380 1 1 ; issue done 381 () ; state 382 ((GRk INT -1) (FRk INT -1)) ; inputs 383 () ; outputs 384 () ; profile action (default) 385 ) 386 ; Float Conversion unit 387 (unit u-float-convert "Float Conversion unit" () 388 1 1 ; issue done 389 () ; state 390 ((FRj INT -1) (FRintj INT -1) (FRdoublej INT -1)) ; inputs 391 ((FRk INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; outputs 392 () ; profile action (default) 393 ) 394 ; Media units 395 (unit u-media "Media unit" () 396 1 1 ; issue done 397 () ; state 398 ((FRinti INT -1) (FRintj INT -1)) ; inputs 399 ((FRintk INT -1)) ; outputs 400 () ; profile action (default) 401 ) 402 (unit u-media-quad "Media-quad unit" () 403 1 1 ; issue done 404 () ; state 405 ((FRintieven INT -1) (FRintjeven INT -1)) ; inputs 406 ((FRintkeven INT -1)) ; outputs 407 () ; profile action (default) 408 ) 409 (unit u-media-dual-expand "Media Dual Expand unit" () 410 1 1 ; issue done 411 () ; state 412 ((FRinti INT -1)) ; inputs 413 ((FRintkeven INT -1)) ; outputs 414 () ; profile action (default) 415 ) 416 (unit u-media-3-dual "Media-3-dual unit" () 417 1 1 ; issue done 418 () ; state 419 ((FRinti INT -1)) ; inputs 420 ((FRintk INT -1)) ; outputs 421 () ; profile action (default) 422 ) 423 (unit u-media-3-acc "Media unit for M-3 using ACC" () 424 1 1 ; issue done 425 () ; state 426 ((FRintj INT -1) (ACC40Si INT -1)) ; inputs 427 ((FRintk INT -1)) ; outputs 428 () ; profile action (default) 429 ) 430 (unit u-media-3-acc-dual "Media-3-acc-dual unit" () 431 1 1 ; issue done 432 () ; state 433 ((ACC40Si INT -1)) ; inputs 434 ((FRintkeven INT -1)) ; outputs 435 () ; profile action (default) 436 ) 437 (unit u-media-3-wtacc "Media-3-wtacc unit" () 438 1 1 ; issue done 439 () ; state 440 ((FRinti INT -1) (ACC40Sk INT -1)) ; inputs 441 () ; outputs 442 () ; profile action (default) 443 ) 444 (unit u-media-3-mclracc "Media-3-mclracc unit" () 445 1 1 ; issue done 446 () ; state 447 () ; inputs 448 () ; outputs 449 () ; profile action (default) 450 ) 451 (unit u-media-set "Media set" () 452 1 1 ; issue done 453 () ; state 454 () ; inputs 455 ((FRintk INT -1)) ; outputs 456 () ; profile action (default) 457 ) 458 (unit u-media-4 "Media-4 unit" () 459 1 1 ; issue done 460 () ; state 461 ((FRinti INT -1) (FRintj INT -1)) ; inputs 462 ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs 463 () ; profile action (default) 464 ) 465 (unit u-media-4-acc "Media-4-acc unit" () 466 1 1 ; issue done 467 () ; state 468 ((ACC40Si INT -1)) ; inputs 469 ((ACC40Sk INT -1)) ; outputs 470 () ; profile action (default) 471 ) 472 (unit u-media-4-acc-dual "Media-4-acc-dual unit" () 473 1 1 ; issue done 474 () ; state 475 ((ACC40Si INT -1)) ; inputs 476 ((ACC40Sk INT -1)) ; outputs 477 () ; profile action (default) 478 ) 479 (unit u-media-4-add-sub "Media-4-add-sub unit" () 480 1 1 ; issue done 481 () ; state 482 ((ACC40Si INT -1)) ; inputs 483 ((ACC40Sk INT -1)) ; outputs 484 () ; profile action (default) 485 ) 486 (unit u-media-4-add-sub-dual "Media-4-add-sub-dual unit" () 487 1 1 ; issue done 488 () ; state 489 ((ACC40Si INT -1)) ; inputs 490 ((ACC40Sk INT -1)) ; outputs 491 () ; profile action (default) 492 ) 493 (unit u-media-4-quad "Media-4-quad unit" () 494 1 1 ; issue done 495 () ; state 496 ((FRintieven INT -1) (FRintjeven INT -1)) ; inputs 497 ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs 498 () ; profile action (default) 499 ) 500) 501 502; FR500 machine. 503(define-mach 504 (name fr500) 505 (comment "FR500 cpu") 506 (cpu frvbf) 507) 508(define-model 509 (name fr500) (comment "FR500 model") (attrs) 510 (mach fr500) 511 512 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 513 514 ; `state' is a list of variables for recording model state 515 (state 516 ; State items 517 ; These are all masks with each bit representing one register. 518 (prev-fpop DI) ; Previous use of FR register was floating point insn 519 (prev-media DI) ; Previous use of FR register was a media insn 520 (prev-cc-complex DI) ; Previous use of ICC register was not simple 521 (cur-fpop DI) ; Current use of FR register was floating point insn 522 (cur-media DI) ; Current use of FR register was a media insn 523 (cur-cc-complex DI) ; Current use of ICC register was not simple 524 ) 525 ; Basic unit for instructions with no latency penalties 526 (unit u-exec "Execution Unit" () 527 1 1 ; issue done 528 () ; state 529 () ; inputs 530 () ; outputs 531 () ; profile action (default) 532 ) 533 ; Basic integer insn unit 534 (unit u-integer "Integer Unit" () 535 1 1 ; issue done 536 () ; state 537 ((GRi INT -1) (GRj INT -1)) ; inputs 538 ((GRk INT -1) (ICCi_1 INT -1)) ; outputs 539 () ; profile action (default) 540 ) 541 ; Integer multiplication unit 542 (unit u-imul "Integer Multiplication Unit" () 543 1 1 ; issue done 544 () ; state 545 ((GRi INT -1) (GRj INT -1)) ; inputs 546 ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs 547 () ; profile action (default) 548 ) 549 ; Integer division unit 550 (unit u-idiv "Integer Division Unit" () 551 1 1 ; issue done 552 () ; state 553 ((GRi INT -1) (GRj INT -1)) ; inputs 554 ((GRk INT -1) (ICCi_1 INT -1)) ; outputs 555 () ; profile action (default) 556 ) 557 ; Branch unit 558 (unit u-branch "Branch Unit" () 559 1 1 ; issue done 560 () ; state 561 ((GRi INT -1) (GRj INT -1) 562 (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs 563 ((pc)) ; outputs 564 () ; profile action (default) 565 ) 566 ; Trap unit 567 (unit u-trap "Trap Unit" () 568 1 1 ; issue done 569 () ; state 570 ((GRi INT -1) (GRj INT -1) 571 (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs 572 () ; outputs 573 () ; profile action (default) 574 ) 575 ; Condition code check unit 576 (unit u-check "Check Unit" () 577 1 1 ; issue done 578 () ; state 579 ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs 580 () ; outputs 581 () ; profile action (default) 582 ) 583 ; Clrgr unit 584 (unit u-clrgr "Clrgr Unit" () 585 1 1 ; issue done 586 () ; state 587 ((GRk INT -1)) ; inputs 588 () ; outputs 589 () ; profile action (default) 590 ) 591 ; Clrfr unit 592 (unit u-clrfr "Clrfr Unit" () 593 1 1 ; issue done 594 () ; state 595 ((FRk INT -1)) ; inputs 596 () ; outputs 597 () ; profile action (default) 598 ) 599 ; GR set half unit 600 (unit u-set-hilo "GR Set Half" () 601 1 1 ; issue done 602 () ; state 603 () ; inputs 604 ((GRkhi INT -1) (GRklo INT -1)) ; outputs 605 () ; profile action (default) 606 ) 607 ; GR load unit -- TODO doesn't handle quad 608 (unit u-gr-load "GR Load Unit" () 609 1 1 ; issue done 610 () ; state 611 ((GRi INT -1) (GRj INT -1)) ; inputs 612 ((GRk INT -1) (GRdoublek INT -1)) ; outputs 613 () ; profile action (default) 614 ) 615 ; GR store unit -- TODO doesn't handle quad 616 (unit u-gr-store "GR Store Unit" () 617 1 1 ; issue done 618 () ; state 619 ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs 620 () ; outputs 621 () ; profile action (default) 622 ) 623 ; GR recovering store unit -- TODO doesn't handle quad 624 (unit u-gr-r-store "GR Recovering Store Unit" () 625 1 1 ; issue done 626 () ; state 627 ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs 628 () ; outputs 629 () ; profile action (default) 630 ) 631 ; FR load unit -- TODO doesn't handle quad 632 (unit u-fr-load "FR Load Unit" () 633 1 1 ; issue done 634 () ; state 635 ((GRi INT -1) (GRj INT -1)) ; inputs 636 ((FRintk INT -1) (FRdoublek INT -1)) ; outputs 637 () ; profile action (default) 638 ) 639 ; FR store unit -- TODO doesn't handle quad 640 (unit u-fr-store "FR Store Unit" () 641 1 1 ; issue done 642 () ; state 643 ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs 644 () ; outputs 645 () ; profile action (default) 646 ) 647 ; FR recovering store unit -- TODO doesn't handle quad 648 (unit u-fr-r-store "FR Recovering Store Unit" () 649 1 1 ; issue done 650 () ; state 651 ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs 652 () ; outputs 653 () ; profile action (default) 654 ) 655 ; Swap unit 656 (unit u-swap "Swap Unit" () 657 1 1 ; issue done 658 () ; state 659 ((GRi INT -1) (GRj INT -1)) ; inputs 660 ((GRk INT -1)) ; outputs 661 () ; profile action (default) 662 ) 663 ; FR Move to FR unit 664 (unit u-fr2fr "FR Move to FR Unit" () 665 1 1 ; issue done 666 () ; state 667 ((FRi INT -1)) ; inputs 668 ((FRk INT -1)) ; outputs 669 () ; profile action (default) 670 ) 671 ; FR Move to GR unit 672 (unit u-fr2gr "FR Move to GR Unit" () 673 1 1 ; issue done 674 () ; state 675 ((FRintk INT -1)) ; inputs 676 ((GRj INT -1)) ; outputs 677 () ; profile action (default) 678 ) 679 ; SPR Move to GR unit 680 (unit u-spr2gr "SPR Move to GR Unit" () 681 1 1 ; issue done 682 () ; state 683 ((spr INT -1)) ; inputs 684 ((GRj INT -1)) ; outputs 685 () ; profile action (default) 686 ) 687 ; GR Move to FR unit 688 (unit u-gr2fr "GR Move to FR Unit" () 689 1 1 ; issue done 690 () ; state 691 ((GRj INT -1)) ; inputs 692 ((FRintk INT -1)) ; outputs 693 () ; profile action (default) 694 ) 695 ; GR Move to SPR unit 696 (unit u-gr2spr "GR Move to SPR Unit" () 697 1 1 ; issue done 698 () ; state 699 ((GRj INT -1)) ; inputs 700 ((spr INT -1)) ; outputs 701 () ; profile action (default) 702 ) 703 ; Float Arithmetic unit 704 (unit u-float-arith "Float Arithmetic unit" () 705 1 1 ; issue done 706 () ; state 707 ((FRi INT -1) (FRj INT -1) ; inputs 708 (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs 709 ((FRk INT -1) (FRdoublek INT -1)) ; outputs 710 () ; profile action (default) 711 ) 712 ; Float Dual Arithmetic unit 713 (unit u-float-dual-arith "Float Arithmetic unit" () 714 1 1 ; issue done 715 () ; state 716 ((FRi INT -1) (FRj INT -1) ; inputs 717 (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs 718 ((FRk INT -1) (FRdoublek INT -1)) ; outputs 719 () ; profile action (default) 720 ) 721 ; Float Div unit 722 (unit u-float-div "Float Div unit" () 723 1 1 ; issue done 724 () ; state 725 ((FRi INT -1) (FRj INT -1)) ; inputs 726 ((FRk INT -1)) ; outputs 727 () ; profile action (default) 728 ) 729 ; Float Square Root unit 730 (unit u-float-sqrt "Float Square Root unit" () 731 1 1 ; issue done 732 () ; state 733 ((FRj INT -1) (FRdoublej INT -1)) ; inputs 734 ((FRk INT -1) (FRdoublek INT -1)) ; outputs 735 () ; profile action (default) 736 ) 737 ; Float Dual Square Root unit 738 (unit u-float-dual-sqrt "Float Dual Square Root unit" () 739 1 1 ; issue done 740 () ; state 741 ((FRj INT -1)) ; inputs 742 ((FRk INT -1)) ; outputs 743 () ; profile action (default) 744 ) 745 ; Float Compare unit 746 (unit u-float-compare "Float Compare unit" () 747 1 1 ; issue done 748 () ; state 749 ((FRi INT -1) (FRj INT -1) 750 (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs 751 ((FCCi_2 INT -1)) ; outputs 752 () ; profile action (default) 753 ) 754 ; Dual Float Compare unit 755 (unit u-float-dual-compare "Float Dual Compare unit" () 756 1 1 ; issue done 757 () ; state 758 ((FRi INT -1) (FRj INT -1)) ; inputs 759 ((FCCi_2 INT -1)) ; outputs 760 () ; profile action (default) 761 ) 762 ; Float Conversion unit 763 (unit u-float-convert "Float Conversion unit" () 764 1 1 ; issue done 765 () ; state 766 ((FRj INT -1) (FRintj INT -1) (FRdoublej INT -1)) ; inputs 767 ((FRk INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; outputs 768 () ; profile action (default) 769 ) 770 ; Dual Float Conversion unit 771 (unit u-float-dual-convert "Float Dual Conversion unit" () 772 1 1 ; issue done 773 () ; state 774 ((FRj INT -1) (FRintj INT -1)) ; inputs 775 ((FRk INT -1) (FRintk INT -1)) ; outputs 776 () ; profile action (default) 777 ) 778 ; Media unit 779 (unit u-media "Media unit" () 780 1 1 ; issue done 781 () ; state 782 ((FRinti INT -1) (FRintj INT -1) (ACC40Si INT -1) (ACCGi INT -1)) ; inputs 783 ((FRintk INT -1) (ACC40Sk INT -1) (ACC40Uk INT -1) (ACCGk INT -1)) ; outputs 784 () ; profile action (default) 785 ) 786 ; Media Quad Arithmetic unit 787 (unit u-media-quad-arith "Media Quad Arithmetic unit" () 788 1 1 ; issue done 789 () ; state 790 ((FRinti INT -1) (FRintj INT -1)) ; inputs 791 ((FRintk INT -1)) ; outputs 792 () ; profile action (default) 793 ) 794 ; Media Dual Multiplication unit 795 (unit u-media-dual-mul "Media Dual Multiplication unit" () 796 1 1 ; issue done 797 () ; state 798 ((FRinti INT -1) (FRintj INT -1)) ; inputs 799 ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs 800 () ; profile action (default) 801 ) 802 ; Media Quad Multiplication unit 803 (unit u-media-quad-mul "Media Quad Multiplication unit" () 804 1 1 ; issue done 805 () ; state 806 ((FRinti INT -1) (FRintj INT -1)) ; inputs 807 ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs 808 () ; profile action (default) 809 ) 810 ; Media Quad Complex unit 811 (unit u-media-quad-complex "Media Quad Complex unit" () 812 1 1 ; issue done 813 () ; state 814 ((FRinti INT -1) (FRintj INT -1)) ; inputs 815 ((ACC40Sk INT -1)) ; outputs 816 () ; profile action (default) 817 ) 818 ; Media Dual Expand unit 819 (unit u-media-dual-expand "Media Dual Expand unit" () 820 1 1 ; issue done 821 () ; state 822 ((FRinti INT -1)) ; inputs 823 ((FRintk INT -1)) ; outputs 824 () ; profile action (default) 825 ) 826 ; Media Dual Unpack unit 827 (unit u-media-dual-unpack "Media Dual Unpack unit" () 828 1 1 ; issue done 829 () ; state 830 ((FRinti INT -1)) ; inputs 831 ((FRintk INT -1)) ; outputs 832 () ; profile action (default) 833 ) 834 ; Media Dual byte to half unit 835 (unit u-media-dual-btoh "Media Byte to byte" () 836 1 1 ; issue done 837 () ; state 838 ((FRintj INT -1)) ; inputs 839 ((FRintk INT -1)) ; outputs 840 () ; profile action (default) 841 ) 842 ; Media Dual half to byte unit 843 (unit u-media-dual-htob "Media Half to byte" () 844 1 1 ; issue done 845 () ; state 846 ((FRintj INT -1)) ; inputs 847 ((FRintk INT -1)) ; outputs 848 () ; profile action (default) 849 ) 850 ; Media Dual byte to half unit extended 851 (unit u-media-dual-btohe "Media Byte to byte extended" () 852 1 1 ; issue done 853 () ; state 854 ((FRintj INT -1)) ; inputs 855 ((FRintk INT -1)) ; outputs 856 () ; profile action (default) 857 ) 858 ; Barrier unit 859 (unit u-barrier "Barrier unit" () 860 1 1 ; issue done 861 () ; state 862 () ; inputs 863 () ; outputs 864 () ; profile action (default) 865 ) 866 ; Memory Barrier unit 867 (unit u-membar "Memory Barrier unit" () 868 1 1 ; issue done 869 () ; state 870 () ; inputs 871 () ; outputs 872 () ; profile action (default) 873 ) 874 ; Insn cache invalidate unit 875 (unit u-ici "Insn cache invalidate unit" () 876 1 1 ; issue done 877 () ; state 878 ((GRi INT -1) (GRj INT -1)) ; inputs 879 () ; outputs 880 () ; profile action (default) 881 ) 882 ; Data cache invalidate unit 883 (unit u-dci "Data cache invalidate unit" () 884 1 1 ; issue done 885 () ; state 886 ((GRi INT -1) (GRj INT -1)) ; inputs 887 () ; outputs 888 () ; profile action (default) 889 ) 890 ; Data cache flush unit 891 (unit u-dcf "Data cache flush unit" () 892 1 1 ; issue done 893 () ; state 894 ((GRi INT -1) (GRj INT -1)) ; inputs 895 () ; outputs 896 () ; profile action (default) 897 ) 898 ; Insn cache preload unit 899 (unit u-icpl "Insn cache preload unit" () 900 1 1 ; issue done 901 () ; state 902 ((GRi INT -1) (GRj INT -1)) ; inputs 903 () ; outputs 904 () ; profile action (default) 905 ) 906 ; Data cache preload unit 907 (unit u-dcpl "Data cache preload unit" () 908 1 1 ; issue done 909 () ; state 910 ((GRi INT -1) (GRj INT -1)) ; inputs 911 () ; outputs 912 () ; profile action (default) 913 ) 914 ; Insn cache unlock unit 915 (unit u-icul "Insn cache unlock unit" () 916 1 1 ; issue done 917 () ; state 918 ((GRi INT -1) (GRj INT -1)) ; inputs 919 () ; outputs 920 () ; profile action (default) 921 ) 922 ; Data cache unlock unit 923 (unit u-dcul "Data cache unlock unit" () 924 1 1 ; issue done 925 () ; state 926 ((GRi INT -1) (GRj INT -1)) ; inputs 927 () ; outputs 928 () ; profile action (default) 929 ) 930 ; commit unit 931 (unit u-commit "Commit Unit" () 932 1 1 ; issue done 933 () ; state 934 ((GRk INT -1) (FRk INT -1)) ; inputs 935 () ; outputs 936 () ; profile action (default) 937 ) 938) 939 940; Tomcat machine. Early version of fr500 machine 941(define-mach 942 (name tomcat) 943 (comment "Tomcat -- early version of fr500") 944 (cpu frvbf) 945) 946(define-model 947 (name tomcat) (comment "Tomcat model") (attrs) 948 (mach tomcat) 949 950 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 951 952 ; `state' is a list of variables for recording model state 953 ; (state) 954 955 (unit u-exec "Execution Unit" () 956 1 1 ; issue done 957 () ; state 958 () ; inputs 959 () ; outputs 960 () ; profile action (default) 961 ) 962) 963 964; FR400 machine 965(define-mach 966 (name fr400) 967 (comment "FR400 cpu") 968 (cpu frvbf) 969) 970(define-model 971 (name fr400) (comment "FR400 model") (attrs) 972 (mach fr400) 973 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 974 ; `state' is a list of variables for recording model state 975 (state 976 ; State items 977 ; These are all masks with each bit representing one register. 978 (prev-fp-load DI) ; Previous use of FR register was floating point load 979 (prev-fr-p4 DI) ; Previous use of FR register was media unit 4 980 (prev-fr-p6 DI) ; Previous use of FR register was media unit 6 981 (prev-acc-p2 DI) ; Previous use of ACC register was media unit 2 982 (prev-acc-p4 DI) ; Previous use of ACC register was media unit 4 983 (cur-fp-load DI) ; Current use of FR register is floating point load 984 (cur-fr-p4 DI) ; Current use of FR register is media unit 4 985 (cur-fr-p6 DI) ; Current use of FR register is media unit 6 986 (cur-acc-p2 DI) ; Current use of ACC register is media unit 2 987 (cur-acc-p4 DI) ; Current use of ACC register is media unit 4 988 ) 989 (unit u-exec "Execution Unit" () 990 1 1 ; issue done 991 () ; state 992 () ; inputs 993 () ; outputs 994 () ; profile action (default) 995 ) 996 ; Basic integer insn unit 997 (unit u-integer "Integer Unit" () 998 1 1 ; issue done 999 () ; state 1000 ((GRi INT -1) (GRj INT -1)) ; inputs 1001 ((GRk INT -1) (ICCi_1 INT -1)) ; outputs 1002 () ; profile action (default) 1003 ) 1004 ; Integer multiplication unit 1005 (unit u-imul "Integer Multiplication Unit" () 1006 1 1 ; issue done 1007 () ; state 1008 ((GRi INT -1) (GRj INT -1)) ; inputs 1009 ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs 1010 () ; profile action (default) 1011 ) 1012 ; Integer division unit 1013 (unit u-idiv "Integer Division Unit" () 1014 1 1 ; issue done 1015 () ; state 1016 ((GRi INT -1) (GRj INT -1)) ; inputs 1017 ((GRk INT -1) (ICCi_1 INT -1)) ; outputs 1018 () ; profile action (default) 1019 ) 1020 ; Branch unit 1021 (unit u-branch "Branch Unit" () 1022 1 1 ; issue done 1023 () ; state 1024 ((GRi INT -1) (GRj INT -1) 1025 (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs 1026 ((pc)) ; outputs 1027 () ; profile action (default) 1028 ) 1029 ; Trap unit 1030 (unit u-trap "Trap Unit" () 1031 1 1 ; issue done 1032 () ; state 1033 ((GRi INT -1) (GRj INT -1) 1034 (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs 1035 () ; outputs 1036 () ; profile action (default) 1037 ) 1038 ; Condition code check unit 1039 (unit u-check "Check Unit" () 1040 1 1 ; issue done 1041 () ; state 1042 ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs 1043 () ; outputs 1044 () ; profile action (default) 1045 ) 1046 ; GR set half unit 1047 (unit u-set-hilo "GR Set Half" () 1048 1 1 ; issue done 1049 () ; state 1050 () ; inputs 1051 ((GRkhi INT -1) (GRklo INT -1)) ; outputs 1052 () ; profile action (default) 1053 ) 1054 ; GR load unit -- TODO doesn't handle quad 1055 (unit u-gr-load "GR Load Unit" () 1056 1 1 ; issue done 1057 () ; state 1058 ((GRi INT -1) (GRj INT -1)) ; inputs 1059 ((GRk INT -1) (GRdoublek INT -1)) ; outputs 1060 () ; profile action (default) 1061 ) 1062 ; GR store unit -- TODO doesn't handle quad 1063 (unit u-gr-store "GR Store Unit" () 1064 1 1 ; issue done 1065 () ; state 1066 ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs 1067 () ; outputs 1068 () ; profile action (default) 1069 ) 1070 ; FR load unit -- TODO doesn't handle quad 1071 (unit u-fr-load "FR Load Unit" () 1072 1 1 ; issue done 1073 () ; state 1074 ((GRi INT -1) (GRj INT -1)) ; inputs 1075 ((FRintk INT -1) (FRdoublek INT -1)) ; outputs 1076 () ; profile action (default) 1077 ) 1078 ; FR store unit -- TODO doesn't handle quad 1079 (unit u-fr-store "FR Store Unit" () 1080 1 1 ; issue done 1081 () ; state 1082 ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs 1083 () ; outputs 1084 () ; profile action (default) 1085 ) 1086 ; Swap unit 1087 (unit u-swap "Swap Unit" () 1088 1 1 ; issue done 1089 () ; state 1090 ((GRi INT -1) (GRj INT -1)) ; inputs 1091 ((GRk INT -1)) ; outputs 1092 () ; profile action (default) 1093 ) 1094 ; FR Move to GR unit 1095 (unit u-fr2gr "FR Move to GR Unit" () 1096 1 1 ; issue done 1097 () ; state 1098 ((FRintk INT -1)) ; inputs 1099 ((GRj INT -1)) ; outputs 1100 () ; profile action (default) 1101 ) 1102 ; SPR Move to GR unit 1103 (unit u-spr2gr "SPR Move to GR Unit" () 1104 1 1 ; issue done 1105 () ; state 1106 ((spr INT -1)) ; inputs 1107 ((GRj INT -1)) ; outputs 1108 () ; profile action (default) 1109 ) 1110 ; GR Move to FR unit 1111 (unit u-gr2fr "GR Move to FR Unit" () 1112 1 1 ; issue done 1113 () ; state 1114 ((GRj INT -1)) ; inputs 1115 ((FRintk INT -1)) ; outputs 1116 () ; profile action (default) 1117 ) 1118 ; GR Move to SPR unit 1119 (unit u-gr2spr "GR Move to SPR Unit" () 1120 1 1 ; issue done 1121 () ; state 1122 ((GRj INT -1)) ; inputs 1123 ((spr INT -1)) ; outputs 1124 () ; profile action (default) 1125 ) 1126 ; Media unit M1 -- see table 13-8 in the fr400 LSI 1127 (unit u-media-1 "Media-1 unit" () 1128 1 1 ; issue done 1129 () ; state 1130 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1131 ((FRintk INT -1)) ; outputs 1132 () ; profile action (default) 1133 ) 1134 (unit u-media-1-quad "Media-1-quad unit" () 1135 1 1 ; issue done 1136 () ; state 1137 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1138 ((FRintk INT -1)) ; outputs 1139 () ; profile action (default) 1140 ) 1141 (unit u-media-hilo "Media-hilo unit -- a variation of the Media-1 unit" () 1142 1 1 ; issue done 1143 () ; state 1144 () ; inputs 1145 ((FRkhi INT -1) (FRklo INT -1)) ; outputs 1146 () ; profile action (default) 1147 ) 1148 ; Media unit M2 -- see table 13-8 in the fr400 LSI 1149 (unit u-media-2 "Media-2 unit" () 1150 1 1 ; issue done 1151 () ; state 1152 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1153 ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs 1154 () ; profile action (default) 1155 ) 1156 (unit u-media-2-quad "Media-2-quad unit" () 1157 1 1 ; issue done 1158 () ; state 1159 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1160 ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs 1161 () ; profile action (default) 1162 ) 1163 (unit u-media-2-acc "Media-2-acc unit" () 1164 1 1 ; issue done 1165 () ; state 1166 ((ACC40Si INT -1)) ; inputs 1167 ((ACC40Sk INT -1)) ; outputs 1168 () ; profile action (default) 1169 ) 1170 (unit u-media-2-acc-dual "Media-2-acc-dual unit" () 1171 1 1 ; issue done 1172 () ; state 1173 ((ACC40Si INT -1)) ; inputs 1174 ((ACC40Sk INT -1)) ; outputs 1175 () ; profile action (default) 1176 ) 1177 (unit u-media-2-add-sub "Media-2-add-sub unit" () 1178 1 1 ; issue done 1179 () ; state 1180 ((ACC40Si INT -1)) ; inputs 1181 ((ACC40Sk INT -1)) ; outputs 1182 () ; profile action (default) 1183 ) 1184 (unit u-media-2-add-sub-dual "Media-2-add-sub-dual unit" () 1185 1 1 ; issue done 1186 () ; state 1187 ((ACC40Si INT -1)) ; inputs 1188 ((ACC40Sk INT -1)) ; outputs 1189 () ; profile action (default) 1190 ) 1191 ; Media unit M3 -- see table 13-8 in the fr400 LSI 1192 (unit u-media-3 "Media-3 unit" () 1193 1 1 ; issue done 1194 () ; state 1195 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1196 ((FRintk INT -1)) ; outputs 1197 () ; profile action (default) 1198 ) 1199 (unit u-media-3-dual "Media-3-dual unit" () 1200 1 1 ; issue done 1201 () ; state 1202 ((FRinti INT -1)) ; inputs 1203 ((FRintk INT -1)) ; outputs 1204 () ; profile action (default) 1205 ) 1206 (unit u-media-3-quad "Media-3-quad unit" () 1207 1 1 ; issue done 1208 () ; state 1209 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1210 ((FRintk INT -1)) ; outputs 1211 () ; profile action (default) 1212 ) 1213 ; Media unit M4 -- see table 13-8 in the fr400 LSI 1214 (unit u-media-4 "Media-4 unit" () 1215 1 1 ; issue done 1216 () ; state 1217 ((ACC40Si INT -1) (FRintj INT -1)) ; inputs 1218 ((ACC40Sk INT -1) (FRintk INT -1)) ; outputs 1219 () ; profile action (default) 1220 ) 1221 (unit u-media-4-accg "Media-4-accg unit" () 1222 1 1 ; issue done 1223 () ; state 1224 ((ACCGi INT -1) (FRinti INT -1)) ; inputs 1225 ((ACCGk INT -1) (FRintk INT -1)) ; outputs 1226 () ; profile action (default) 1227 ) 1228 (unit u-media-4-acc-dual "Media-4-acc-dual unit" () 1229 1 1 ; issue done 1230 () ; state 1231 ((ACC40Si INT -1)) ; inputs 1232 ((FRintk INT -1)) ; outputs 1233 () ; profile action (default) 1234 ) 1235 ; Media unit M6 -- see table 13-8 in the fr400 LSI 1236 (unit u-media-6 "Media-6 unit" () 1237 1 1 ; issue done 1238 () ; state 1239 ((FRinti INT -1)) ; inputs 1240 ((FRintk INT -1)) ; outputs 1241 () ; profile action (default) 1242 ) 1243 ; Media unit M7 -- see table 13-8 in the fr400 LSI 1244 (unit u-media-7 "Media-1 unit" () 1245 1 1 ; issue done 1246 () ; state 1247 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1248 ((FCCk INT -1)) ; outputs 1249 () ; profile action (default) 1250 ) 1251 ; Media Dual Expand unit 1252 (unit u-media-dual-expand "Media Dual Expand unit" () 1253 1 1 ; issue done 1254 () ; state 1255 ((FRinti INT -1)) ; inputs 1256 ((FRintk INT -1)) ; outputs 1257 () ; profile action (default) 1258 ) 1259 ; Media Dual half to byte unit 1260 (unit u-media-dual-htob "Media Half to byte" () 1261 1 1 ; issue done 1262 () ; state 1263 ((FRintj INT -1)) ; inputs 1264 ((FRintk INT -1)) ; outputs 1265 () ; profile action (default) 1266 ) 1267 ; Barrier unit 1268 (unit u-barrier "Barrier unit" () 1269 1 1 ; issue done 1270 () ; state 1271 () ; inputs 1272 () ; outputs 1273 () ; profile action (default) 1274 ) 1275 ; Memory Barrier unit 1276 (unit u-membar "Memory Barrier unit" () 1277 1 1 ; issue done 1278 () ; state 1279 () ; inputs 1280 () ; outputs 1281 () ; profile action (default) 1282 ) 1283 ; Insn cache invalidate unit 1284 (unit u-ici "Insn cache invalidate unit" () 1285 1 1 ; issue done 1286 () ; state 1287 ((GRi INT -1) (GRj INT -1)) ; inputs 1288 () ; outputs 1289 () ; profile action (default) 1290 ) 1291 ; Data cache invalidate unit 1292 (unit u-dci "Data cache invalidate unit" () 1293 1 1 ; issue done 1294 () ; state 1295 ((GRi INT -1) (GRj INT -1)) ; inputs 1296 () ; outputs 1297 () ; profile action (default) 1298 ) 1299 ; Data cache flush unit 1300 (unit u-dcf "Data cache flush unit" () 1301 1 1 ; issue done 1302 () ; state 1303 ((GRi INT -1) (GRj INT -1)) ; inputs 1304 () ; outputs 1305 () ; profile action (default) 1306 ) 1307 ; Insn cache preload unit 1308 (unit u-icpl "Insn cache preload unit" () 1309 1 1 ; issue done 1310 () ; state 1311 ((GRi INT -1) (GRj INT -1)) ; inputs 1312 () ; outputs 1313 () ; profile action (default) 1314 ) 1315 ; Data cache preload unit 1316 (unit u-dcpl "Data cache preload unit" () 1317 1 1 ; issue done 1318 () ; state 1319 ((GRi INT -1) (GRj INT -1)) ; inputs 1320 () ; outputs 1321 () ; profile action (default) 1322 ) 1323 ; Insn cache unlock unit 1324 (unit u-icul "Insn cache unlock unit" () 1325 1 1 ; issue done 1326 () ; state 1327 ((GRi INT -1) (GRj INT -1)) ; inputs 1328 () ; outputs 1329 () ; profile action (default) 1330 ) 1331 ; Data cache unlock unit 1332 (unit u-dcul "Data cache unlock unit" () 1333 1 1 ; issue done 1334 () ; state 1335 ((GRi INT -1) (GRj INT -1)) ; inputs 1336 () ; outputs 1337 () ; profile action (default) 1338 ) 1339) 1340 1341; Simple machine - single issue integer machine 1342(define-mach 1343 (name simple) 1344 (comment "Simple single issue integer cpu") 1345 (cpu frvbf) 1346) 1347(define-model 1348 (name simple) (comment "Simple model") (attrs) 1349 (mach simple) 1350 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 1351 ; `state' is a list of variables for recording model state 1352 (state) 1353 (unit u-exec "Execution Unit" () 1354 1 1 ; issue done 1355 () ; state 1356 () ; inputs 1357 () ; outputs 1358 () ; profile action (default) 1359 ) 1360) 1361 1362; The instruction fetch/execute cycle. 1363; 1364; This is how to fetch and decode an instruction. 1365; Leave it out for now 1366 1367; (define-extract (const SI 0)) 1368 1369; This is how to execute a decoded instruction. 1370; Leave it out for now 1371 1372; (define-execute (const SI 0)) 1373 1374; An attribute to describe which unit an insn runs in. 1375(define-attr 1376 (for insn) 1377 (type enum) 1378 (name UNIT) 1379 (comment "parallel execution pipeline selection") 1380 ; The order of declaration is significant. 1381 ; See the *_unit_mapping tables in frv.opc 1382 ; Keep variations on the same unit together. 1383 ; Keep the '01' variant immediately after the '1' variant in each unit. 1384 ; Keep the 'ALL' variations immediately after the last numbered variant in each unit. 1385 (values NIL 1386 I0 I1 I01 I2 I3 IALL 1387 FM0 FM1 FM01 FM2 FM3 FMALL FMLOW 1388 B0 B1 B01 1389 C 1390 MULT-DIV ; multiply/division slotted differently on different machines 1391 IACC ; iacc multiply slotted differently on different machines 1392 LOAD ; loads slotted differently on different machines 1393 STORE ; store slotted differently on different machines 1394 SCAN ; scan, scani slotted differently on different machines 1395 DCPL ; dcpl slotted differently on different machines 1396 MDUALACC ; media dual acc slotted differently on different machines 1397 MCLRACC-1; mclracc A==1 slotted differently on different machines 1398 NUM_UNITS 1399 ) 1400) 1401; Attributes to describe major categories of insns 1402(define-attr 1403 (for insn) 1404 (type enum) 1405 (name FR400-MAJOR) 1406 (comment "fr400 major insn categories") 1407 ; The order of declaration is significant. Keep variations on the same major 1408 ; together. 1409 (values NONE 1410 I-1 I-2 I-3 I-4 I-5 1411 B-1 B-2 B-3 B-4 B-5 B-6 1412 C-1 C-2 1413 M-1 M-2 1414 ) 1415) 1416(define-attr 1417 (for insn) 1418 (type enum) 1419 (name FR500-MAJOR) 1420 (comment "fr500 major insn categories") 1421 ; The order of declaration is significant. Keep variations on the same major 1422 ; together. 1423 (values NONE 1424 I-1 I-2 I-3 I-4 I-5 I-6 1425 B-1 B-2 B-3 B-4 B-5 B-6 1426 C-1 C-2 1427 F-1 F-2 F-3 F-4 F-5 F-6 F-7 F-8 1428 M-1 M-2 M-3 M-4 M-5 M-6 M-7 M-8 1429 ) 1430) 1431(define-attr 1432 (for insn) 1433 (type enum) 1434 (name FR550-MAJOR) 1435 (comment "fr550 major insn categories") 1436 ; The order of declaration is significant. Keep variations on the same major 1437 ; together. 1438 (values NONE 1439 I-1 I-2 I-3 I-4 I-5 I-6 I-7 I-8 1440 B-1 B-2 B-3 B-4 B-5 B-6 1441 C-1 C-2 1442 F-1 F-2 F-3 F-4 1443 M-1 M-2 M-3 M-4 M-5 1444 ) 1445) 1446; Privileged insn 1447(define-attr 1448 (for insn) 1449 (type boolean) 1450 (name PRIVILEGED) 1451 (comment "insn only allowed in supervisor mode") 1452) 1453; Non-Excepting insn 1454(define-attr 1455 (for insn) 1456 (type boolean) 1457 (name NON-EXCEPTING) 1458 (comment "non-excepting insn") 1459) 1460; Conditional insn 1461(define-attr 1462 (for insn) 1463 (type boolean) 1464 (name CONDITIONAL) 1465 (comment "conditional insn") 1466) 1467; insn accesses FR registers 1468(define-attr 1469 (for insn) 1470 (type boolean) 1471 (name FR-ACCESS) 1472 (comment "insn accesses FR registers") 1473) 1474; insn preserves MSR.OVF 1475(define-attr 1476 (for insn) 1477 (type boolean) 1478 (name PRESERVE-OVF) 1479 (comment "Preserve value of MSR.OVF") 1480) 1481; null attribute -- used as a place holder for where an attribue is required. 1482(define-attr 1483 (for insn) 1484 (type boolean) 1485 (name NA) 1486 (comment "placeholder attribute") 1487 (attrs META) ; do not define in any generated file for now 1488) 1489 1490; IDOC attribute for instruction documentation. 1491 1492(define-attr 1493 (for insn) 1494 (type enum) 1495 (name IDOC) 1496 (comment "insn kind for documentation") 1497 (attrs META) 1498 (values 1499 (MEM - () "Memory") 1500 (ALU - () "ALU") 1501 (FPU - () "FPU") 1502 (BR - () "Branch") 1503 (PRIV - () "Priviledged") 1504 (MISC - () "Miscellaneous") 1505 ) 1506) 1507 1508; Instruction fields. 1509; 1510; Attributes: 1511; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) 1512; ABS-ADDR: absolute address (for reloc and disassembly purposes?) 1513; RESERVED: bits are not used to decode insn, must be all 0 1514(dnf f-pack "packing bit" () 31 1) 1515(dnf f-op "primary opcode" () 24 7) 1516(dnf f-ope1 "extended opcode" () 11 6) 1517(dnf f-ope2 "extended opcode" () 9 4) 1518(dnf f-ope3 "extended opcode" () 15 3) 1519(dnf f-ope4 "extended opcode" () 7 2) 1520 1521(dnf f-GRi "source register 1" () 17 6) 1522(dnf f-GRj "source register 2" () 5 6) 1523(dnf f-GRk "destination register" () 30 6) 1524 1525(dnf f-FRi "source register 1" () 17 6) 1526(dnf f-FRj "source register 2" () 5 6) 1527(dnf f-FRk "destination register" () 30 6) 1528 1529(dnf f-CPRi "source register 1" () 17 6) 1530(dnf f-CPRj "source register 2" () 5 6) 1531(dnf f-CPRk "destination register" () 30 6) 1532 1533(dnf f-ACCGi "source register" () 17 6) 1534(dnf f-ACCGk "destination register" () 30 6) 1535 1536(dnf f-ACC40Si "40 bit signed accumulator" () 17 6) 1537(dnf f-ACC40Ui "40 bit unsigned accumulator" () 17 6) 1538(dnf f-ACC40Sk "40 bit accumulator" () 30 6) 1539(dnf f-ACC40Uk "40 bit accumulator" () 30 6) 1540 1541(dnf f-CRi "source register" () 14 3) 1542(dnf f-CRj "source register" () 2 3) 1543(dnf f-CRk "destination register" () 27 3) 1544(dnf f-CCi "condition register" () 11 3) 1545 1546(df f-CRj_int "target cr for ck insns" () 26 2 UINT 1547 ((value pc) (sub WI value 4)) 1548 ((value pc) (add WI value 4)) 1549) 1550(dnf f-CRj_float "target cr for fck insns" () 26 2) 1551 1552(dnf f-ICCi_1 "condition register" () 11 2) 1553(dnf f-ICCi_2 "condition register" () 26 2) 1554(dnf f-ICCi_3 "condition register" () 1 2) 1555(dnf f-FCCi_1 "condition register" () 11 2) 1556(dnf f-FCCi_2 "condition register" () 26 2) 1557(dnf f-FCCi_3 "condition register" () 1 2) 1558(dnf f-FCCk "condition register" () 26 2) 1559(dnf f-eir "exception insn register" () 17 6) 1560 1561(df f-s10 "10 bit sign extended" () 9 10 INT #f #f) 1562(df f-s12 "12 bit sign extended" () 11 12 INT #f #f) 1563(df f-d12 "12 bit sign extended" () 11 12 INT #f #f) 1564(df f-u16 "16 bit unsigned" () 15 16 UINT #f #f) 1565(df f-s16 "16 bit sign extended" () 15 16 INT #f #f) 1566(df f-s6 "6 bit signed" () 5 6 INT #f #f) 1567(df f-s6_1 "6 bit signed" () 11 6 INT #f #f) 1568(df f-u6 "6 bit unsigned" () 5 6 UINT #f #f) 1569(df f-s5 "5 bit signed" () 4 5 INT #f #f) 1570 1571(df f-u12-h "upper 6 bits of u12" () 17 6 INT #f #f) 1572(df f-u12-l "lower 6 bits of u12" () 5 6 UINT #f #f) 1573(dnmf f-u12 "12 bit signed immediate" () INT 1574 (f-u12-h f-u12-l) 1575 (sequence () ; insert 1576 (set (ifield f-u12-h) (sra SI (ifield f-u12) 6)) 1577 (set (ifield f-u12-l) (and (ifield f-u12) #x3f)) 1578 ) 1579 (sequence () ; extract 1580 (set (ifield f-u12) (or (sll (ifield f-u12-h) 6) 1581 (ifield f-u12-l))) 1582 ) 1583) 1584 1585(dnf f-int-cc "integer branch conditions" () 30 4) 1586(dnf f-flt-cc "floating branch conditions" () 30 4) 1587(df f-cond "conditional arithmetic" () 8 1 UINT #f #f) 1588(df f-ccond "lr branch condition" () 12 1 UINT #f #f) 1589(df f-hint "2 bit branch prediction hint" () 17 2 UINT #f #f) 1590(df f-LI "link indicator" () 25 1 UINT #f #f) 1591(df f-lock "cache lock indicator" () 25 1 UINT #f #f) 1592(df f-debug "debug mode indicator" () 25 1 UINT #f #f) 1593(df f-A "all accumulator bit" () 17 1 UINT #f #f) 1594(df f-ae "cache all entries indicator" () 25 1 UINT #f #f) 1595 1596(dnf f-spr-h "upper 6 bits of spr" () 30 6) 1597(dnf f-spr-l "lower 6 bits of spr" () 17 6) 1598(dnmf f-spr "special purpose register" () UINT 1599 (f-spr-h f-spr-l) 1600 (sequence () ; insert 1601 (set (ifield f-spr-h) (srl (ifield f-spr) (const 6))) 1602 (set (ifield f-spr-l) (and (ifield f-spr) (const #x3f))) 1603 ) 1604 (sequence () ; extract 1605 (set (ifield f-spr) (or (sll (ifield f-spr-h) (const 6)) 1606 (ifield f-spr-l))) 1607 ) 1608) 1609 1610(df f-label16 "18 bit pc relative signed offset" (PCREL-ADDR) 15 16 INT 1611 ((value pc) (sra WI (sub WI value pc) (const 2))) 1612 ((value pc) (add WI (sll WI value (const 2)) pc)) 1613) 1614 1615(df f-labelH6 "upper 6 bits of label24" () 30 6 INT #f #f) 1616(dnf f-labelL18 "lower 18 bits of label24" () 17 18) 1617(dnmf f-label24 "26 bit signed offset" (PCREL-ADDR) INT 1618 (f-labelH6 f-labelL18) 1619 ; insert 1620 (sequence () 1621 (set (ifield f-labelH6) 1622 (sra WI (sub (ifield f-label24) pc) (const 20))) 1623 (set (ifield f-labelL18) 1624 (and (srl (sub (ifield f-label24) pc) (const 2)) 1625 (const #x3ffff))) 1626 ) 1627 ; extract 1628 (sequence () 1629 (set (ifield f-label24) 1630 (add (sll (or (sll (ifield f-labelH6) (const 18)) 1631 (ifield f-labelL18)) 1632 (const 2)) 1633 pc))) 1634) 1635 1636(dnf f-ICCi_1-null "null field" (RESERVED) 11 2) 1637(dnf f-ICCi_2-null "null field" (RESERVED) 26 2) 1638(dnf f-ICCi_3-null "null field" (RESERVED) 1 2) 1639(dnf f-FCCi_1-null "null field" (RESERVED) 11 2) 1640(dnf f-FCCi_2-null "null field" (RESERVED) 26 2) 1641(dnf f-FCCi_3-null "null field" (RESERVED) 1 2) 1642(dnf f-rs-null "null field" (RESERVED) 17 6) 1643(dnf f-GRi-null "null field" (RESERVED) 17 6) 1644(dnf f-GRj-null "null field" (RESERVED) 5 6) 1645(dnf f-GRk-null "null field" (RESERVED) 30 6) 1646(dnf f-FRi-null "null field" (RESERVED) 17 6) 1647(dnf f-FRj-null "null field" (RESERVED) 5 6) 1648(dnf f-ACCj-null "null field" (RESERVED) 5 6) 1649(dnf f-rd-null "null field" (RESERVED) 30 6) 1650(dnf f-cond-null "null field" (RESERVED) 30 4) 1651(dnf f-ccond-null "null field" (RESERVED) 12 1) 1652(dnf f-s12-null "null field" (RESERVED) 11 12) 1653(dnf f-label16-null "null field" (RESERVED) 15 16) 1654(dnf f-misc-null-1 "null field" (RESERVED) 30 5) 1655(dnf f-misc-null-2 "null field" (RESERVED) 11 6) 1656(dnf f-misc-null-3 "null field" (RESERVED) 11 4) 1657(dnf f-misc-null-4 "null field" (RESERVED) 17 2) 1658(dnf f-misc-null-5 "null field" (RESERVED) 17 16) 1659(dnf f-misc-null-6 "null field" (RESERVED) 30 3) 1660(dnf f-misc-null-7 "null field" (RESERVED) 17 3) 1661(dnf f-misc-null-8 "null field" (RESERVED) 5 3) 1662(dnf f-misc-null-9 "null field" (RESERVED) 5 4) 1663(dnf f-misc-null-10 "null field" (RESERVED) 16 5) 1664(dnf f-misc-null-11 "null field" (RESERVED) 5 1) 1665 1666(dnf f-LI-off "null field" (RESERVED) 25 1) 1667(dnf f-LI-on "null field" (RESERVED) 25 1) 1668 1669; Enums. 1670 1671; insn-op: 1672; FIXME: should use die macro or some such 1673(define-normal-insn-enum insn-op "insn op enums" () OP_ f-op 1674 ( 1675 "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F" 1676 "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "1A" "1B" "1C" "1D" "1E" "1F" 1677 "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "2A" "2B" "2C" "2D" "2E" "2F" 1678 "30" "31" "32" "33" "34" "35" "36" "37" "38" "39" "3A" "3B" "3C" "3D" "3E" "3F" 1679 "40" "41" "42" "43" "44" "45" "46" "47" "48" "49" "4A" "4B" "4C" "4D" "4E" "4F" 1680 "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "5A" "5B" "5C" "5D" "5E" "5F" 1681 "60" "61" "62" "63" "64" "65" "66" "67" "68" "69" "6A" "6B" "6C" "6D" "6E" "6F" 1682 "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" "7A" "7B" "7C" "7D" "7E" "7F" 1683 ) 1684) 1685 1686(define-normal-insn-enum insn-ope1 "insn ope enums" () OPE1_ f-ope1 1687 ( 1688 "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F" 1689 "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "1A" "1B" "1C" "1D" "1E" "1F" 1690 "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "2A" "2B" "2C" "2D" "2E" "2F" 1691 "30" "31" "32" "33" "34" "35" "36" "37" "38" "39" "3A" "3B" "3C" "3D" "3E" "3F" 1692 ) 1693) 1694 1695(define-normal-insn-enum insn-ope2 "insn ope enums" () OPE2_ f-ope2 1696 ( 1697 "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F" 1698 ) 1699) 1700 1701(define-normal-insn-enum insn-ope3 "insn ope enums" () OPE3_ f-ope3 1702 ( 1703 "00" "01" "02" "03" "04" "05" "06" "07" 1704 ) 1705) 1706 1707(define-normal-insn-enum insn-ope4 "insn ope enums" () OPE4_ f-ope4 1708 ( 1709 "0" "1" "2" "3" 1710 ) 1711) 1712 1713; int-cc: integer branch conditions 1714; FIXME: should use die macro or some such 1715(define-normal-insn-enum int-cc "integer branch cond enums" () ICC_ f-int-cc 1716 ( 1717 "nev" "c" "v" "lt" "eq" "ls" "n" "le" 1718 "ra" "nc" "nv" "ge" "ne" "hi" "p" "gt" 1719 ) 1720) 1721 1722; flt-cc: floating-point/media branch conditions 1723; FIXME: should use die macro or some such 1724(define-normal-insn-enum flt-cc "float branch cond enums" () FCC_ f-flt-cc 1725 ("nev" "u" "gt" "ug" "lt" "ul" "lg" "ne" 1726 "eq" "ue" "ge" "uge" "le" "ule" "o" "ra") 1727) 1728 1729; Hardware pieces. 1730; These entries list the elements of the raw hardware. 1731; They're also used to provide tables and other elements of the assembly 1732; language. 1733(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) 1734 1735; The PSR. The individual fields are referenced more than the entire 1736; register, so reference them directly. We can assemble the 1737; entire register contents when necessary. 1738; 1739(dsh h-psr_imple "PSR.IMPLE" () (register UQI)) 1740(dsh h-psr_ver "PSR.VER" () (register UQI)) 1741(dsh h-psr_ice "PSR.ICE bit" () (register BI)) 1742(dsh h-psr_nem "PSR.NEM bit" () (register BI)) 1743(dsh h-psr_cm "PSR.CM bit" () (register BI)) 1744(dsh h-psr_be "PSR.BE bit" () (register BI)) 1745(dsh h-psr_esr "PSR.ESR bit" () (register BI)) 1746(dsh h-psr_ef "PSR.EF bit" () (register BI)) 1747(dsh h-psr_em "PSR.EM bit" () (register BI)) 1748(dsh h-psr_pil "PSR.PIL " () (register UQI)) 1749(dsh h-psr_ps "PSR.PS bit" () (register BI)) 1750(dsh h-psr_et "PSR.ET bit" () (register BI)) 1751 1752; PSR.S requires special handling because the shadow registers (SR0-SR4) must 1753; be switched with GR4-GR7 when changing from user to supervisor mode or 1754; vice-versa. 1755(define-hardware 1756 (name h-psr_s) 1757 (comment "PSR.S bit") 1758 (attrs) 1759 (type register BI) 1760 (get) 1761 (set (newval) (c-call VOID "@cpu@_h_psr_s_set_handler" newval)) 1762) 1763 1764; The TBR. The individual bits are referenced more than the entire 1765; register, so reference them directly. We can assemble the 1766; entire register contents when necessary. 1767; 1768(dsh h-tbr_tba "TBR.TBA" () (register UWI)) 1769(dsh h-tbr_tt "TBR.TT" () (register UQI)) 1770 1771; The BPSR. The individual bits are referenced more than the entire 1772; register, so reference them directly. We can assemble the 1773; entire register contents when necessary. 1774; 1775(dsh h-bpsr_bs "PSR.S bit" () (register BI)) 1776(dsh h-bpsr_bet "PSR.ET bit" () (register BI)) 1777 1778; General registers 1779; 1780(define-keyword 1781 (name gr-names) 1782 (print-name h-gr) 1783 (prefix "") 1784 (values 1785 (sp 1) (fp 2) 1786 (gr0 0)(gr1 1)(gr2 2)(gr3 3)(gr4 4)(gr5 5)(gr6 6)(gr7 7) 1787 (gr8 8)(gr9 9)(gr10 10)(gr11 11)(gr12 12)(gr13 13)(gr14 14)(gr15 15) 1788 (gr16 16)(gr17 17)(gr18 18)(gr19 19)(gr20 20)(gr21 21)(gr22 22)(gr23 23) 1789 (gr24 24)(gr25 25)(gr26 26)(gr27 27)(gr28 28)(gr29 29)(gr30 30)(gr31 31) 1790 (gr32 32)(gr33 33)(gr34 34)(gr35 35)(gr36 36)(gr37 37)(gr38 38)(gr39 39) 1791 (gr40 40)(gr41 41)(gr42 42)(gr43 43)(gr44 44)(gr45 45)(gr46 46)(gr47 47) 1792 (gr48 48)(gr49 49)(gr50 50)(gr51 51)(gr52 52)(gr53 53)(gr54 54)(gr55 55) 1793 (gr56 56)(gr57 57)(gr58 58)(gr59 59)(gr60 60)(gr61 61)(gr62 62)(gr63 63) 1794 ) 1795) 1796 1797(define-hardware 1798 (name h-gr) 1799 (comment "general registers") 1800 (attrs PROFILE) 1801 (type register USI (64)) 1802 (indices extern-keyword gr-names) 1803 (get (index) (c-call WI "@cpu@_h_gr_get_handler" index)) 1804 (set (index newval) (c-call VOID "@cpu@_h_gr_set_handler" index newval)) 1805) 1806 1807; General Registers as double words 1808; These registers are shadowed onto h-gr 1809(define-hardware 1810 (name h-gr_double) 1811 (comment "general registers as double words") 1812 (attrs PROFILE VIRTUAL) 1813 (type register DI (32)) 1814 ; FIXME: Need constraint to prohibit odd numbers. 1815 (indices extern-keyword gr-names) 1816 (get (index) 1817 (c-call DI "@cpu@_h_gr_double_get_handler" index)) 1818 (set (index newval) 1819 (c-call VOID "@cpu@_h_gr_double_set_handler" index newval)) 1820) 1821 1822; General Registers as high and low half words 1823; These registers are shadowed onto h-gr 1824(define-hardware 1825 (name h-gr_hi) 1826 (comment "general registers as high half word") 1827 (attrs PROFILE VIRTUAL) 1828 (type register UHI (64)) 1829 (indices extern-keyword gr-names) 1830 (get (index) (c-call UHI "@cpu@_h_gr_hi_get_handler" index)) 1831 (set (index newval) (c-call VOID "@cpu@_h_gr_hi_set_handler" index newval)) 1832) 1833(define-hardware 1834 (name h-gr_lo) 1835 (comment "general registers as low half word") 1836 (attrs PROFILE VIRTUAL) 1837 (type register UHI (64)) 1838 (indices extern-keyword gr-names) 1839 (get (index) (c-call UHI "@cpu@_h_gr_lo_get_handler" index)) 1840 (set (index newval) (c-call VOID "@cpu@_h_gr_lo_set_handler" index newval)) 1841) 1842 1843; Floating Point Registers 1844(define-keyword 1845 (name fr-names) 1846 (print-name h-fr) 1847 (prefix "") 1848 (values 1849 (fr0 0)(fr1 1)(fr2 2)(fr3 3)(fr4 4)(fr5 5)(fr6 6)(fr7 7) 1850 (fr8 8)(fr9 9)(fr10 10)(fr11 11)(fr12 12)(fr13 13)(fr14 14)(fr15 15) 1851 (fr16 16)(fr17 17)(fr18 18)(fr19 19)(fr20 20)(fr21 21)(fr22 22)(fr23 23) 1852 (fr24 24)(fr25 25)(fr26 26)(fr27 27)(fr28 28)(fr29 29)(fr30 30)(fr31 31) 1853 (fr32 32)(fr33 33)(fr34 34)(fr35 35)(fr36 36)(fr37 37)(fr38 38)(fr39 39) 1854 (fr40 40)(fr41 41)(fr42 42)(fr43 43)(fr44 44)(fr45 45)(fr46 46)(fr47 47) 1855 (fr48 48)(fr49 49)(fr50 50)(fr51 51)(fr52 52)(fr53 53)(fr54 54)(fr55 55) 1856 (fr56 56)(fr57 57)(fr58 58)(fr59 59)(fr60 60)(fr61 61)(fr62 62)(fr63 63) 1857 ) 1858) 1859 1860(define-hardware 1861 (name h-fr) 1862 (comment "floating point registers") 1863 (attrs PROFILE) 1864 (type register SF (64)) 1865 (indices extern-keyword fr-names) 1866 (get (index) (c-call SF "@cpu@_h_fr_get_handler" index)) 1867 (set (index newval) (c-call VOID "@cpu@_h_fr_set_handler" index newval)) 1868) 1869 1870; Floating Point Registers as double precision 1871; These registers are shadowed onto h-fr 1872 1873(define-hardware 1874 (name h-fr_double) 1875 (comment "floating point registers as double precision") 1876 (attrs PROFILE VIRTUAL) 1877 (type register DF (32)) 1878 ; FIXME: Need constraint to prohibit odd numbers. 1879 (indices extern-keyword fr-names) 1880 (get (index) 1881 (c-call DF "@cpu@_h_fr_double_get_handler" index)) 1882 (set (index newval) 1883 (c-call VOID "@cpu@_h_fr_double_set_handler" index newval)) 1884) 1885 1886; Floating Point Registers as integer words. 1887; These registers are shadowed onto h-fr 1888 1889(define-hardware 1890 (name h-fr_int) 1891 (comment "floating point registers as integers") 1892 (attrs PROFILE VIRTUAL) 1893 (type register USI (64)) 1894 (indices extern-keyword fr-names) 1895 (get (index) 1896 (c-call USI "@cpu@_h_fr_int_get_handler" index)) 1897 (set (index newval) 1898 (c-call VOID "@cpu@_h_fr_int_set_handler" index newval)) 1899) 1900 1901; Floating Point Registers as high and low half words 1902; These registers are shadowed onto h-fr 1903(define-hardware 1904 (name h-fr_hi) 1905 (comment "floating point registers as unsigned high half word") 1906 (attrs PROFILE VIRTUAL) 1907 (type register UHI (64)) 1908 (indices extern-keyword fr-names) 1909 (get (regno) (srl (reg h-fr_int regno) 16)) 1910 (set (regno newval) (set (reg h-fr_int regno) 1911 (or (and (reg h-fr_int regno) #xffff) 1912 (sll newval 16)))) 1913) 1914(define-hardware 1915 (name h-fr_lo) 1916 (comment "floating point registers as unsigned low half word") 1917 (attrs PROFILE VIRTUAL) 1918 (type register UHI (64)) 1919 (indices extern-keyword fr-names) 1920 (get (regno) (and (reg h-fr_int regno) #xffff)) 1921 (set (regno newval) (set (reg h-fr_int regno) 1922 (or (and (reg h-fr_int regno) #xffff0000) 1923 (and newval #xffff)))) 1924) 1925 1926; Floating Point Registers as unsigned bytes 1927; These registers are shadowed onto h-fr 1928(define-hardware 1929 (name h-fr_0) 1930 (comment "floating point registers as unsigned byte 0") 1931 (attrs PROFILE VIRTUAL) 1932 (type register UHI (64)) 1933 (indices extern-keyword fr-names) 1934 (get (regno) (and (reg h-fr_int regno) #xff)) 1935 (set (regno newval) 1936 (sequence () 1937 (if (gt USI newval #xff) 1938 (set newval #xff)) 1939 (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xffffff00) 1940 newval)))) 1941) 1942(define-hardware 1943 (name h-fr_1) 1944 (comment "floating point registers as unsigned byte 1") 1945 (attrs PROFILE VIRTUAL) 1946 (type register UHI (64)) 1947 (indices extern-keyword fr-names) 1948 (get (regno) (and (srl (reg h-fr_int regno) 8) #xff)) 1949 (set (regno newval) 1950 (sequence () 1951 (if (gt USI newval #xff) 1952 (set newval #xff)) 1953 (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xffff00ff) 1954 (sll newval 8))))) 1955) 1956(define-hardware 1957 (name h-fr_2) 1958 (comment "floating point registers as unsigned byte 2") 1959 (attrs PROFILE VIRTUAL) 1960 (type register UHI (64)) 1961 (indices extern-keyword fr-names) 1962 (get (regno) (and (srl (reg h-fr_int regno) 16) #xff)) 1963 (set (regno newval) 1964 (sequence () 1965 (if (gt USI newval #xff) 1966 (set newval #xff)) 1967 (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xff00ffff) 1968 (sll newval 16))))) 1969) 1970(define-hardware 1971 (name h-fr_3) 1972 (comment "floating point registers as unsigned byte 3") 1973 (attrs PROFILE VIRTUAL) 1974 (type register UHI (64)) 1975 (indices extern-keyword fr-names) 1976 (get (regno) (and (srl (reg h-fr_int regno) 24) #xff)) 1977 (set (regno newval) 1978 (sequence () 1979 (if (gt USI newval #xff) 1980 (set newval #xff)) 1981 (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #x00ffffff) 1982 (sll newval 24))))) 1983) 1984; Coprocessor Registers 1985; 1986(define-keyword 1987 (name cpr-names) 1988 (print-name h-cpr) 1989 (prefix "") 1990 (values 1991(cpr0 0)(cpr1 1)(cpr2 2)(cpr3 3)(cpr4 4)(cpr5 5)(cpr6 6)(cpr7 7) 1992(cpr8 8)(cpr9 9)(cpr10 10)(cpr11 11)(cpr12 12)(cpr13 13)(cpr14 14)(cpr15 15) 1993(cpr16 16)(cpr17 17)(cpr18 18)(cpr19 19)(cpr20 20)(cpr21 21)(cpr22 22)(cpr23 23) 1994(cpr24 24)(cpr25 25)(cpr26 26)(cpr27 27)(cpr28 28)(cpr29 29)(cpr30 30)(cpr31 31) 1995(cpr32 32)(cpr33 33)(cpr34 34)(cpr35 35)(cpr36 36)(cpr37 37)(cpr38 38)(cpr39 39) 1996(cpr40 40)(cpr41 41)(cpr42 42)(cpr43 43)(cpr44 44)(cpr45 45)(cpr46 46)(cpr47 47) 1997(cpr48 48)(cpr49 49)(cpr50 50)(cpr51 51)(cpr52 52)(cpr53 53)(cpr54 54)(cpr55 55) 1998(cpr56 56)(cpr57 57)(cpr58 58)(cpr59 59)(cpr60 60)(cpr61 61)(cpr62 62)(cpr63 63) 1999 ) 2000) 2001 2002(define-hardware 2003 (name h-cpr) 2004 (comment "coprocessor registers") 2005 (attrs PROFILE (MACH frv)) 2006 (type register WI (64)) 2007 (indices extern-keyword cpr-names) 2008) 2009 2010; Coprocessor Registers as double words 2011; These registers are shadowed onto h-cpr 2012(define-hardware 2013 (name h-cpr_double) 2014 (comment "coprocessor registers as double words") 2015 (attrs PROFILE VIRTUAL (MACH frv)) 2016 (type register DI (32)) 2017 ; FIXME: Need constraint to prohibit odd numbers. 2018 (indices extern-keyword cpr-names) 2019 (get (index) 2020 (c-call DI "@cpu@_h_cpr_double_get_handler" index)) 2021 (set (index newval) 2022 (c-call VOID "@cpu@_h_cpr_double_set_handler" index newval)) 2023) 2024 2025; Special Purpose Registers 2026; 2027(define-keyword 2028 (name spr-names) 2029 (print-name h-spr) 2030 (prefix "") 2031 (values 2032 (psr 0) (pcsr 1) (bpcsr 2) (tbr 3) (bpsr 4) 2033 2034 (hsr0 16) (hsr1 17) (hsr2 18) (hsr3 19) 2035 (hsr4 20) (hsr5 21) (hsr6 22) (hsr7 23) 2036 (hsr8 24) (hsr9 25) (hsr10 26) (hsr11 27) 2037 (hsr12 28) (hsr13 29) (hsr14 30) (hsr15 31) 2038 (hsr16 32) (hsr17 33) (hsr18 34) (hsr19 35) 2039 (hsr20 36) (hsr21 37) (hsr22 38) (hsr23 39) 2040 (hsr24 40) (hsr25 41) (hsr26 42) (hsr27 43) 2041 (hsr28 44) (hsr29 45) (hsr30 46) (hsr31 47) 2042 (hsr32 48) (hsr33 49) (hsr34 50) (hsr35 51) 2043 (hsr36 52) (hsr37 53) (hsr38 54) (hsr39 55) 2044 (hsr40 56) (hsr41 57) (hsr42 58) (hsr43 59) 2045 (hsr44 60) (hsr45 61) (hsr46 62) (hsr47 63) 2046 (hsr48 64) (hsr49 65) (hsr50 66) (hsr51 67) 2047 (hsr52 68) (hsr53 69) (hsr54 70) (hsr55 71) 2048 (hsr56 72) (hsr57 73) (hsr58 74) (hsr59 75) 2049 (hsr60 76) (hsr61 77) (hsr62 78) (hsr63 79) 2050 2051 (ccr 256) (cccr 263) (lr 272) (lcr 273) (iacc0h 280) (iacc0l 281) (isr 288) 2052 2053 (neear0 352) (neear1 353) (neear2 354) (neear3 355) 2054 (neear4 356) (neear5 357) (neear6 358) (neear7 359) 2055 (neear8 360) (neear9 361) (neear10 362) (neear11 363) 2056 (neear12 364) (neear13 365) (neear14 366) (neear15 367) 2057 (neear16 368) (neear17 369) (neear18 370) (neear19 371) 2058 (neear20 372) (neear21 373) (neear22 374) (neear23 375) 2059 (neear24 376) (neear25 377) (neear26 378) (neear27 379) 2060 (neear28 380) (neear29 381) (neear30 382) (neear31 383) 2061 2062 (nesr0 384) (nesr1 385) (nesr2 386) (nesr3 387) 2063 (nesr4 388) (nesr5 389) (nesr6 390) (nesr7 391) 2064 (nesr8 392) (nesr9 393) (nesr10 394) (nesr11 395) 2065 (nesr12 396) (nesr13 397) (nesr14 398) (nesr15 399) 2066 (nesr16 400) (nesr17 401) (nesr18 402) (nesr19 403) 2067 (nesr20 404) (nesr21 405) (nesr22 406) (nesr23 407) 2068 (nesr24 408) (nesr25 409) (nesr26 410) (nesr27 411) 2069 (nesr28 412) (nesr29 413) (nesr30 414) (nesr31 415) 2070 2071 (necr 416) 2072 2073 (gner0 432) (gner1 433) 2074 2075 (fner0 434) (fner1 435) 2076 2077 (epcr0 512) (epcr1 513) (epcr2 514) (epcr3 515) 2078 (epcr4 516) (epcr5 517) (epcr6 518) (epcr7 519) 2079 (epcr8 520) (epcr9 521) (epcr10 522) (epcr11 523) 2080 (epcr12 524) (epcr13 525) (epcr14 526) (epcr15 527) 2081 (epcr16 528) (epcr17 529) (epcr18 530) (epcr19 531) 2082 (epcr20 532) (epcr21 533) (epcr22 534) (epcr23 535) 2083 (epcr24 536) (epcr25 537) (epcr26 538) (epcr27 539) 2084 (epcr28 540) (epcr29 541) (epcr30 542) (epcr31 543) 2085 (epcr32 544) (epcr33 545) (epcr34 546) (epcr35 547) 2086 (epcr36 548) (epcr37 549) (epcr38 550) (epcr39 551) 2087 (epcr40 552) (epcr41 553) (epcr42 554) (epcr43 555) 2088 (epcr44 556) (epcr45 557) (epcr46 558) (epcr47 559) 2089 (epcr48 560) (epcr49 561) (epcr50 562) (epcr51 563) 2090 (epcr52 564) (epcr53 565) (epcr54 566) (epcr55 567) 2091 (epcr56 568) (epcr57 569) (epcr58 570) (epcr59 571) 2092 (epcr60 572) (epcr61 573) (epcr62 574) (epcr63 575) 2093 2094 (esr0 576) (esr1 577) (esr2 578) (esr3 579) 2095 (esr4 580) (esr5 581) (esr6 582) (esr7 583) 2096 (esr8 584) (esr9 585) (esr10 586) (esr11 587) 2097 (esr12 588) (esr13 589) (esr14 590) (esr15 591) 2098 (esr16 592) (esr17 593) (esr18 594) (esr19 595) 2099 (esr20 596) (esr21 597) (esr22 598) (esr23 599) 2100 (esr24 600) (esr25 601) (esr26 602) (esr27 603) 2101 (esr28 604) (esr29 605) (esr30 606) (esr31 607) 2102 (esr32 608) (esr33 609) (esr34 610) (esr35 611) 2103 (esr36 612) (esr37 613) (esr38 614) (esr39 615) 2104 (esr40 616) (esr41 617) (esr42 618) (esr43 619) 2105 (esr44 620) (esr45 621) (esr46 622) (esr47 623) 2106 (esr48 624) (esr49 625) (esr50 626) (esr51 627) 2107 (esr52 628) (esr53 629) (esr54 630) (esr55 631) 2108 (esr56 632) (esr57 633) (esr58 634) (esr59 635) 2109 (esr60 636) (esr61 637) (esr62 638) (esr63 639) 2110 2111 (eir0 640) (eir1 641) (eir2 642) (eir3 643) 2112 (eir4 644) (eir5 645) (eir6 646) (eir7 647) 2113 (eir8 648) (eir9 649) (eir10 650) (eir11 651) 2114 (eir12 652) (eir13 653) (eir14 654) (eir15 655) 2115 (eir16 656) (eir17 657) (eir18 658) (eir19 659) 2116 (eir20 660) (eir21 661) (eir22 662) (eir23 663) 2117 (eir24 664) (eir25 665) (eir26 666) (eir27 667) 2118 (eir28 668) (eir29 669) (eir30 670) (eir31 671) 2119 2120 (esfr0 672) (esfr1 673) 2121 2122 (sr0 768) (sr1 769) (sr2 770) (sr3 771) 2123 2124 (fsr0 1024) (fsr1 1025) (fsr2 1026) (fsr3 1027) 2125 (fsr4 1028) (fsr5 1029) (fsr6 1030) (fsr7 1031) 2126 (fsr8 1032) (fsr9 1033) (fsr10 1034) (fsr11 1035) 2127 (fsr12 1036) (fsr13 1037) (fsr14 1038) (fsr15 1039) 2128 (fsr16 1040) (fsr17 1041) (fsr18 1042) (fsr19 1043) 2129 (fsr20 1044) (fsr21 1045) (fsr22 1046) (fsr23 1047) 2130 (fsr24 1048) (fsr25 1049) (fsr26 1050) (fsr27 1051) 2131 (fsr28 1052) (fsr29 1053) (fsr30 1054) (fsr31 1055) 2132 (fsr32 1056) (fsr33 1057) (fsr34 1058) (fsr35 1059) 2133 (fsr36 1060) (fsr37 1061) (fsr38 1062) (fsr39 1063) 2134 (fsr40 1064) (fsr41 1065) (fsr42 1066) (fsr43 1067) 2135 (fsr44 1068) (fsr45 1069) (fsr46 1070) (fsr47 1071) 2136 (fsr48 1072) (fsr49 1073) (fsr50 1074) (fsr51 1075) 2137 (fsr52 1076) (fsr53 1077) (fsr54 1078) (fsr55 1079) 2138 (fsr56 1080) (fsr57 1081) (fsr58 1082) (fsr59 1083) 2139 (fsr60 1084) (fsr61 1085) (fsr62 1086) (fsr63 1087) 2140 2141 ; FQ0-FQ31 are 64 bit registers. 2142 ; These names allow access to the upper 32 bits of the FQ registers. 2143 (fqop0 1088) (fqop1 1090) (fqop2 1092) (fqop3 1094) 2144 (fqop4 1096) (fqop5 1098) (fqop6 1100) (fqop7 1102) 2145 (fqop8 1104) (fqop9 1106) (fqop10 1108) (fqop11 1110) 2146 (fqop12 1112) (fqop13 1114) (fqop14 1116) (fqop15 1118) 2147 (fqop16 1120) (fqop17 1122) (fqop18 1124) (fqop19 1126) 2148 (fqop20 1128) (fqop21 1130) (fqop22 1132) (fqop23 1134) 2149 (fqop24 1136) (fqop25 1138) (fqop26 1140) (fqop27 1142) 2150 (fqop28 1144) (fqop29 1146) (fqop30 1148) (fqop31 1150) 2151 ; These names allow access to the lower 32 bits of the FQ registers. 2152 (fqst0 1089) (fqst1 1091) (fqst2 1093) (fqst3 1095) 2153 (fqst4 1097) (fqst5 1099) (fqst6 1101) (fqst7 1103) 2154 (fqst8 1105) (fqst9 1107) (fqst10 1109) (fqst11 1111) 2155 (fqst12 1113) (fqst13 1115) (fqst14 1117) (fqst15 1119) 2156 (fqst16 1121) (fqst17 1123) (fqst18 1125) (fqst19 1127) 2157 (fqst20 1129) (fqst21 1131) (fqst22 1133) (fqst23 1135) 2158 (fqst24 1137) (fqst25 1139) (fqst26 1141) (fqst27 1143) 2159 (fqst28 1145) (fqst29 1147) (fqst30 1149) (fqst31 1151) 2160 ; These also access the lower 32 bits of the FQ registers. 2161 ; These are not accessible as spr registers (see LSI appendix - section 13.4) 2162; (fq0 1089) (fq1 1091) (fq2 1093) (fq3 1095) 2163; (fq4 1097) (fq5 1099) (fq6 1101) (fq7 1103) 2164; (fq8 1105) (fq9 1107) (fq10 1109) (fq11 1111) 2165; (fq12 1113) (fq13 1115) (fq14 1117) (fq15 1119) 2166; (fq16 1121) (fq17 1123) (fq18 1125) (fq19 1127) 2167; (fq20 1129) (fq21 1131) (fq22 1133) (fq23 1135) 2168; (fq24 1137) (fq25 1139) (fq26 1141) (fq27 1143) 2169; (fq28 1145) (fq29 1147) (fq30 1149) (fq31 1151) 2170 2171 (mcilr0 1272) (mcilr1 1273) 2172 2173 (msr0 1280) (msr1 1281) (msr2 1282) (msr3 1283) 2174 (msr4 1284) (msr5 1285) (msr6 1286) (msr7 1287) 2175 (msr8 1288) (msr9 1289) (msr10 1290) (msr11 1291) 2176 (msr12 1292) (msr13 1293) (msr14 1294) (msr15 1295) 2177 (msr16 1296) (msr17 1297) (msr18 1298) (msr19 1299) 2178 (msr20 1300) (msr21 1301) (msr22 1302) (msr23 1303) 2179 (msr24 1304) (msr25 1305) (msr26 1306) (msr27 1307) 2180 (msr28 1308) (msr29 1309) (msr30 1310) (msr31 1311) 2181 (msr32 1312) (msr33 1313) (msr34 1314) (msr35 1315) 2182 (msr36 1316) (msr37 1317) (msr38 1318) (msr39 1319) 2183 (msr40 1320) (msr41 1321) (msr42 1322) (msr43 1323) 2184 (msr44 1324) (msr45 1325) (msr46 1326) (msr47 1327) 2185 (msr48 1328) (msr49 1329) (msr50 1330) (msr51 1331) 2186 (msr52 1332) (msr53 1333) (msr54 1334) (msr55 1335) 2187 (msr56 1336) (msr57 1337) (msr58 1338) (msr59 1339) 2188 (msr60 1340) (msr61 1341) (msr62 1342) (msr63 1343) 2189 2190 ; MQ0-MQ31 are 64 bit registers. 2191 ; These names allow access to the upper 32 bits of the MQ registers. 2192 (mqop0 1344) (mqop1 1346) (mqop2 1348) (mqop3 1350) 2193 (mqop4 1352) (mqop5 1354) (mqop6 1356) (mqop7 1358) 2194 (mqop8 1360) (mqop9 1362) (mqop10 1364) (mqop11 1366) 2195 (mqop12 1368) (mqop13 1370) (mqop14 1372) (mqop15 1374) 2196 (mqop16 1376) (mqop17 1378) (mqop18 1380) (mqop19 1382) 2197 (mqop20 1384) (mqop21 1386) (mqop22 1388) (mqop23 1390) 2198 (mqop24 1392) (mqop25 1394) (mqop26 1396) (mqop27 1398) 2199 (mqop28 1400) (mqop29 1402) (mqop30 1404) (mqop31 1406) 2200 ; These names allow access to the lower 32 bits of the MQ registers. 2201 (mqst0 1345) (mqst1 1347) (mqst2 1349) (mqst3 1351) 2202 (mqst4 1353) (mqst5 1355) (mqst6 1357) (mqst7 1359) 2203 (mqst8 1361) (mqst9 1363) (mqst10 1365) (mqst11 1367) 2204 (mqst12 1369) (mqst13 1371) (mqst14 1373) (mqst15 1375) 2205 (mqst16 1377) (mqst17 1379) (mqst18 1381) (mqst19 1383) 2206 (mqst20 1385) (mqst21 1387) (mqst22 1389) (mqst23 1391) 2207 (mqst24 1393) (mqst25 1395) (mqst26 1397) (mqst27 1399) 2208 (mqst28 1401) (mqst29 1403) (mqst30 1405) (mqst31 1407) 2209 ; These also access the lower 32 bits of the MQ registers. 2210 ; These are not accessible as spr registers (see LSI appendix - section 13.4) 2211; (mq0 1345) (mq1 1347) (mq2 1349) (mq3 1351) 2212; (mq4 1353) (mq5 1355) (mq6 1357) (mq7 1359) 2213; (mq8 1361) (mq9 1363) (mq10 1365) (mq11 1367) 2214; (mq12 1369) (mq13 1371) (mq14 1373) (mq15 1375) 2215; (mq16 1377) (mq17 1379) (mq18 1381) (mq19 1383) 2216; (mq20 1385) (mq21 1387) (mq22 1389) (mq23 1391) 2217; (mq24 1393) (mq25 1395) (mq26 1397) (mq27 1399) 2218; (mq28 1401) (mq29 1403) (mq30 1405) (mq31 1407) 2219 2220 ; These are not accessible as spr registers (see LSI appendix - section 13.4) 2221; (acc0 1408) (acc1 1409) (acc2 1410) (acc3 1411) 2222; (acc4 1412) (acc5 1413) (acc6 1414) (acc7 1415) 2223; (acc8 1416) (acc9 1417) (acc10 1418) (acc11 1419) 2224; (acc12 1420) (acc13 1421) (acc14 1422) (acc15 1423) 2225; (acc16 1424) (acc17 1425) (acc18 1426) (acc19 1427) 2226; (acc20 1428) (acc21 1429) (acc22 1430) (acc23 1431) 2227; (acc24 1432) (acc25 1433) (acc26 1434) (acc27 1435) 2228; (acc28 1436) (acc29 1437) (acc30 1438) (acc31 1439) 2229; (acc32 1440) (acc33 1441) (acc34 1442) (acc35 1443) 2230; (acc36 1444) (acc37 1445) (acc38 1446) (acc39 1447) 2231; (acc40 1448) (acc41 1449) (acc42 1450) (acc43 1451) 2232; (acc44 1452) (acc45 1453) (acc46 1454) (acc47 1455) 2233; (acc48 1456) (acc49 1457) (acc50 1458) (acc51 1459) 2234; (acc52 1460) (acc53 1461) (acc54 1462) (acc55 1463) 2235; (acc56 1464) (acc57 1465) (acc58 1466) (acc59 1467) 2236; (acc60 1468) (acc61 1469) (acc62 1470) (acc63 1471) 2237 2238; (accg0 1472) (accg1 1473) (accg2 1474) (accg3 1475) 2239; (accg4 1476) (accg5 1477) (accg6 1478) (accg7 1479) 2240; (accg8 1480) (accg9 1481) (accg10 1482) (accg11 1483) 2241; (accg12 1484) (accg13 1485) (accg14 1486) (accg15 1487) 2242; (accg16 1488) (accg17 1489) (accg18 1490) (accg19 1491) 2243; (accg20 1492) (accg21 1493) (accg22 1494) (accg23 1495) 2244; (accg24 1496) (accg25 1497) (accg26 1498) (accg27 1499) 2245; (accg28 1500) (accg29 1501) (accg30 1502) (accg31 1503) 2246; (accg32 1504) (accg33 1505) (accg34 1506) (accg35 1507) 2247; (accg36 1508) (accg37 1509) (accg38 1510) (accg39 1511) 2248; (accg40 1512) (accg41 1513) (accg42 1514) (accg43 1515) 2249; (accg44 1516) (accg45 1517) (accg46 1518) (accg47 1519) 2250; (accg48 1520) (accg49 1521) (accg50 1522) (accg51 1523) 2251; (accg52 1524) (accg53 1525) (accg54 1526) (accg55 1527) 2252; (accg56 1528) (accg57 1529) (accg58 1530) (accg59 1531) 2253; (accg60 1532) (accg61 1533) (accg62 1534) (accg63 1535) 2254 2255 (ear0 1536) (ear1 1537) (ear2 1538) (ear3 1539) 2256 (ear4 1540) (ear5 1541) (ear6 1542) (ear7 1543) 2257 (ear8 1544) (ear9 1545) (ear10 1546) (ear11 1547) 2258 (ear12 1548) (ear13 1549) (ear14 1550) (ear15 1551) 2259 (ear16 1552) (ear17 1553) (ear18 1554) (ear19 1555) 2260 (ear20 1556) (ear21 1557) (ear22 1558) (ear23 1559) 2261 (ear24 1560) (ear25 1561) (ear26 1562) (ear27 1563) 2262 (ear28 1564) (ear29 1565) (ear30 1566) (ear31 1567) 2263 (ear32 1568) (ear33 1569) (ear34 1570) (ear35 1571) 2264 (ear36 1572) (ear37 1573) (ear38 1574) (ear39 1575) 2265 (ear40 1576) (ear41 1577) (ear42 1578) (ear43 1579) 2266 (ear44 1580) (ear45 1581) (ear46 1582) (ear47 1583) 2267 (ear48 1584) (ear49 1585) (ear50 1586) (ear51 1587) 2268 (ear52 1588) (ear53 1589) (ear54 1590) (ear55 1591) 2269 (ear56 1592) (ear57 1593) (ear58 1594) (ear59 1595) 2270 (ear60 1596) (ear61 1597) (ear62 1598) (ear63 1599) 2271 2272 (edr0 1600) (edr1 1601) (edr2 1602) (edr3 1603) 2273 (edr4 1604) (edr5 1605) (edr6 1606) (edr7 1607) 2274 (edr8 1608) (edr9 1609) (edr10 1610) (edr11 1611) 2275 (edr12 1612) (edr13 1613) (edr14 1614) (edr15 1615) 2276 (edr16 1616) (edr17 1617) (edr18 1618) (edr19 1619) 2277 (edr20 1620) (edr21 1621) (edr22 1622) (edr23 1623) 2278 (edr24 1624) (edr25 1625) (edr26 1626) (edr27 1627) 2279 (edr28 1628) (edr29 1629) (edr30 1630) (edr31 1631) 2280 (edr32 1632) (edr33 1636) (edr34 1634) (edr35 1635) 2281 (edr36 1636) (edr37 1637) (edr38 1638) (edr39 1639) 2282 (edr40 1640) (edr41 1641) (edr42 1642) (edr43 1643) 2283 (edr44 1644) (edr45 1645) (edr46 1646) (edr47 1647) 2284 (edr48 1648) (edr49 1649) (edr50 1650) (edr51 1651) 2285 (edr52 1652) (edr53 1653) (edr54 1654) (edr55 1655) 2286 (edr56 1656) (edr57 1657) (edr58 1658) (edr59 1659) 2287 (edr60 1660) (edr61 1661) (edr62 1662) (edr63 1663) 2288 2289 (iamlr0 1664) (iamlr1 1665) (iamlr2 1666) (iamlr3 1667) 2290 (iamlr4 1668) (iamlr5 1669) (iamlr6 1670) (iamlr7 1671) 2291 (iamlr8 1672) (iamlr9 1673) (iamlr10 1674) (iamlr11 1675) 2292 (iamlr12 1676) (iamlr13 1677) (iamlr14 1678) (iamlr15 1679) 2293 (iamlr16 1680) (iamlr17 1681) (iamlr18 1682) (iamlr19 1683) 2294 (iamlr20 1684) (iamlr21 1685) (iamlr22 1686) (iamlr23 1687) 2295 (iamlr24 1688) (iamlr25 1689) (iamlr26 1690) (iamlr27 1691) 2296 (iamlr28 1692) (iamlr29 1693) (iamlr30 1694) (iamlr31 1695) 2297 (iamlr32 1696) (iamlr33 1697) (iamlr34 1698) (iamlr35 1699) 2298 (iamlr36 1700) (iamlr37 1701) (iamlr38 1702) (iamlr39 1703) 2299 (iamlr40 1704) (iamlr41 1705) (iamlr42 1706) (iamlr43 1707) 2300 (iamlr44 1708) (iamlr45 1709) (iamlr46 1710) (iamlr47 1711) 2301 (iamlr48 1712) (iamlr49 1713) (iamlr50 1714) (iamlr51 1715) 2302 (iamlr52 1716) (iamlr53 1717) (iamlr54 1718) (iamlr55 1719) 2303 (iamlr56 1720) (iamlr57 1721) (iamlr58 1722) (iamlr59 1723) 2304 (iamlr60 1724) (iamlr61 1725) (iamlr62 1726) (iamlr63 1727) 2305 2306 (iampr0 1728) (iampr1 1729) (iampr2 1730) (iampr3 1731) 2307 (iampr4 1732) (iampr5 1733) (iampr6 1734) (iampr7 1735) 2308 (iampr8 1736) (iampr9 1737) (iampr10 1738) (iampr11 1739) 2309 (iampr12 1740) (iampr13 1741) (iampr14 1742) (iampr15 1743) 2310 (iampr16 1744) (iampr17 1745) (iampr18 1746) (iampr19 1747) 2311 (iampr20 1748) (iampr21 1749) (iampr22 1750) (iampr23 1751) 2312 (iampr24 1752) (iampr25 1753) (iampr26 1754) (iampr27 1755) 2313 (iampr28 1756) (iampr29 1757) (iampr30 1758) (iampr31 1759) 2314 (iampr32 1760) (iampr33 1761) (iampr34 1762) (iampr35 1763) 2315 (iampr36 1764) (iampr37 1765) (iampr38 1766) (iampr39 1767) 2316 (iampr40 1768) (iampr41 1769) (iampr42 1770) (iampr43 1771) 2317 (iampr44 1772) (iampr45 1773) (iampr46 1774) (iampr47 1775) 2318 (iampr48 1776) (iampr49 1777) (iampr50 1778) (iampr51 1779) 2319 (iampr52 1780) (iampr53 1781) (iampr54 1782) (iampr55 1783) 2320 (iampr56 1784) (iampr57 1785) (iampr58 1786) (iampr59 1787) 2321 (iampr60 1788) (iampr61 1789) (iampr62 1790) (iampr63 1791) 2322 2323 (damlr0 1792) (damlr1 1793) (damlr2 1794) (damlr3 1795) 2324 (damlr4 1796) (damlr5 1797) (damlr6 1798) (damlr7 1799) 2325 (damlr8 1800) (damlr9 1801) (damlr10 1802) (damlr11 1803) 2326 (damlr12 1804) (damlr13 1805) (damlr14 1806) (damlr15 1807) 2327 (damlr16 1808) (damlr17 1809) (damlr18 1810) (damlr19 1811) 2328 (damlr20 1812) (damlr21 1813) (damlr22 1814) (damlr23 1815) 2329 (damlr24 1816) (damlr25 1817) (damlr26 1818) (damlr27 1819) 2330 (damlr28 1820) (damlr29 1821) (damlr30 1822) (damlr31 1823) 2331 (damlr32 1824) (damlr33 1825) (damlr34 1826) (damlr35 1827) 2332 (damlr36 1828) (damlr37 1829) (damlr38 1830) (damlr39 1831) 2333 (damlr40 1832) (damlr41 1833) (damlr42 1834) (damlr43 1835) 2334 (damlr44 1836) (damlr45 1837) (damlr46 1838) (damlr47 1839) 2335 (damlr48 1840) (damlr49 1841) (damlr50 1842) (damlr51 1843) 2336 (damlr52 1844) (damlr53 1845) (damlr54 1846) (damlr55 1847) 2337 (damlr56 1848) (damlr57 1849) (damlr58 1850) (damlr59 1851) 2338 (damlr60 1852) (damlr61 1853) (damlr62 1854) (damlr63 1855) 2339 2340 (dampr0 1856) (dampr1 1857) (dampr2 1858) (dampr3 1859) 2341 (dampr4 1860) (dampr5 1861) (dampr6 1862) (dampr7 1863) 2342 (dampr8 1864) (dampr9 1865) (dampr10 1866) (dampr11 1867) 2343 (dampr12 1868) (dampr13 1869) (dampr14 1870) (dampr15 1871) 2344 (dampr16 1872) (dampr17 1873) (dampr18 1874) (dampr19 1875) 2345 (dampr20 1876) (dampr21 1877) (dampr22 1878) (dampr23 1879) 2346 (dampr24 1880) (dampr25 1881) (dampr26 1882) (dampr27 1883) 2347 (dampr28 1884) (dampr29 1885) (dampr30 1886) (dampr31 1887) 2348 (dampr32 1888) (dampr33 1889) (dampr34 1890) (dampr35 1891) 2349 (dampr36 1892) (dampr37 1893) (dampr38 1894) (dampr39 1895) 2350 (dampr40 1896) (dampr41 1897) (dampr42 1898) (dampr43 1899) 2351 (dampr44 1900) (dampr45 1901) (dampr46 1902) (dampr47 1903) 2352 (dampr48 1904) (dampr49 1905) (dampr50 1906) (dampr51 1907) 2353 (dampr52 1908) (dampr53 1909) (dampr54 1910) (dampr55 1911) 2354 (dampr56 1912) (dampr57 1913) (dampr58 1914) (dampr59 1915) 2355 (dampr60 1916) (dampr61 1917) (dampr62 1918) (dampr63 1919) 2356 2357 (amcr 1920) (stbar 1921) (mmcr 1922) 2358 (dcr 2048) (brr 2049) (nmar 2050) 2359 2360 (ibar0 2052) (ibar1 2053) (ibar2 2054) (ibar3 2055) 2361 (dbar0 2056) (dbar1 2057) (dbar2 2058) (dbar3 2059) 2362 2363 (dbdr00 2060) (dbdr01 2061) (dbdr02 2062) (dbdr03 2063) 2364 (dbdr10 2064) (dbdr11 2065) (dbdr12 2066) (dbdr13 2067) 2365 (dbdr20 2068) (dbdr21 2069) (dbdr22 2070) (dbdr23 2071) 2366 (dbdr30 2072) (dbdr31 2073) (dbdr32 2074) (dbdr33 2075) 2367 2368 (dbmr00 2076) (dbmr01 2077) (dbmr02 2078) (dbmr03 2079) 2369 (dbmr10 2080) (dbmr11 2081) (dbmr12 2082) (dbmr13 2083) 2370 (dbmr20 2084) (dbmr21 2085) (dbmr22 2086) (dbmr23 2087) 2371 (dbmr30 2088) (dbmr31 2089) (dbmr32 2090) (dbmr33 2091) 2372 2373 (cpcfr 2092) (cpcr 2093) (cpsr 2094) 2374 2375 (cpesr0 2096) (cpesr1 2097) 2376 (cpemr0 2098) (cpemr1 2099) 2377 2378 (ihsr8 3848) 2379 ) 2380) 2381 2382(define-hardware 2383 (name h-spr) 2384 (comment "special purpose registers") 2385 (attrs PROFILE) 2386 (type register UWI (4096)) 2387 (indices extern-keyword spr-names) 2388 (get (index) (c-call UWI "@cpu@_h_spr_get_handler" index)) 2389 (set (index newval) (c-call VOID "@cpu@_h_spr_set_handler" index newval)) 2390) 2391 2392(define-pmacro (spr-pcsr) (reg h-spr 1)) 2393(define-pmacro (spr-bpcsr) (reg h-spr 2)) 2394(define-pmacro (spr-lr) (reg h-spr 272)) 2395(define-pmacro (spr-lcr) (reg h-spr 273)) 2396(define-pmacro (spr-iacc0h) (reg h-spr 280)) 2397(define-pmacro (spr-iacc0l) (reg h-spr 281)) 2398(define-pmacro (spr-sr0) (reg h-spr 768)) 2399(define-pmacro (spr-sr1) (reg h-spr 769)) 2400(define-pmacro (spr-sr2) (reg h-spr 770)) 2401(define-pmacro (spr-sr3) (reg h-spr 771)) 2402 2403; Accumulator guard. Actually a subset of the SPR registers, but those SPRs 2404; are read-only in most insns. This hardware element is used by those insns 2405; which have direct access (mwtaccg, mrdaccg). 2406(define-keyword 2407 (name accg-names) 2408 (print-name h-accg) 2409 (prefix "") 2410 (values 2411 (accg0 0)(accg1 1)(accg2 2)(accg3 3) 2412 (accg4 4)(accg5 5)(accg6 6)(accg7 7) 2413 (accg8 8)(accg9 9)(accg10 10)(accg11 11) 2414 (accg12 12)(accg13 13)(accg14 14)(accg15 15) 2415 (accg16 16)(accg17 17)(accg18 18)(accg19 19) 2416 (accg20 20)(accg21 21)(accg22 22)(accg23 23) 2417 (accg24 24)(accg25 25)(accg26 26)(accg27 27) 2418 (accg28 28)(accg29 29)(accg30 30)(accg31 31) 2419 (accg32 32)(accg33 33)(accg34 34)(accg35 35) 2420 (accg36 36)(accg37 37)(accg38 38)(accg39 39) 2421 (accg40 40)(accg41 41)(accg42 42)(accg43 43) 2422 (accg44 44)(accg45 45)(accg46 46)(accg47 47) 2423 (accg48 48)(accg49 49)(accg50 50)(accg51 51) 2424 (accg52 52)(accg53 53)(accg54 54)(accg55 55) 2425 (accg56 56)(accg57 57)(accg58 58)(accg59 59) 2426 (accg60 60)(accg61 61)(accg62 62)(accg63 63) 2427 ) 2428) 2429 2430(define-hardware 2431 (name h-accg) 2432 (comment "accumulator guard") 2433 (attrs PROFILE VIRTUAL) 2434 (type register UWI (64)) 2435 (indices extern-keyword accg-names) 2436 (get (index) 2437 (and (reg h-spr (add index 1472)) #xff)) 2438 (set (index newval) 2439 (set (raw-reg UWI h-spr (add index 1472)) (and newval #xff))) 2440) 2441 2442; 40 bit accumulator. Composed of ACCG and ACC registers concatenated, but 2443; referenced more often as the composed 40 bits. 2444(define-keyword 2445 (name acc-names) 2446 (print-name h-acc40) 2447 (prefix "") 2448 (values 2449(acc0 0)(acc1 1)(acc2 2)(acc3 3)(acc4 4)(acc5 5)(acc6 6)(acc7 7) 2450(acc8 8)(acc9 9)(acc10 10)(acc11 11)(acc12 12)(acc13 13)(acc14 14)(acc15 15) 2451(acc16 16)(acc17 17)(acc18 18)(acc19 19)(acc20 20)(acc21 21)(acc22 22)(acc23 23) 2452(acc24 24)(acc25 25)(acc26 26)(acc27 27)(acc28 28)(acc29 29)(acc30 30)(acc31 31) 2453(acc32 32)(acc33 33)(acc34 34)(acc35 35)(acc36 36)(acc37 37)(acc38 38)(acc39 39) 2454(acc40 40)(acc41 41)(acc42 42)(acc43 43)(acc44 44)(acc45 45)(acc46 46)(acc47 47) 2455(acc48 48)(acc49 49)(acc50 50)(acc51 51)(acc52 52)(acc53 53)(acc54 54)(acc55 55) 2456(acc56 56)(acc57 57)(acc58 58)(acc59 59)(acc60 60)(acc61 61)(acc62 62)(acc63 63) 2457 ) 2458) 2459 2460(define-hardware 2461 (name h-acc40S) 2462 (comment "40 bit signed accumulator") 2463 (attrs PROFILE VIRTUAL) 2464 (type register DI (64)) 2465 (indices extern-keyword acc-names) 2466 ; The accumlator is made up of two 32 bit registers, accgi/acci. 2467 ; We want to extract this as a combined 40 signed bits 2468 (get (index) 2469 (or DI 2470 (sll DI (ext DI (trunc QI (reg h-spr (add index 1472)))) 2471 32) 2472 (zext DI (reg h-spr (add index 1408))))) 2473 ; Bits 40-63 are not written. raw-reg is used to bypass read-only restrictions 2474 ; on ACC and ACCG registers 2475 (set (index newval) 2476 (sequence () 2477 (c-call VOID "frv_check_spr_write_access" (add index 1408)) 2478 (set (raw-reg UWI h-spr 2479 (add index 1472)) (and (srl newval 32) #xff)) 2480 (set (raw-reg UWI h-spr 2481 (add index 1408)) (trunc USI newval)))) 2482) 2483 2484(define-hardware 2485 (name h-acc40U) 2486 (comment "40 bit unsigned accumulator") 2487 (attrs PROFILE VIRTUAL) 2488 (type register UDI (64)) 2489 (indices extern-keyword acc-names) 2490 ; The accumlator is made up of two 32 bit registers, accgi/acci. 2491 ; We want to extract this as a combined 40 unsigned bits 2492 (get (index) 2493 (or DI 2494 (sll DI (zext DI (reg h-spr (add index 1472))) 32) 2495 (zext DI (reg h-spr (add index 1408))))) 2496 ; Bits 40-63 are not written. raw-reg is used to bypass read-only restrictions 2497 ; on ACC and ACCG registers 2498 (set (index newval) 2499 (sequence () 2500 (c-call VOID "frv_check_spr_write_access" (add index 1408)) 2501 (set (raw-reg UWI h-spr 2502 (add index 1472)) (and (srl newval 32) #xff)) 2503 (set (raw-reg UWI h-spr 2504 (add index 1408)) (trunc USI newval)))) 2505) 2506; 64-bit signed accumulator. Composed of iacc0h and iacc0l registers 2507; concatenated, but referenced more often as the composed 64 bits. 2508(define-keyword 2509 ; This is totally hokey -- I have to have an index! 2510 (name iacc0-names) 2511 (print-name h-iacc0) 2512 (prefix "") 2513 (values (iacc0 0)) 2514) 2515 2516(define-hardware 2517 (name h-iacc0) 2518 (comment "64 bit signed accumulator") 2519 (attrs PROFILE VIRTUAL (MACH fr400)) 2520 (type register DI (1)) 2521 (indices extern-keyword iacc0-names) 2522 ; The single 64-bit integer accumulator is made up of two 32 bit 2523 ; registers, iacc0h and iacc0l. We want to extract this as a 2524 ; combined 64 signed bits. 2525 (get (idx) (or DI (sll DI (ext DI (spr-iacc0h)) 32) (zext DI (spr-iacc0l)))) 2526 (set (idx newval) 2527 (sequence () 2528 (set (spr-iacc0h) (trunc SI (srl newval 32))) 2529 (set (spr-iacc0l) (trunc SI newval)))) 2530) 2531 2532; Integer condition code registers (CCR) 2533; 2534; The individual sub registers bits of the CCR are referenced more often than 2535; the entire register so set them directly. We can assemble the 2536; entire register when necessary. 2537; 2538(define-keyword 2539 (name iccr-names) 2540 (print-name h-iccr) 2541 (prefix "") 2542 (values (icc0 0) (icc1 1) (icc2 2) (icc3 3)) 2543) 2544 2545(define-hardware 2546 (name h-iccr) 2547 (comment "Integer condition code registers") 2548 (attrs PROFILE) 2549 (type register UQI (4)) 2550 (indices extern-keyword iccr-names) 2551) 2552 2553; Floating point condition code registers (CCR) 2554; 2555; The individual sub registers bits of the CCR are referenced more often than 2556; the entire register so set them directly. We can assemble the 2557; entire register when necessary. 2558; 2559(define-keyword 2560 (name fccr-names) 2561 (print-name h-fccr) 2562 (prefix "") 2563 (values (fcc0 0) (fcc1 1) (fcc2 2) (fcc3 3)) 2564) 2565 2566(define-hardware 2567 (name h-fccr) 2568 (comment "Floating point condition code registers") 2569 (attrs PROFILE) 2570 (type register UQI (4)) 2571 (indices extern-keyword fccr-names) 2572) 2573 2574; C condition code registers (CCCR) 2575; 2576(define-keyword 2577 (name cccr-names) 2578 (print-name h-cccr) 2579 (prefix "") 2580 (values (cc0 0) (cc1 1) (cc2 2) (cc3 3) (cc4 4) (cc5 5) (cc6 6) (cc7 7)) 2581) 2582 2583(define-hardware 2584 (name h-cccr) 2585 (comment "Condition code registers") 2586 (attrs PROFILE) 2587 (type register UQI (8)) 2588 (indices extern-keyword cccr-names) 2589) 2590 2591; Dummy hardware used to define packing bit on insns 2592; 2593(define-hardware 2594 (name h-pack) 2595 (comment "Packing bit dummy hardware") 2596 (type immediate (UINT 1)) 2597 (values keyword "" (("" 1) (".p" 0) (".P" 0))) 2598) 2599; Dummy hardware used to define hint field for branches always taken 2600; 2601(define-hardware 2602 (name h-hint-taken) 2603 (comment "Branch taken hint dummy hardware") 2604 (type immediate (UINT 1)) 2605 ; The order of these is important. We want '2' to get written by default, 2606 ; but we also want the docoder/disassembler to allow the values '0', '1' and 2607 ; '3'. 2608 (values keyword "" (("" 2) ("" 0) ("" 1) ("" 3))) 2609) 2610; Dummy hardware used to define hint field for branches never taken 2611; 2612(define-hardware 2613 (name h-hint-not-taken) 2614 (comment "Branch not taken hint dummy hardware") 2615 (type immediate (UINT 1)) 2616 ; The order of these is important. We want '0' to get written by default, 2617 ; but we also want the docoder/disassembler to allow the values '1', '2' and 2618 ; '3'. 2619 (values keyword "" (("" 0) ("" 1) ("" 2) ("" 3))) 2620) 2621 2622; Instruction Operands. 2623; These entries provide a layer between the assembler and the raw hardware 2624; description, and are used to refer to hardware elements in the semantic 2625; code. Usually there's a bit of over-specification, but in more complicated 2626; instruction sets there isn't. 2627 2628; FRV specific operand attributes: 2629 2630(define-attr 2631 (for operand) 2632 (type boolean) 2633 (name HASH-PREFIX) 2634 (comment "immediates have an optional '#' prefix") 2635) 2636 2637; ??? Convention says this should be o-sr, but then the insn definitions 2638; should refer to o-sr which is clumsy. The "o-" could be implicit, but 2639; then it should be implicit for all the symbols here, but then there would 2640; be confusion between (f-)simm8 and (h-)simm8. 2641; So for now the rule is exactly as it appears here. 2642 2643; dnmop: define-normal-mode-operand: temporary, pending potential removal 2644; of modes from h/w. 2645(define-pmacro (dnmop xname xcomment xattrs xtype xindex xmode) 2646 (define-operand 2647 (name xname) 2648 (comment xcomment) 2649 (.splice attrs (.unsplice xattrs)) 2650 (type xtype) 2651 (index xindex) 2652 (mode xmode) 2653 ) 2654) 2655 2656; dnpmop: define-normal-parsed-mode-operand: Normal mode operand with parse handler 2657(define-pmacro (dnpmop xname xcomment xattrs xtype xindex xmode xparse) 2658 (define-operand 2659 (name xname) 2660 (comment xcomment) 2661 (.splice attrs (.unsplice xattrs)) 2662 (type xtype) 2663 (index xindex) 2664 (mode xmode) 2665 (handlers (parse xparse)) 2666 ) 2667) 2668 2669(dnop pack "packing bit" () h-pack f-pack) 2670 2671(dnmop GRi "source register 1" () h-gr f-GRi SI) 2672(dnmop GRj "source register 2" () h-gr f-GRj SI) 2673(dnmop GRk "destination register" () h-gr f-GRk SI) 2674(dnmop GRkhi "destination register" () h-gr_hi f-GRk UHI) 2675(dnmop GRklo "destination register" () h-gr_lo f-GRk UHI) 2676(dnpmop GRdoublek "destination register" () h-gr_double f-GRk DI "even_register") 2677(dnmop ACC40Si "signed accumulator" () h-acc40S f-ACC40Si DI) 2678(dnmop ACC40Ui "unsigned accumulator" () h-acc40U f-ACC40Ui UDI) 2679(dnmop ACC40Sk "target accumulator" () h-acc40S f-ACC40Sk DI) 2680(dnmop ACC40Uk "target accumulator" () h-acc40U f-ACC40Uk UDI) 2681(dnmop ACCGi "source register" () h-accg f-ACCGi UWI) 2682(dnmop ACCGk "target register" () h-accg f-ACCGk UWI) 2683 2684(dnmop CPRi "source register" ((MACH frv)) h-cpr f-CPRi SI) 2685(dnmop CPRj "source register" ((MACH frv)) h-cpr f-CPRj SI) 2686(dnmop CPRk "destination register" ((MACH frv)) h-cpr f-CPRk SI) 2687(dnpmop CPRdoublek "destination register" ((MACH frv)) h-cpr_double f-CPRk DI "even_register") 2688 2689; floating point operands 2690(dnmop FRinti "source register 1" () h-fr_int f-FRi SI) 2691(dnmop FRintj "source register 2" () h-fr_int f-FRj SI) 2692(dnmop FRintk "target register" () h-fr_int f-FRk SI) 2693(dnmop FRi "source register 1" () h-fr f-FRi SF) 2694(dnmop FRj "source register 2" () h-fr f-FRj SF) 2695(dnmop FRk "destination register" () h-fr f-FRk SF) 2696(dnmop FRkhi "destination register" () h-fr_hi f-FRk UHI) 2697(dnmop FRklo "destination register" () h-fr_lo f-FRk UHI) 2698(dnpmop FRdoublei "source register 1" () h-fr_double f-FRi DF "even_register") 2699(dnpmop FRdoublej "source register 2" () h-fr_double f-FRj DF "even_register") 2700(dnpmop FRdoublek "target register" () h-fr_double f-FRk DF "even_register") 2701 2702(dnop CRi "source register 1" () h-cccr f-CRi) 2703(dnop CRj "source register 2" () h-cccr f-CRj) 2704(dnop CRj_int "destination register" () h-cccr f-CRj_int) 2705(dnop CRj_float "destination register" () h-cccr f-CRj_float) 2706(dnop CRk "destination register" () h-cccr f-CRk) 2707(dnop CCi "condition register" () h-cccr f-CCi) 2708 2709(dnop ICCi_1 "condition register" () h-iccr f-ICCi_1) 2710(dnop ICCi_2 "condition register" () h-iccr f-ICCi_2) 2711(dnop ICCi_3 "condition register" () h-iccr f-ICCi_3) 2712(dnop FCCi_1 "condition register" () h-fccr f-FCCi_1) 2713(dnop FCCi_2 "condition register" () h-fccr f-FCCi_2) 2714(dnop FCCi_3 "condition register" () h-fccr f-FCCi_3) 2715(dnop FCCk "condition register" () h-fccr f-FCCk) 2716 2717(dnop eir "exception insn reg" () h-uint f-eir) 2718(dnop s10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-s10) 2719(dnop u16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-u16) 2720(dnop s16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-s16) 2721(dnop s6 "6 bit signed immediate" (HASH-PREFIX) h-sint f-s6) 2722(dnop s6_1 "6 bit signed immediate" (HASH-PREFIX) h-sint f-s6_1) 2723(dnop u6 "6 bit unsigned immediate" (HASH-PREFIX) h-uint f-u6) 2724(dnop s5 "5 bit signed immediate" (HASH-PREFIX) h-sint f-s5) 2725(dnop cond "conditional arithmetic" (HASH-PREFIX) h-uint f-cond) 2726(dnop ccond "lr branch condition" (HASH-PREFIX) h-uint f-ccond) 2727(dnop hint "2 bit branch predictor" (HASH-PREFIX) h-uint f-hint) 2728(dnop hint_taken "2 bit branch predictor" () h-hint-taken f-hint) 2729(dnop hint_not_taken "2 bit branch predictor" () h-hint-not-taken f-hint) 2730 2731(dnop LI "link indicator" () h-uint f-LI) 2732(dnop lock "cache lock indicator" (HASH-PREFIX) h-uint f-lock) 2733(dnop debug "debug mode indicator" (HASH-PREFIX) h-uint f-debug) 2734(dnop ae "all entries indicator" (HASH-PREFIX) h-uint f-ae) 2735 2736(dnop label16 "18 bit pc relative address" () h-iaddr f-label16) 2737(dnop label24 "26 bit pc relative address" () h-iaddr f-label24) 2738 2739(define-operand 2740 (name A0) 2741 (comment "A==0 operand of mclracc") 2742 (attrs) 2743 (type h-uint) 2744 (index f-A) 2745 (mode USI) 2746 (handlers (parse "A0")) 2747) 2748 2749(define-operand 2750 (name A1) 2751 (comment "A==1 operand of mclracc") 2752 (attrs) 2753 (type h-uint) 2754 (index f-A) 2755 (mode USI) 2756 (handlers (parse "A1")) 2757) 2758 2759(define-operand 2760 (name FRintieven) 2761 (comment "(even) source register 1") 2762 (attrs) 2763 (type h-fr_int) 2764 (index f-FRi) 2765 (mode SI) 2766 (handlers (parse "even_register")) 2767) 2768 2769(define-operand 2770 (name FRintjeven) 2771 (comment "(even) source register 2") 2772 (attrs) 2773 (type h-fr_int) 2774 (index f-FRj) 2775 (mode SI) 2776 (handlers (parse "even_register")) 2777) 2778 2779(define-operand 2780 (name FRintkeven) 2781 (comment "(even) target register") 2782 (attrs) 2783 (type h-fr_int) 2784 (index f-FRk) 2785 (mode SI) 2786 (handlers (parse "even_register")) 2787) 2788 2789(define-operand 2790 (name d12) 2791 (comment "12 bit signed immediate") 2792 (attrs) 2793 (type h-sint) 2794 (index f-d12) 2795 (handlers (parse "d12")) 2796) 2797 2798(define-operand 2799 (name s12) 2800 (comment "12 bit signed immediate") 2801 (attrs HASH-PREFIX) 2802 (type h-sint) 2803 (index f-d12) 2804 (handlers (parse "s12")) 2805) 2806 2807(define-operand 2808 (name u12) 2809 (comment "12 bit signed immediate") 2810 (attrs HASH-PREFIX) 2811 (type h-sint) 2812 (index f-u12) 2813 (handlers (parse "u12")) 2814) 2815 2816(define-operand 2817 (name spr) 2818 (comment "special purpose register") 2819 (attrs) 2820 (type h-spr) 2821 (index f-spr) 2822 (handlers (parse "spr") (print "spr")) 2823) 2824 2825(define-operand 2826 (name ulo16) 2827 (comment "16 bit unsigned immediate, for #lo()") 2828 (attrs) 2829 (type h-uint) 2830 (index f-u16) 2831 (handlers (parse "ulo16") (print "lo")) 2832) 2833 2834(define-operand 2835 (name slo16) 2836 (comment "16 bit unsigned immediate, for #lo()") 2837 (attrs) 2838 (type h-sint) 2839 (index f-s16) 2840 (handlers (parse "uslo16") (print "lo")) 2841) 2842 2843(define-operand 2844 (name uhi16) 2845 (comment "16 bit unsigned immediate, for #hi()") 2846 (attrs) 2847 (type h-uint) 2848 (index f-u16) 2849 (handlers (parse "uhi16") (print "hi")) 2850) 2851 2852; operands representing hardware 2853; 2854(dnop psr_esr "PSR.ESR bit" (SEM-ONLY) h-psr_esr f-nil) 2855(dnop psr_s "PSR.S bit" (SEM-ONLY) h-psr_s f-nil) 2856(dnop psr_ps "PSR.PS bit" (SEM-ONLY) h-psr_ps f-nil) 2857(dnop psr_et "PSR.ET bit" (SEM-ONLY) h-psr_et f-nil) 2858 2859(dnop bpsr_bs "BPSR.BS bit" (SEM-ONLY) h-bpsr_bs f-nil) 2860(dnop bpsr_bet "BPSR.BET bit" (SEM-ONLY) h-bpsr_bet f-nil) 2861 2862(dnop tbr_tba "TBR.TBA" (SEM-ONLY) h-tbr_tba f-nil) 2863(dnop tbr_tt "TBR.TT" (SEM-ONLY) h-tbr_tt f-nil) 2864 2865; Null operands 2866; 2867(define-pmacro (ICCi_1-null) (f-ICCi_1-null 0)) 2868(define-pmacro (ICCi_2-null) (f-ICCi_2-null 0)) 2869(define-pmacro (ICCi_3-null) (f-ICCi_3-null 0)) 2870(define-pmacro (FCCi_1-null) (f-FCCi_1-null 0)) 2871(define-pmacro (FCCi_2-null) (f-FCCi_2-null 0)) 2872(define-pmacro (FCCi_3-null) (f-FCCi_3-null 0)) 2873(define-pmacro (rs-null) (f-rs-null 0)) 2874(define-pmacro (GRi-null) (f-GRi-null 0)) 2875(define-pmacro (GRj-null) (f-GRj-null 0)) 2876(define-pmacro (GRk-null) (f-GRk-null 0)) 2877(define-pmacro (FRi-null) (f-FRi-null 0)) 2878(define-pmacro (FRj-null) (f-FRj-null 0)) 2879(define-pmacro (ACCj-null) (f-ACCj-null 0)) 2880(define-pmacro (rd-null) (f-rd-null 0)) 2881(define-pmacro (cond-null) (f-cond-null 0)) 2882(define-pmacro (ccond-null) (f-ccond-null 0)) 2883(define-pmacro (s12-null) (f-s12-null 0)) 2884(define-pmacro (label16-null) (f-label16-null 0)) 2885(define-pmacro (misc-null-1) (f-misc-null-1 0)) 2886(define-pmacro (misc-null-2) (f-misc-null-2 0)) 2887(define-pmacro (misc-null-3) (f-misc-null-3 0)) 2888(define-pmacro (misc-null-4) (f-misc-null-4 0)) 2889(define-pmacro (misc-null-5) (f-misc-null-5 0)) 2890(define-pmacro (misc-null-6) (f-misc-null-6 0)) 2891(define-pmacro (misc-null-7) (f-misc-null-7 0)) 2892(define-pmacro (misc-null-8) (f-misc-null-8 0)) 2893(define-pmacro (misc-null-9) (f-misc-null-9 0)) 2894(define-pmacro (misc-null-10) (f-misc-null-10 0)) 2895(define-pmacro (misc-null-11) (f-misc-null-11 0)) 2896 2897(define-pmacro (LI-on) (f-LI-on 1)) 2898(define-pmacro (LI-off) (f-LI-off 0)) 2899 2900; Instruction definitions. 2901; 2902; Notes: 2903; - dni is short for "define-normal-instruction" 2904; - Macros are used to represent each insn format. These should be used as much 2905; as possible unless an insn has exceptional behaviour 2906; 2907 2908; Commonly used Macros 2909; 2910; Specific registers 2911; 2912 2913; Integer condition code manipulation 2914; 2915(define-pmacro (set-z-and-n icc x) 2916 (if (eq x 0) 2917 (set icc (or (and icc #x7) #x4)) 2918 (if (lt x 0) 2919 (set icc (or (and icc #xb) #x8)) 2920 (set icc (and icc #x3)))) 2921) 2922 2923(define-pmacro (set-n icc val) 2924 (if (eq val 0) 2925 (set icc (and icc #x7)) 2926 (set icc (or icc #x8))) 2927) 2928 2929(define-pmacro (set-z icc val) 2930 (if (eq val 0) 2931 (set icc (and icc #xb)) 2932 (set icc (or icc #x4))) 2933) 2934 2935(define-pmacro (set-v icc val) 2936 (if (eq val 0) 2937 (set icc (and icc #xd)) 2938 (set icc (or icc #x2))) 2939) 2940 2941(define-pmacro (set-c icc val) 2942 (if (eq val 0) 2943 (set icc (and icc #xe)) 2944 (set icc (or icc #x1))) 2945) 2946 2947(define-pmacro (nbit icc) 2948 (trunc BI (srl (and icc #x8) 3)) 2949) 2950 2951(define-pmacro (zbit icc) 2952 (trunc BI (srl (and icc #x4) 2)) 2953) 2954 2955(define-pmacro (vbit icc) 2956 (trunc BI (srl (and icc #x2) 1)) 2957) 2958 2959(define-pmacro (cbit icc) 2960 (trunc BI (and icc #x1)) 2961) 2962 2963(define-pmacro (ebit icc) 2964 (trunc BI (srl (and icc #x8) 3)) 2965) 2966 2967(define-pmacro (lbit icc) 2968 (trunc BI (srl (and icc #x4) 2)) 2969) 2970 2971(define-pmacro (gbit icc) 2972 (trunc BI (srl (and icc #x2) 1)) 2973) 2974 2975(define-pmacro (ubit icc) 2976 (trunc BI (and icc #x1)) 2977) 2978 2979; FRV insns 2980; 2981; 2982; Format: INT, Logic, Shift r-r 2983; 2984(define-pmacro (int-logic-r-r name operation op ope comment) 2985 (dni name 2986 (comment) 2987 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 2988 (.str name "$pack $GRi,$GRj,$GRk") 2989 (+ pack GRk op GRi (ICCi_1-null) ope GRj) 2990 (set GRk (operation GRi GRj)) 2991 ((fr400 (unit u-integer)) 2992 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 2993 ) 2994) 2995 2996(int-logic-r-r add add OP_00 OPE2_00 "add reg/reg") 2997(int-logic-r-r sub sub OP_00 OPE2_04 "sub reg/reg") 2998(int-logic-r-r and and OP_01 OPE2_00 "and reg/reg") 2999(int-logic-r-r or or OP_01 OPE2_02 "or reg/reg") 3000(int-logic-r-r xor xor OP_01 OPE2_04 "xor reg/reg") 3001 3002(dni not 3003 ("not") 3004 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3005 ("not$pack $GRj,$GRk") 3006 (+ pack GRk OP_01 (rs-null) (ICCi_1-null) OPE2_06 GRj) 3007 (set GRk (inv GRj)) 3008 ((fr400 (unit u-integer)) 3009 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3010) 3011 3012(dni sdiv 3013 "signed division" 3014 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) 3015 "sdiv$pack $GRi,$GRj,$GRk" 3016 (+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0E GRj) 3017 (sequence () 3018 (c-call VOID "@cpu@_signed_integer_divide" 3019 GRi GRj (index-of GRk) 0) 3020 (clobber GRk)) 3021 ((fr400 (unit u-idiv)) 3022 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3023) 3024 3025(dni nsdiv 3026 "non excepting signed division" 3027 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING 3028 (MACH simple,tomcat,fr500,fr550,frv)) 3029 "nsdiv$pack $GRi,$GRj,$GRk" 3030 (+ pack GRk OP_01 GRi (ICCi_1-null) OPE2_0E GRj) 3031 (sequence () 3032 (c-call VOID "@cpu@_signed_integer_divide" 3033 GRi GRj (index-of GRk) 1) 3034 (clobber GRk)) 3035 ((fr400 (unit u-idiv)) 3036 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3037) 3038 3039(dni udiv 3040 "unsigned division reg/reg" 3041 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) 3042 "udiv$pack $GRi,$GRj,$GRk" 3043 (+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0F GRj) 3044 (sequence () 3045 (c-call VOID "@cpu@_unsigned_integer_divide" 3046 GRi GRj (index-of GRk) 0) 3047 (clobber GRk)) 3048 ((fr400 (unit u-idiv)) 3049 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3050) 3051 3052(dni nudiv 3053 "non excepting unsigned division" 3054 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING 3055 (MACH simple,tomcat,fr500,fr550,frv)) 3056 "nudiv$pack $GRi,$GRj,$GRk" 3057 (+ pack GRk OP_01 GRi (ICCi_1-null) OPE2_0F GRj) 3058 (sequence () 3059 (c-call VOID "@cpu@_unsigned_integer_divide" 3060 GRi GRj (index-of GRk) 1) 3061 (clobber GRk)) 3062 ((fr400 (unit u-idiv)) 3063 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3064) 3065 3066; Multiplication 3067; 3068(define-pmacro (multiply-r-r name signop op ope comment) 3069 (dni name 3070 (comment) 3071 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) 3072 (.str name "$pack $GRi,$GRj,$GRdoublek") 3073 (+ pack GRdoublek op GRi (ICCi_1-null) ope GRj) 3074 (set GRdoublek (mul DI (signop DI GRi) (signop DI GRj))) 3075 ((fr400 (unit u-imul)) 3076 (fr500 (unit u-imul)) (fr550 (unit u-imul))) 3077 ) 3078) 3079 3080(multiply-r-r smul ext OP_00 OPE2_08 "signed multiply reg/reg") 3081(multiply-r-r umul zext OP_00 OPE2_0A "unsigned multiply reg/reg") 3082 3083; Multiplication with integer accumulator IACC 3084; 3085 3086(define-pmacro (iacc-set value) 3087 (set (reg h-iacc0 0) value)) 3088 3089(define-pmacro (iacc-add value) 3090 (set (reg h-iacc0 0) 3091 (cond DI 3092 ((andif (andif (gt value 0) (gt (reg h-iacc0 0) 0)) 3093 (lt (sub DI #x7fffffffffffffff value) (reg h-iacc0 0))) 3094 ; Positive overflow 3095 (const DI #x7fffffffffffffff)) 3096 ((andif (andif (lt value 0) (lt (reg h-iacc0 0) 0)) 3097 (gt (sub DI #x8000000000000000 value) (reg h-iacc0 0))) 3098 ; Negative overflow 3099 (const DI #x8000000000000000)) 3100 (else 3101 (add DI (reg h-iacc0 0) value)))) 3102) 3103 3104(define-pmacro (iacc-sub value) 3105 (set (reg h-iacc0 0) 3106 (cond DI 3107 ((andif (andif (lt value 0) (gt (reg h-iacc0 0) 0)) 3108 (lt (add DI #x7fffffffffffffff value) (reg h-iacc0 0))) 3109 ; Positive overflow 3110 (const DI #x7fffffffffffffff)) 3111 ((andif (andif (gt value 0) (lt (reg h-iacc0 0) 0)) 3112 (gt (add DI #x8000000000000000 value) (reg h-iacc0 0))) 3113 ; Negative overflow 3114 (const DI #x8000000000000000)) 3115 (else 3116 (sub DI (reg h-iacc0 0) value)))) 3117) 3118 3119(define-pmacro (iacc-multiply-r-r name operation op ope comment) 3120 (dni name 3121 (comment) 3122 ((UNIT IACC) (FR400-MAJOR I-1) (MACH fr400)) 3123 (.str name "$pack $GRi,$GRj") 3124 (+ pack (rd-null) op GRi ope GRj) 3125 ((.sym iacc- operation) (mul DI (ext DI GRi) (ext DI GRj))) 3126 ((fr400 (unit u-integer))) 3127 ) 3128) 3129 3130(iacc-multiply-r-r smu set OP_46 OPE1_05 "Signed multiply reg/reg/iacc") 3131(iacc-multiply-r-r smass add OP_46 OPE1_06 "Signed multiply/add reg/reg/iacc") 3132(iacc-multiply-r-r smsss sub OP_46 OPE1_07 "Signed multiply/sub reg/reg/iacc") 3133 3134(define-pmacro (int-shift-r-r name op ope comment) 3135 (dni name 3136 (comment) 3137 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3138 (.str name "$pack $GRi,$GRj,$GRk") 3139 (+ pack GRk op GRi (ICCi_1-null) ope GRj) 3140 (set GRk (name GRi (and GRj #x1f))) 3141 ((fr400 (unit u-integer)) 3142 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3143 ) 3144) 3145 3146(int-shift-r-r sll OP_01 OPE2_08 "shift left logical reg/reg") 3147(int-shift-r-r srl OP_01 OPE2_0A "shift right logical reg/reg") 3148(int-shift-r-r sra OP_01 OPE2_0C "shift right arith reg/reg") 3149 3150(dni slass 3151 "shift left arith reg/reg with saturation" 3152 ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400)) 3153 "slass$pack $GRi,$GRj,$GRk" 3154 (+ pack GRk OP_46 GRi OPE1_02 GRj) 3155 (set GRk (c-call SI "@cpu@_shift_left_arith_saturate" GRi GRj)) 3156 () 3157) 3158 3159(dni scutss 3160 "Integer accumulator cut with saturation" 3161 ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400)) 3162 "scutss$pack $GRj,$GRk" 3163 (+ pack GRk OP_46 (rs-null) OPE1_04 GRj) 3164 (set GRk (c-call SI "@cpu@_iacc_cut" (reg h-iacc0 0) GRj)) 3165 () 3166) 3167 3168(define-pmacro (scan-semantics arg1 arg2 targ) 3169 (sequence ((WI tmp1) (WI tmp2)) 3170 (set tmp1 arg1) 3171 (set tmp2 (sra arg2 1)) 3172 (set targ (c-call WI "@cpu@_scan_result" (xor tmp1 tmp2)))) 3173) 3174 3175(dni scan 3176 "scan" 3177 ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3178 "scan$pack $GRi,$GRj,$GRk" 3179 (+ pack GRk OP_0B GRi (ICCi_1-null) OPE2_00 GRj) 3180 (scan-semantics GRi GRj GRk) 3181 ((fr400 (unit u-integer)) 3182 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3183) 3184 3185; Format: conditional INT, Logic, Shift r-r 3186; 3187(define-pmacro (conditional-int-logic name operation op ope comment) 3188 (dni name 3189 (comment) 3190 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) 3191 (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") 3192 (+ pack GRk op GRi CCi cond ope GRj) 3193 (if (eq CCi (or cond 2)) 3194 (set GRk (operation GRi GRj))) 3195 ((fr400 (unit u-integer)) 3196 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3197 ) 3198) 3199 3200(conditional-int-logic cadd add OP_58 OPE4_0 "conditional add") 3201(conditional-int-logic csub sub OP_58 OPE4_1 "conditional sub") 3202(conditional-int-logic cand and OP_5A OPE4_0 "conditional and") 3203(conditional-int-logic cor or OP_5A OPE4_1 "conditional or") 3204(conditional-int-logic cxor xor OP_5A OPE4_2 "conditional xor") 3205 3206(dni cnot 3207 "conditional not" 3208 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) 3209 "cnot$pack $GRj,$GRk,$CCi,$cond" 3210 (+ pack GRk OP_5A (rs-null) CCi cond OPE4_3 GRj) 3211 (if (eq CCi (or cond 2)) 3212 (set GRk (inv GRj))) 3213 ((fr400 (unit u-integer)) 3214 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3215) 3216 3217(dni csmul 3218 "conditional signed multiply" 3219 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL) 3220 "csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond" 3221 (+ pack GRdoublek OP_58 GRi CCi cond OPE4_2 GRj) 3222 (if (eq CCi (or cond 2)) 3223 (set GRdoublek (mul DI (ext DI GRi) (ext DI GRj)))) 3224 ((fr400 (unit u-imul)) 3225 (fr500 (unit u-imul)) (fr550 (unit u-imul))) 3226) 3227 3228(dni csdiv 3229 "conditional signed division" 3230 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL) 3231 "csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond" 3232 (+ pack GRk OP_58 GRi CCi cond OPE4_3 GRj) 3233 (if (eq CCi (or cond 2)) 3234 (sequence () 3235 (c-call VOID "@cpu@_signed_integer_divide" 3236 GRi GRj (index-of GRk) 0) 3237 (clobber GRk))) 3238 ((fr400 (unit u-idiv)) 3239 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3240) 3241 3242(dni cudiv 3243 "conditional unsigned division" 3244 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL) 3245 "cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond" 3246 (+ pack GRk OP_59 GRi CCi cond OPE4_3 GRj) 3247 (if (eq CCi (or cond 2)) 3248 (sequence () 3249 (c-call VOID "@cpu@_unsigned_integer_divide" 3250 GRi GRj (index-of GRk) 0) 3251 (clobber GRk))) 3252 ((fr400 (unit u-idiv)) 3253 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3254) 3255 3256(define-pmacro (conditional-shift name operation op ope comment) 3257 (dni name 3258 (comment) 3259 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) 3260 (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") 3261 (+ pack GRk op GRi CCi cond ope GRj) 3262 (if (eq CCi (or cond 2)) 3263 (set GRk (operation GRi (and GRj #x1f)))) 3264 ((fr400 (unit u-integer)) 3265 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3266 ) 3267) 3268 3269(conditional-shift csll sll OP_5C OPE4_0 "conditional shift left logical") 3270(conditional-shift csrl srl OP_5C OPE4_1 "conditional shift right logical") 3271(conditional-shift csra sra OP_5C OPE4_2 "conditional shift right arith") 3272 3273(dni cscan 3274 "conditional scan" 3275 ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) 3276 "cscan$pack $GRi,$GRj,$GRk,$CCi,$cond" 3277 (+ pack GRk OP_65 GRi CCi cond OPE4_3 GRj) 3278 (if (eq CCi (or cond 2)) 3279 (scan-semantics GRi GRj GRk)) 3280 ((fr400 (unit u-integer)) 3281 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3282) 3283 3284; Format: INT, Logic, Shift, cc r-r 3285; 3286(define-pmacro (int-arith-cc-semantics operation icc) 3287 (sequence ((BI tmp) (QI cc) (SI result)) 3288 (set cc icc) 3289 (set tmp ((.sym operation -oflag) GRi GRj (const 0))) 3290 (set-v cc tmp) 3291 (set tmp ((.sym operation -cflag) GRi GRj (const 0))) 3292 (set-c cc tmp) 3293 (set result (operation GRi GRj)) 3294 (set-z-and-n cc result) 3295 (set GRk result) 3296 (set icc cc)) 3297) 3298 3299(define-pmacro (int-arith-cc-r-r name operation op ope comment) 3300 (dni name 3301 (comment) 3302 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3303 (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") 3304 (+ pack GRk op GRi ICCi_1 ope GRj) 3305 (int-arith-cc-semantics operation ICCi_1) 3306 ((fr400 (unit u-integer)) 3307 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3308 ) 3309) 3310 3311(int-arith-cc-r-r addcc add OP_00 OPE2_01 "add reg/reg, set icc") 3312(int-arith-cc-r-r subcc sub OP_00 OPE2_05 "sub reg/reg, set icc") 3313 3314(define-pmacro (int-logic-cc-semantics op icc) 3315 (sequence ((SI tmp)) 3316 (set tmp (op GRi GRj)) 3317 (set GRk tmp) 3318 (set-z-and-n icc tmp)) 3319) 3320 3321(define-pmacro (int-logic-cc-r-r name op ope comment) 3322 (dni (.sym name cc) 3323 (comment) 3324 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3325 (.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1") 3326 (+ pack GRk op GRi ICCi_1 ope GRj) 3327 (int-logic-cc-semantics name ICCi_1) 3328 ((fr400 (unit u-integer)) 3329 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3330 ) 3331) 3332 3333(int-logic-cc-r-r and OP_01 OPE2_01 "and reg/reg, set icc") 3334(int-logic-cc-r-r or OP_01 OPE2_03 "or reg/reg, set icc") 3335(int-logic-cc-r-r xor OP_01 OPE2_05 "xor reg/reg, set icc") 3336 3337(define-pmacro (int-shift-cc-semantics op l-r icc) 3338 (sequence ((WI shift) (SI tmp) (QI cc)) 3339 (set shift (and GRj #x1f)) 3340 (set cc (c-call QI (.str "@cpu@_set_icc_for_shift_" l-r) 3341 GRi shift icc)) 3342 (set tmp (op GRi shift)) 3343 (set GRk tmp) 3344 (set-z-and-n cc tmp) 3345 (set icc cc)) 3346) 3347 3348(define-pmacro (int-shift-cc-r-r name l-r op ope comment) 3349 (dni (.sym name cc) 3350 (comment) 3351 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3352 (.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1") 3353 (+ pack GRk op GRi ICCi_1 ope GRj) 3354 (int-shift-cc-semantics name l-r ICCi_1) 3355 ((fr400 (unit u-integer)) 3356 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3357 ) 3358) 3359 3360(int-shift-cc-r-r sll left OP_01 OPE2_09 "shift left logical reg/reg,set icc") 3361(int-shift-cc-r-r srl right OP_01 OPE2_0B "shift right logical reg/reg,set icc") 3362(int-shift-cc-r-r sra right OP_01 OPE2_0D "shift right arith reg/reg,set icc") 3363 3364(define-pmacro (multiply-cc-semantics signop arg1 arg2 targ icc) 3365 (sequence ((DI tmp) (QI cc)) 3366 (set cc icc) 3367 (set tmp (mul DI (signop DI arg1) (signop DI arg2))) 3368 (set-n cc (srl DI tmp 63)) 3369 (set-z cc (eq tmp 0)) 3370 (set targ tmp) 3371 (set icc cc)) 3372) 3373 3374(define-pmacro (multiply-cc-r-r name signop op ope comment) 3375 (dni name 3376 (comment) 3377 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) 3378 (.str name "$pack $GRi,$GRj,$GRdoublek,$ICCi_1") 3379 (+ pack GRdoublek op GRi ICCi_1 ope GRj) 3380 (multiply-cc-semantics signop GRi GRj GRdoublek ICCi_1) 3381 ((fr400 (unit u-imul)) 3382 (fr500 (unit u-imul)) (fr550 (unit u-imul))) 3383 ) 3384) 3385 3386(multiply-cc-r-r smulcc ext OP_00 OPE2_09 "signed multiply reg/reg") 3387(multiply-cc-r-r umulcc zext OP_00 OPE2_0B "unsigned multiply reg/reg") 3388 3389 3390; Format: conditional INT, Logic, Shift, cc r-r 3391; 3392(define-pmacro (conditional-int-arith-cc name operation op ope comment) 3393 (dni name 3394 (comment) 3395 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) 3396 (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") 3397 (+ pack GRk op GRi CCi cond ope GRj) 3398 (if (eq CCi (or cond 2)) 3399 (int-arith-cc-semantics operation 3400 (reg h-iccr (and (index-of CCi) 3)))) 3401 ((fr400 (unit u-integer)) 3402 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3403 ) 3404) 3405 3406(conditional-int-arith-cc caddcc add OP_59 OPE4_0 "add, set icc") 3407(conditional-int-arith-cc csubcc sub OP_59 OPE4_1 "sub, set icc") 3408 3409(dni csmulcc 3410 "conditional signed multiply and set condition code" 3411 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL) 3412 "csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond" 3413 (+ pack GRdoublek OP_59 GRi CCi cond OPE4_2 GRj) 3414 (if (eq CCi (or cond 2)) 3415 (multiply-cc-semantics ext GRi GRj GRdoublek 3416 (reg h-iccr (and (index-of CCi) 3)))) 3417 ((fr400 (unit u-imul)) 3418 (fr500 (unit u-imul)) (fr550 (unit u-imul))) 3419) 3420 3421(define-pmacro (conditional-int-logic-cc name operation op ope comment) 3422 (dni name 3423 (comment) 3424 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) 3425 (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") 3426 (+ pack GRk op GRi CCi cond ope GRj) 3427 (if (eq CCi (or cond 2)) 3428 (int-logic-cc-semantics operation 3429 (reg h-iccr (and (index-of CCi) 3)))) 3430 ((fr400 (unit u-integer)) 3431 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3432 ) 3433) 3434 3435(conditional-int-logic-cc candcc and OP_5B OPE4_0 "conditional and, set icc") 3436(conditional-int-logic-cc corcc or OP_5B OPE4_1 "conditional or , set icc") 3437(conditional-int-logic-cc cxorcc xor OP_5B OPE4_2 "conditional xor, set icc") 3438 3439(define-pmacro (conditional-int-shift-cc name l-r op ope comment) 3440 (dni (.sym c name cc) 3441 (comment) 3442 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) 3443 (.str (.sym c name cc) "$pack $GRi,$GRj,$GRk,$CCi,$cond") 3444 (+ pack GRk op GRi CCi cond ope GRj) 3445 (if (eq CCi (or cond 2)) 3446 (int-shift-cc-semantics name l-r 3447 (reg h-iccr (and (index-of CCi) 3)))) 3448 ((fr400 (unit u-integer)) 3449 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3450 ) 3451) 3452 3453(conditional-int-shift-cc sll left OP_5D OPE4_0 "shift left logical, set icc") 3454(conditional-int-shift-cc srl right OP_5D OPE4_1 "shift right logical, set icc") 3455(conditional-int-shift-cc sra right OP_5D OPE4_2 "shift right arith , set icc") 3456 3457; Add and subtract with carry 3458; 3459(define-pmacro (int-arith-x-r-r name operation op ope comment) 3460 (dni name 3461 (comment) 3462 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3463 (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") 3464 (+ pack GRk op GRi ICCi_1 ope GRj) 3465 (set GRk ((.sym operation c) GRi GRj (cbit ICCi_1))) 3466 ((fr400 (unit u-integer)) 3467 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3468 ) 3469) 3470 3471(int-arith-x-r-r addx add OP_00 OPE2_02 "Add reg/reg, with carry") 3472(int-arith-x-r-r subx sub OP_00 OPE2_06 "Sub reg/reg, with carry") 3473 3474(define-pmacro (int-arith-x-cc-r-r name operation op ope comment) 3475 (dni name 3476 (comment) 3477 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3478 (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") 3479 (+ pack GRk op GRi ICCi_1 ope GRj) 3480 (sequence ((WI tmp) (QI cc)) 3481 (set cc ICCi_1) 3482 (set tmp ((.sym operation c) GRi GRj (cbit cc))) 3483 (set-v cc ((.sym operation -oflag) GRi GRj (cbit cc))) 3484 (set-c cc ((.sym operation -cflag) GRi GRj (cbit cc))) 3485 (set-z-and-n cc tmp) 3486 (set GRk tmp) 3487 (set ICCi_1 cc)) 3488 ((fr400 (unit u-integer)) 3489 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3490 ) 3491) 3492 3493(int-arith-x-cc-r-r addxcc add OP_00 OPE2_03 "Add reg/reg, use/set carry") 3494(int-arith-x-cc-r-r subxcc sub OP_00 OPE2_07 "Sub reg/reg, use/set carry") 3495; Add and subtract with saturation 3496; 3497(define-pmacro (int-arith-ss-r-r name operation op ope comment) 3498 (dni name 3499 (comment) 3500 ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400)) 3501 (.str name "$pack $GRi,$GRj,$GRk") 3502 (+ pack GRk op GRi ope GRj) 3503 (sequence () 3504 (set GRk (operation GRi GRj)) 3505 (if ((.sym operation -oflag) GRi GRj (const 0)) 3506 ; Overflow, saturate. 3507 ; Sign of result will be 3508 ; same as sign of first operand. 3509 (set GRk 3510 (cond SI 3511 ((gt GRi 0) (const #x7fffffff)) 3512 ((lt GRi 0) (const #x80000000)) 3513 (else (const 0))))) 3514 ) 3515 ((fr400 (unit u-integer))) 3516 ) 3517) 3518 3519(int-arith-ss-r-r addss add OP_46 OPE1_00 "add reg/reg, with saturation") 3520(int-arith-ss-r-r subss sub OP_46 OPE1_01 "sub reg/reg, with saturation") 3521 3522; Format: INT, Logic, Shift r-simm 3523; 3524(define-pmacro (int-logic-r-simm name operation op comment) 3525 (dni name 3526 (comment) 3527 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3528 (.str name "$pack $GRi,$s12,$GRk") 3529 (+ pack GRk op GRi s12) 3530 (set GRk (operation GRi s12)) 3531 ((fr400 (unit u-integer)) 3532 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3533 ) 3534) 3535 3536(int-logic-r-simm addi add OP_10 "add reg/immed") 3537(int-logic-r-simm subi sub OP_14 "sub reg/immed") 3538(int-logic-r-simm andi and OP_20 "and reg/immed") 3539(int-logic-r-simm ori or OP_22 "or reg/immed") 3540(int-logic-r-simm xori xor OP_24 "xor reg/immed") 3541 3542(dni sdivi 3543 "signed division reg/immed" 3544 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) 3545 "sdivi$pack $GRi,$s12,$GRk" 3546 (+ pack GRk OP_1E GRi s12) 3547 (sequence () 3548 (c-call VOID "@cpu@_signed_integer_divide" 3549 GRi s12 (index-of GRk) 0) 3550 (clobber GRk)) 3551 ((fr400 (unit u-idiv)) 3552 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3553) 3554 3555(dni nsdivi 3556 "non excepting signed division reg/immed" 3557 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING 3558 (MACH simple,tomcat,fr500,fr550,frv)) 3559 "nsdivi$pack $GRi,$s12,$GRk" 3560 (+ pack GRk OP_2E GRi s12) 3561 (sequence () 3562 (c-call VOID "@cpu@_signed_integer_divide" 3563 GRi s12 (index-of GRk) 1) 3564 (clobber GRk)) 3565 ((fr400 (unit u-idiv)) 3566 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3567) 3568 3569(dni udivi 3570 "unsigned division reg/immed" 3571 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) 3572 "udivi$pack $GRi,$s12,$GRk" 3573 (+ pack GRk OP_1F GRi s12) 3574 (sequence () 3575 (c-call VOID "@cpu@_unsigned_integer_divide" 3576 GRi s12 (index-of GRk) 0) 3577 (clobber GRk)) 3578 ((fr400 (unit u-idiv)) 3579 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3580) 3581 3582(dni nudivi 3583 "non excepting unsigned division reg/immed" 3584 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING 3585 (MACH simple,tomcat,fr500,fr550,frv)) 3586 "nudivi$pack $GRi,$s12,$GRk" 3587 (+ pack GRk OP_2F GRi s12) 3588 (sequence () 3589 (c-call VOID "@cpu@_unsigned_integer_divide" 3590 GRi s12 (index-of GRk) 1) 3591 (clobber GRk)) 3592 ((fr400 (unit u-idiv)) 3593 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3594) 3595 3596(define-pmacro (multiply-r-simm name signop op comment) 3597 (dni name 3598 (comment) 3599 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) 3600 (.str name "$pack $GRi,$s12,$GRdoublek") 3601 (+ pack GRdoublek op GRi s12) 3602 (set GRdoublek (mul DI (signop DI GRi) (signop DI s12))) 3603 ((fr400 (unit u-imul)) 3604 (fr500 (unit u-imul)) (fr550 (unit u-imul))) 3605 ) 3606) 3607 3608(multiply-r-simm smuli ext OP_18 "signed multiply reg/immed") 3609(multiply-r-simm umuli zext OP_1A "unsigned multiply reg/immed") 3610 3611(define-pmacro (int-shift-r-simm name op comment) 3612 (dni (.sym name i) 3613 (comment) 3614 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3615 (.str (.sym name i) "$pack $GRi,$s12,$GRk") 3616 (+ pack GRk op GRi s12) 3617 (set GRk (name GRi (and s12 #x1f))) 3618 ((fr400 (unit u-integer)) 3619 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3620 ) 3621) 3622 3623(int-shift-r-simm sll OP_28 "shift left logical reg/immed") 3624(int-shift-r-simm srl OP_2A "shift right logical reg/immed") 3625(int-shift-r-simm sra OP_2C "shift right arith reg/immed") 3626 3627(dni scani 3628 "scan immediate" 3629 ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3630 "scani$pack $GRi,$s12,$GRk" 3631 (+ pack GRk OP_47 GRi s12) 3632 (scan-semantics GRi s12 GRk) 3633 ((fr400 (unit u-integer)) 3634 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3635) 3636 3637; Format: INT, Logic, Shift cc r-simm 3638; 3639(define-pmacro (int-arith-cc-r-simm name operation op comment) 3640 (dni name 3641 (comment) 3642 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3643 (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") 3644 (+ pack GRk op GRi ICCi_1 s10) 3645 (sequence ((BI tmp) (QI cc) (SI result)) 3646 (set cc ICCi_1) 3647 (set tmp ((.sym operation -oflag) GRi s10 (const 0))) 3648 (set-v cc tmp) 3649 (set tmp ((.sym operation -cflag) GRi s10 (const 0))) 3650 (set-c cc tmp) 3651 (set result (operation GRi s10)) 3652 (set-z-and-n cc result) 3653 (set GRk result) 3654 (set ICCi_1 cc)) 3655 ((fr400 (unit u-integer)) 3656 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3657 ) 3658) 3659 3660(int-arith-cc-r-simm addicc add OP_11 "add reg/immed, set icc") 3661(int-arith-cc-r-simm subicc sub OP_15 "sub reg/immed, set icc") 3662 3663(define-pmacro (int-logic-cc-r-simm name op comment) 3664 (dni (.sym name icc) 3665 (comment) 3666 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3667 (.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1") 3668 (+ pack GRk op GRi ICCi_1 s10) 3669 (sequence ((SI tmp)) 3670 (set tmp (name GRi s10)) 3671 (set GRk tmp) 3672 (set-z-and-n ICCi_1 tmp)) 3673 ((fr400 (unit u-integer)) 3674 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3675 ) 3676) 3677 3678(int-logic-cc-r-simm and OP_21 "and reg/immed, set icc") 3679(int-logic-cc-r-simm or OP_23 "or reg/immed, set icc") 3680(int-logic-cc-r-simm xor OP_25 "xor reg/immed, set icc") 3681 3682(define-pmacro (multiply-cc-r-simm name signop op comment) 3683 (dni name 3684 (comment) 3685 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1)) 3686 (.str name "$pack $GRi,$s10,$GRdoublek,$ICCi_1") 3687 (+ pack GRdoublek op GRi ICCi_1 s10) 3688 (multiply-cc-semantics signop GRi s10 GRdoublek ICCi_1) 3689 ((fr400 (unit u-imul)) 3690 (fr500 (unit u-imul)) (fr550 (unit u-imul))) 3691 ) 3692) 3693 3694(multiply-cc-r-simm smulicc ext OP_19 "signed multiply reg/immed") 3695(multiply-cc-r-simm umulicc zext OP_1B "unsigned multiply reg/immed") 3696 3697(define-pmacro (int-shift-cc-r-simm name l-r op comment) 3698 (dni (.sym name icc) 3699 (comment) 3700 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3701 (.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1") 3702 (+ pack GRk op GRi ICCi_1 s10) 3703 (sequence ((WI shift) (SI tmp) (QI cc)) 3704 (set shift (and s10 #x1f)) 3705 (set cc (c-call QI (.str "@cpu@_set_icc_for_shift_" l-r) 3706 GRi shift ICCi_1)) 3707 (set tmp (name GRi shift)) 3708 (set GRk tmp) 3709 (set-z-and-n cc tmp) 3710 (set ICCi_1 cc)) 3711 ((fr400 (unit u-integer)) 3712 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3713 ) 3714) 3715 3716(int-shift-cc-r-simm sll left OP_29 "shift left logical reg/immed, set icc") 3717(int-shift-cc-r-simm srl right OP_2B "shift right logical reg/immed, set icc") 3718(int-shift-cc-r-simm sra right OP_2D "shift right arith reg/immed, set icc") 3719 3720(define-pmacro (int-arith-x-r-simm name operation op comment) 3721 (dni name 3722 (comment) 3723 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3724 (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") 3725 (+ pack GRk op GRi ICCi_1 s10) 3726 (set GRk ((.sym operation c) GRi s10 (cbit ICCi_1))) 3727 ((fr400 (unit u-integer)) 3728 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3729 ) 3730) 3731 3732(int-arith-x-r-simm addxi add OP_12 "Add reg/immed, with carry") 3733(int-arith-x-r-simm subxi sub OP_16 "Sub reg/immed, with carry") 3734 3735(define-pmacro (int-arith-x-cc-r-simm name operation op comment) 3736 (dni name 3737 (comment) 3738 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3739 (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") 3740 (+ pack GRk op GRi ICCi_1 s10) 3741 (sequence ((WI tmp) (QI cc)) 3742 (set cc ICCi_1) 3743 (set tmp ((.sym operation c) GRi s10 (cbit cc))) 3744 (set-v cc ((.sym operation -oflag) GRi s10 (cbit cc))) 3745 (set-c cc ((.sym operation -cflag) GRi s10 (cbit cc))) 3746 (set-z-and-n cc tmp) 3747 (set GRk tmp) 3748 (set ICCi_1 cc)) 3749 ((fr400 (unit u-integer)) 3750 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3751 ) 3752) 3753 3754(int-arith-x-cc-r-simm addxicc add OP_13 "Add reg/immed, with carry") 3755(int-arith-x-cc-r-simm subxicc sub OP_17 "Sub reg/immed, with carry") 3756 3757; Byte compare insns 3758 3759(dni cmpb 3760 "Compare bytes" 3761 ((UNIT IALL) (FR400-MAJOR I-1) (FR550-MAJOR I-1) (MACH fr400,fr550)) 3762 "cmpb$pack $GRi,$GRj,$ICCi_1" 3763 (+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0C GRj) 3764 (sequence ((QI cc)) 3765 (set-n cc (eq (and GRi #xff000000) (and GRj #xff000000))) 3766 (set-z cc (eq (and GRi #x00ff0000) (and GRj #x00ff0000))) 3767 (set-v cc (eq (and GRi #x0000ff00) (and GRj #x0000ff00))) 3768 (set-c cc (eq (and GRi #x000000ff) (and GRj #x000000ff))) 3769 (set ICCi_1 cc)) 3770 ((fr400 (unit u-integer)) (fr550 (unit u-integer))) 3771) 3772 3773(dni cmpba 3774 "OR of Compare bytes" 3775 ((UNIT IALL) (FR400-MAJOR I-1) (FR550-MAJOR I-1) (MACH fr400,fr550)) 3776 "cmpba$pack $GRi,$GRj,$ICCi_1" 3777 (+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0D GRj) 3778 (sequence ((QI cc)) 3779 (set cc 0) 3780 (set-c cc 3781 (orif (eq (and GRi #xff000000) (and GRj #xff000000)) 3782 (orif (eq (and GRi #x00ff0000) (and GRj #x00ff0000)) 3783 (orif (eq (and GRi #x0000ff00) 3784 (and GRj #x0000ff00)) 3785 (eq (and GRi #x000000ff) 3786 (and GRj #x000000ff)))))) 3787 (set ICCi_1 cc)) 3788 ((fr400 (unit u-integer)) (fr550 (unit u-integer))) 3789) 3790 3791; Format: Load immediate 3792; 3793(dni setlo 3794 "set low order bits" 3795 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3796 "setlo$pack $ulo16,$GRklo" 3797 (+ pack GRk OP_3D (misc-null-4) u16) 3798 (set GRklo u16) 3799 ((fr400 (unit u-set-hilo)) 3800 (fr500 (unit u-set-hilo)) (fr550 (unit u-set-hilo))) 3801) 3802 3803(dni sethi 3804 "set high order bits" 3805 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3806 "sethi$pack $uhi16,$GRkhi" 3807 (+ pack GRkhi OP_3E (misc-null-4) u16) 3808 (set GRkhi u16) 3809 ((fr400 (unit u-set-hilo)) 3810 (fr500 (unit u-set-hilo)) (fr550 (unit u-set-hilo))) 3811) 3812 3813(dni setlos 3814 "set low order bits and extend sign" 3815 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1)) 3816 "setlos$pack $slo16,$GRk" 3817 (+ pack GRk OP_3F (misc-null-4) s16) 3818 (set GRk s16) 3819 ((fr400 (unit u-integer)) 3820 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3821) 3822 3823(define-pmacro (load-gr-r name mode op ope comment) 3824 (dni name 3825 (comment) 3826 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2)) 3827 (.str name "$pack @($GRi,$GRj),$GRk") 3828 (+ pack GRk op GRi ope GRj) 3829 (set GRk (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))) 3830 ((fr400 (unit u-gr-load)) 3831 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 3832 ) 3833) 3834 3835(load-gr-r ldsb QI OP_02 OPE1_00 "Load signed byte") 3836(load-gr-r ldub UQI OP_02 OPE1_01 "Load unsigned byte") 3837(load-gr-r ldsh HI OP_02 OPE1_02 "Load signed half") 3838(load-gr-r lduh UHI OP_02 OPE1_03 "Load unsigned half") 3839(load-gr-r ld SI OP_02 OPE1_04 "Load word") 3840 3841(define-pmacro (load-fr-r name mode op ope comment) 3842 (dni name 3843 (comment) 3844 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) FR-ACCESS) 3845 (.str name "$pack @($GRi,$GRj),$FRintk") 3846 (+ pack FRintk op GRi ope GRj) 3847 (set FRintk (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))) 3848 ((fr400 (unit u-fr-load)) 3849 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 3850 ) 3851) 3852 3853(load-fr-r ldbf UQI OP_02 OPE1_08 "Load byte float") 3854(load-fr-r ldhf UHI OP_02 OPE1_09 "Load half float") 3855(load-fr-r ldf SI OP_02 OPE1_0A "Load word float") 3856 3857(define-pmacro (load-cpr-r name mode op ope reg attr comment) 3858 (dni name 3859 (comment) 3860 ((UNIT LOAD) (FR500-MAJOR I-2) attr) 3861 (.str name "$pack @($GRi,$GRj),$" reg "k") 3862 (+ pack (.sym reg k) op GRi ope GRj) 3863 (set (.sym reg k) 3864 (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))) 3865 () 3866 ) 3867) 3868 3869(load-cpr-r ldc SI OP_02 OPE1_0D CPR (MACH frv) "Load coprocessor word") 3870 3871; These correspond to enumerators in frv-sim.h 3872(define-pmacro (ne-UQI-size) 0) 3873(define-pmacro (ne-QI-size) 1) 3874(define-pmacro (ne-UHI-size) 2) 3875(define-pmacro (ne-HI-size) 3) 3876(define-pmacro (ne-SI-size) 4) 3877(define-pmacro (ne-DI-size) 5) 3878(define-pmacro (ne-XI-size) 6) 3879 3880(define-pmacro (ne-load-semantics base dispix targ idisp size is_float action) 3881 (sequence ((BI do_op)) 3882 (set do_op 3883 (c-call BI "@cpu@_check_non_excepting_load" 3884 (index-of base) dispix (index-of targ) 3885 idisp size is_float)) 3886 (if do_op action)) 3887) 3888 3889(define-pmacro (ne-load-gr-r name mode op ope size comment) 3890 (dni name 3891 (comment) 3892 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING 3893 (MACH simple,tomcat,fr500,fr550,frv)) 3894 (.str name "$pack @($GRi,$GRj),$GRk") 3895 (+ pack GRk op GRi ope GRj) 3896 (ne-load-semantics GRi (index-of GRj) GRk 0 size 0 3897 (set GRk 3898 (c-call mode (.str "@cpu@_read_mem_" mode) 3899 pc (add GRi GRj)))) 3900 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 3901 ) 3902) 3903 3904(ne-load-gr-r nldsb QI OP_02 OPE1_20 (ne-QI-size) "Load signed byte") 3905(ne-load-gr-r nldub UQI OP_02 OPE1_21 (ne-UQI-size) "Load unsigned byte") 3906(ne-load-gr-r nldsh HI OP_02 OPE1_22 (ne-HI-size) "Load signed half") 3907(ne-load-gr-r nlduh UHI OP_02 OPE1_23 (ne-UHI-size) "Load unsigned half") 3908(ne-load-gr-r nld SI OP_02 OPE1_24 (ne-SI-size) "Load word") 3909 3910(define-pmacro (ne-load-fr-r name mode op ope size comment) 3911 (dni name 3912 (comment) 3913 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS 3914 (MACH simple,tomcat,fr500,fr550,frv)) 3915 (.str name "$pack @($GRi,$GRj),$FRintk") 3916 (+ pack FRintk op GRi ope GRj) 3917 (ne-load-semantics GRi (index-of GRj) FRintk 0 size 1 3918 (set FRintk 3919 (c-call mode (.str "@cpu@_read_mem_" mode) 3920 pc (add GRi GRj)))) 3921 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 3922 ) 3923) 3924 3925(ne-load-fr-r nldbf UQI OP_02 OPE1_28 (ne-UQI-size) "Load byte float") 3926(ne-load-fr-r nldhf UHI OP_02 OPE1_29 (ne-UHI-size) "Load half float") 3927(ne-load-fr-r nldf SI OP_02 OPE1_2A (ne-SI-size) "Load word float") 3928 3929; Semantics for a load-double insn 3930; 3931(define-pmacro (load-double-semantics not_gr mode regtype address arg) 3932 (if (orif not_gr (ne (index-of (.sym regtype doublek)) 0)) 3933 (sequence () 3934 (set address (add GRi arg)) 3935 (set (.sym regtype doublek) 3936 (c-call mode (.str "@cpu@_read_mem_" mode) pc address)))) 3937) 3938 3939(define-pmacro (load-double-r-r 3940 name not_gr mode op ope regtype attr profile comment) 3941 (dni name 3942 (comment) 3943 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr) 3944 (.str name "$pack @($GRi,$GRj),$" regtype "doublek") 3945 (+ pack (.sym regtype doublek) op GRi ope GRj) 3946 (sequence ((WI address)) 3947 (load-double-semantics not_gr mode regtype address GRj)) 3948 profile 3949 ) 3950) 3951 3952(load-double-r-r ldd 0 DI OP_02 OPE1_05 GR NA 3953 ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 3954 "Load double word") 3955(load-double-r-r lddf 1 DF OP_02 OPE1_0B FR FR-ACCESS 3956 ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 3957 "Load double float") 3958(load-double-r-r lddc 1 DI OP_02 OPE1_0E CPR (MACH frv) () 3959 "Load coprocessor double") 3960 3961(define-pmacro (ne-load-double-r-r 3962 name not_gr mode op ope regtype size is_float attr profile 3963 comment) 3964 (dni name 3965 (comment) 3966 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr 3967 (MACH simple,tomcat,fr500,fr550,frv)) 3968 (.str name "$pack @($GRi,$GRj),$" regtype "doublek") 3969 (+ pack (.sym regtype doublek) op GRi ope GRj) 3970 (sequence ((WI address)) 3971 (ne-load-semantics GRi (index-of GRj) (.sym regtype doublek) 3972 0 size is_float 3973 (load-double-semantics not_gr mode 3974 regtype 3975 address GRj))) 3976 profile 3977 ) 3978) 3979 3980(ne-load-double-r-r nldd 0 DI OP_02 OPE1_25 GR (ne-DI-size) 0 NA 3981 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load double word") 3982(ne-load-double-r-r nlddf 1 DF OP_02 OPE1_2B FR (ne-DI-size) 1 FR-ACCESS 3983 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load double float") 3984 3985; Semantics for a load-quad insn 3986; 3987(define-pmacro (load-quad-semantics regtype address arg) 3988 (sequence () 3989 (set address (add GRi arg)) 3990 (c-call VOID (.str "@cpu@_load_quad_" regtype) 3991 pc address (index-of (.sym regtype k)))) 3992) 3993 3994(define-pmacro (load-quad-r-r name op ope regtype attr profile comment) 3995 (dni name 3996 (comment) 3997 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr) 3998 (.str name "$pack @($GRi,$GRj),$" regtype "k") 3999 (+ pack (.sym regtype k) op GRi ope GRj) 4000 (sequence ((WI address)) 4001 (load-quad-semantics regtype address GRj)) 4002 ; TODO regtype-k not referenced for profiling 4003 profile 4004 ) 4005) 4006 4007(load-quad-r-r ldq OP_02 OPE1_06 GR NA ((fr500 (unit u-gr-load))) 4008 "Load quad word") 4009(load-quad-r-r ldqf OP_02 OPE1_0C FRint FR-ACCESS ((fr500 (unit u-fr-load))) 4010 "Load quad float") 4011(load-quad-r-r ldqc OP_02 OPE1_0F CPR NA () "Load coprocessor quad") 4012 4013(define-pmacro (ne-load-quad-r-r 4014 name op ope regtype size is_float attr profile comment) 4015 (dni name 4016 (comment) 4017 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING attr) 4018 (.str name "$pack @($GRi,$GRj),$" regtype "k") 4019 (+ pack (.sym regtype k) op GRi ope GRj) 4020 (sequence ((WI address)) 4021 (ne-load-semantics GRi (index-of GRj) (.sym regtype k) 4022 0 size is_float 4023 (load-quad-semantics regtype address GRj))) 4024 ; TODO regtype-k not referenced for profiling 4025 profile 4026 ) 4027) 4028 4029(ne-load-quad-r-r nldq OP_02 OPE1_26 GR (ne-XI-size) 0 NA 4030 ((fr500 (unit u-gr-load))) "Load quad word") 4031(ne-load-quad-r-r nldqf OP_02 OPE1_2C FRint (ne-XI-size) 1 FR-ACCESS 4032 ((fr500 (unit u-fr-load))) "Load quad float") 4033 4034(define-pmacro (load-gr-u-semantics mode) 4035 (sequence ((UWI address)) 4036 (set address (add GRi GRj)) 4037 (set GRk (c-call mode (.str "@cpu@_read_mem_" mode) pc address)) 4038 (if (ne (index-of GRi) (index-of GRk)) 4039 (sequence () 4040 (set GRi address) 4041 (c-call VOID "@cpu@_force_update")))) 4042) 4043 4044(define-pmacro (load-gr-u name mode op ope comment) 4045 (dni name 4046 (comment) 4047 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2)) 4048 (.str name "$pack @($GRi,$GRj),$GRk") 4049 (+ pack GRk op GRi ope GRj) 4050 (load-gr-u-semantics mode) 4051 ((fr400 (unit u-gr-load)) 4052 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4053 ) 4054) 4055 4056(load-gr-u ldsbu QI OP_02 OPE1_10 "Load signed byte, update index") 4057(load-gr-u ldubu UQI OP_02 OPE1_11 "Load unsigned byte, update index") 4058(load-gr-u ldshu HI OP_02 OPE1_12 "Load signed half, update index") 4059(load-gr-u lduhu UHI OP_02 OPE1_13 "Load unsigned half, update index") 4060(load-gr-u ldu SI OP_02 OPE1_14 "Load word, update index") 4061 4062(define-pmacro (ne-load-gr-u name mode op ope size comment) 4063 (dni name 4064 (comment) 4065 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING 4066 (MACH simple,tomcat,fr500,fr550,frv)) 4067 (.str name "$pack @($GRi,$GRj),$GRk") 4068 (+ pack GRk op GRi ope GRj) 4069 (ne-load-semantics GRi (index-of GRj) GRk 0 size 0 (load-gr-u-semantics mode)) 4070 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4071 ) 4072) 4073 4074(ne-load-gr-u nldsbu QI OP_02 OPE1_30 (ne-QI-size) "Load signed byte, update index") 4075(ne-load-gr-u nldubu UQI OP_02 OPE1_31 (ne-UQI-size) "Load unsigned byte, update index") 4076(ne-load-gr-u nldshu HI OP_02 OPE1_32 (ne-HI-size) "Load signed half, update index") 4077(ne-load-gr-u nlduhu UHI OP_02 OPE1_33 (ne-UHI-size) "Load unsigned half, update index") 4078(ne-load-gr-u nldu SI OP_02 OPE1_34 (ne-SI-size) "Load word, update index") 4079 4080(define-pmacro (load-non-gr-u-semantics mode regtype) 4081 (sequence ((UWI address)) 4082 (set address (add GRi GRj)) 4083 (set (.sym regtype k) 4084 (c-call mode (.str "@cpu@_read_mem_" mode) pc address)) 4085 (set GRi address) 4086 (c-call VOID "@cpu@_force_update")) 4087) 4088 4089(define-pmacro (load-fr-u name mode op ope comment) 4090 (dni name 4091 (comment) 4092 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) FR-ACCESS) 4093 (.str name "$pack @($GRi,$GRj),$FRintk") 4094 (+ pack FRintk op GRi ope GRj) 4095 (load-non-gr-u-semantics mode FRint) 4096 ((fr400 (unit u-fr-load)) 4097 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4098 ) 4099) 4100 4101(load-fr-u ldbfu UQI OP_02 OPE1_18 "Load byte float, update index") 4102(load-fr-u ldhfu UHI OP_02 OPE1_19 "Load half float, update index") 4103(load-fr-u ldfu SI OP_02 OPE1_1A "Load word float, update index") 4104 4105(define-pmacro (load-cpr-u name mode op ope comment) 4106 (dni name 4107 (comment) 4108 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv)) 4109 (.str name "$pack @($GRi,$GRj),$CPRk") 4110 (+ pack CPRk op GRi ope GRj) 4111 (load-non-gr-u-semantics mode CPR) 4112 () 4113 ) 4114) 4115 4116(load-cpr-u ldcu SI OP_02 OPE1_1D "Load coprocessor word float,update index") 4117 4118(define-pmacro (ne-load-non-gr-u name mode op ope regtype size comment) 4119 (dni name 4120 (comment) 4121 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS 4122 (MACH simple,tomcat,fr500,fr550,frv)) 4123 (.str name "$pack @($GRi,$GRj),$" regtype "k") 4124 (+ pack (.sym regtype k) op GRi ope GRj) 4125 (ne-load-semantics GRi (index-of GRj) (.sym regtype k) 0 size 1 4126 (load-non-gr-u-semantics mode regtype)) 4127 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4128 ) 4129) 4130 4131(ne-load-non-gr-u nldbfu UQI OP_02 OPE1_38 FRint (ne-UQI-size) "Load byte float, update index") 4132(ne-load-non-gr-u nldhfu UHI OP_02 OPE1_39 FRint (ne-UHI-size) "Load half float, update index") 4133(ne-load-non-gr-u nldfu SI OP_02 OPE1_3A FRint (ne-SI-size) "Load word float, update index") 4134 4135(define-pmacro (load-double-gr-u-semantics) 4136 (sequence ((WI address)) 4137 (load-double-semantics 0 DI GR address GRj) 4138 (if (ne (index-of GRi) (index-of GRdoublek)) 4139 (sequence () 4140 (set GRi address) 4141 (c-call VOID "@cpu@_force_update")))) 4142) 4143 4144(define-pmacro (load-double-gr-u name op ope comment) 4145 (dni name 4146 (comment) 4147 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2)) 4148 (.str name "$pack @($GRi,$GRj),$GRdoublek") 4149 (+ pack GRdoublek op GRi ope GRj) 4150 (load-double-gr-u-semantics) 4151 ((fr400 (unit u-gr-load)) 4152 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4153 ) 4154) 4155 4156(load-double-gr-u lddu OP_02 OPE1_15 "Load double word, update index") 4157 4158(define-pmacro (ne-load-double-gr-u name op ope size comment) 4159 (dni name 4160 (comment) 4161 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING 4162 (MACH simple,tomcat,fr500,fr550,frv)) 4163 (.str name "$pack @($GRi,$GRj),$GRdoublek") 4164 (+ pack GRdoublek op GRi ope GRj) 4165 (ne-load-semantics GRi (index-of GRj) GRdoublek 0 size 0 4166 (load-double-gr-u-semantics)) 4167 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4168 4169 ) 4170) 4171 4172(ne-load-double-gr-u nlddu OP_02 OPE1_35 (ne-DI-size) "Load double word, update index") 4173 4174(define-pmacro (load-double-non-gr-u-semantics mode regtype) 4175 (sequence ((WI address)) 4176 (load-double-semantics 1 mode regtype address GRj) 4177 (set GRi address) 4178 (c-call VOID "@cpu@_force_update")) 4179) 4180 4181(define-pmacro (load-double-non-gr-u 4182 name mode op ope regtype attr profile comment) 4183 (dni name 4184 (comment) 4185 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr) 4186 (.str name "$pack @($GRi,$GRj),$" regtype "doublek") 4187 (+ pack (.sym regtype doublek) op GRi ope GRj) 4188 (load-double-non-gr-u-semantics mode regtype) 4189 profile 4190 ) 4191) 4192 4193(load-double-non-gr-u lddfu DF OP_02 OPE1_1B FR FR-ACCESS 4194 ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4195 "Load double float, update index") 4196(load-double-non-gr-u lddcu DI OP_02 OPE1_1E CPR (MACH frv) 4197 () "Load coprocessor double float, update index") 4198 4199(define-pmacro (ne-load-double-non-gr-u name mode op ope regtype size comment) 4200 (dni name 4201 (comment) 4202 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS 4203 (MACH simple,tomcat,fr500,fr550,frv)) 4204 (.str name "$pack @($GRi,$GRj),$" regtype "doublek") 4205 (+ pack (.sym regtype doublek) op GRi ope GRj) 4206 (ne-load-semantics GRi (index-of GRj) (.sym regtype doublek) 0 size 1 4207 (load-double-non-gr-u-semantics mode regtype)) 4208 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4209 ) 4210) 4211 4212(ne-load-double-non-gr-u nlddfu DF OP_02 OPE1_3B FR (ne-DI-size) "Load double float, update index") 4213 4214(define-pmacro (load-quad-gr-u-semantics) 4215 (sequence ((WI address)) 4216 (load-quad-semantics GR address GRj) 4217 (if (ne (index-of GRi) (index-of GRk)) 4218 (sequence () 4219 (set GRi address) 4220 (c-call VOID "@cpu@_force_update")))) 4221) 4222 4223(define-pmacro (load-quad-gr-u name op ope comment) 4224 (dni name 4225 (comment) 4226 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv)) 4227 (.str name "$pack @($GRi,$GRj),$GRk") 4228 (+ pack GRk op GRi ope GRj) 4229 (load-quad-gr-u-semantics) 4230 ; TODO - GRk not referenced here for profiling 4231 ((fr500 (unit u-gr-load))) 4232 ) 4233) 4234 4235(load-quad-gr-u ldqu OP_02 OPE1_16 "Load quad word, update index") 4236 4237(define-pmacro (ne-load-quad-gr-u name op ope size comment) 4238 (dni name 4239 (comment) 4240 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING) 4241 (.str name "$pack @($GRi,$GRj),$GRk") 4242 (+ pack GRk op GRi ope GRj) 4243 (ne-load-semantics GRi (index-of GRj) GRk 0 size 0 4244 (load-quad-gr-u-semantics)) 4245 ; TODO - GRk not referenced here for profiling 4246 ((fr500 (unit u-gr-load))) 4247 ) 4248) 4249 4250(ne-load-quad-gr-u nldqu OP_02 OPE1_36 (ne-XI-size) "Load quad word, update index") 4251 4252(define-pmacro (load-quad-non-gr-u-semantics regtype) 4253 (sequence ((WI address)) 4254 (load-quad-semantics regtype address GRj) 4255 (set GRi address) 4256 (c-call VOID "@cpu@_force_update")) 4257) 4258 4259(define-pmacro (load-quad-non-gr-u name op ope regtype attr profile comment) 4260 (dni name 4261 (comment) 4262 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr) 4263 (.str name "$pack @($GRi,$GRj),$" regtype "k") 4264 (+ pack (.sym regtype k) op GRi ope GRj) 4265 (load-quad-non-gr-u-semantics regtype) 4266 profile 4267 ) 4268) 4269 4270(load-quad-non-gr-u ldqfu OP_02 OPE1_1C FRint FR-ACCESS 4271 ((fr500 (unit u-fr-load))) "Load quad float, update index") 4272(load-quad-non-gr-u ldqcu OP_02 OPE1_1F CPR NA 4273 () "Load coprocessor quad word, update index") 4274 4275(define-pmacro (ne-load-quad-non-gr-u name op ope regtype size comment) 4276 (dni name 4277 (comment) 4278 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING FR-ACCESS) 4279 (.str name "$pack @($GRi,$GRj),$" regtype "k") 4280 (+ pack (.sym regtype k) op GRi ope GRj) 4281 (ne-load-semantics GRi (index-of GRj) (.sym regtype k) 0 size 1 4282 (load-quad-non-gr-u-semantics regtype)) 4283 ((fr500 (unit u-fr-load))) 4284 ) 4285) 4286 4287(ne-load-quad-non-gr-u nldqfu OP_02 OPE1_3C FRint (ne-XI-size) "Load quad float,update index") 4288 4289(define-pmacro (load-r-simm name mode op regtype attr profile comment) 4290 (dni name 4291 (comment) 4292 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr) 4293 (.str name "$pack @($GRi,$d12),$" regtype "k") 4294 (+ pack (.sym regtype k) op GRi d12) 4295 (set (.sym regtype k) 4296 (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi d12))) 4297 profile 4298 ) 4299) 4300 4301(load-r-simm ldsbi QI OP_30 GR NA 4302 ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4303 "Load signed byte") 4304(load-r-simm ldshi HI OP_31 GR NA 4305 ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4306 "Load signed half") 4307(load-r-simm ldi SI OP_32 GR NA 4308 ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4309 "Load word") 4310(load-r-simm ldubi UQI OP_35 GR NA 4311 ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4312 "Load unsigned byte") 4313(load-r-simm lduhi UHI OP_36 GR NA 4314 ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4315 "Load unsigned half") 4316 4317(load-r-simm ldbfi UQI OP_38 FRint FR-ACCESS 4318 ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4319 "Load byte float") 4320(load-r-simm ldhfi UHI OP_39 FRint FR-ACCESS 4321 ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4322 "Load half float") 4323(load-r-simm ldfi SI OP_3A FRint FR-ACCESS 4324 ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4325 "Load word float") 4326 4327(define-pmacro (ne-load-r-simm 4328 name mode op regtype size is_float attr profile comment) 4329 (dni name 4330 (comment) 4331 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr 4332 (MACH simple,tomcat,fr500,fr550,frv)) 4333 (.str name "$pack @($GRi,$d12),$" regtype "k") 4334 (+ pack (.sym regtype k) op GRi d12) 4335 (ne-load-semantics GRi -1 (.sym regtype k) d12 size is_float 4336 (set (.sym regtype k) 4337 (c-call mode (.str "@cpu@_read_mem_" mode) 4338 pc (add GRi d12)))) 4339 profile 4340 ) 4341) 4342 4343(ne-load-r-simm nldsbi QI OP_40 GR (ne-QI-size) 0 NA 4344 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load signed byte") 4345(ne-load-r-simm nldubi UQI OP_41 GR (ne-UQI-size) 0 NA 4346 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load unsigned byte") 4347(ne-load-r-simm nldshi HI OP_42 GR (ne-HI-size) 0 NA 4348 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load signed half") 4349(ne-load-r-simm nlduhi UHI OP_43 GR (ne-UHI-size) 0 NA 4350 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load unsigned half") 4351(ne-load-r-simm nldi SI OP_44 GR (ne-SI-size) 0 NA 4352 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load word") 4353 4354(ne-load-r-simm nldbfi UQI OP_48 FRint (ne-UQI-size) 1 FR-ACCESS 4355 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load byte float") 4356(ne-load-r-simm nldhfi UHI OP_49 FRint (ne-UHI-size) 1 FR-ACCESS 4357 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load half float") 4358(ne-load-r-simm nldfi SI OP_4A FRint (ne-SI-size) 1 FR-ACCESS 4359 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load word float") 4360 4361(define-pmacro (load-double-r-simm 4362 name not_gr mode op regtype attr profile comment) 4363 (dni name 4364 (comment) 4365 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr) 4366 (.str name "$pack @($GRi,$d12),$" regtype "doublek") 4367 (+ pack (.sym regtype doublek) op GRi d12) 4368 (sequence ((WI address)) 4369 (load-double-semantics not_gr mode regtype address d12)) 4370 profile 4371 ) 4372) 4373 4374(load-double-r-simm lddi 0 DI OP_33 GR NA 4375 ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4376 "Load double word") 4377(load-double-r-simm lddfi 1 DF OP_3B FR FR-ACCESS 4378 ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4379 "Load double float") 4380 4381(define-pmacro (ne-load-double-r-simm 4382 name not_gr mode op regtype size is_float attr profile comment) 4383 (dni name 4384 (comment) 4385 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr 4386 (MACH simple,tomcat,fr500,fr550,frv)) 4387 (.str name "$pack @($GRi,$d12),$" regtype "doublek") 4388 (+ pack (.sym regtype doublek) op GRi d12) 4389 (sequence ((WI address)) 4390 (ne-load-semantics GRi -1 (.sym regtype doublek) 4391 d12 size is_float 4392 (load-double-semantics not_gr mode 4393 regtype 4394 address d12))) 4395 profile 4396 ) 4397) 4398 4399(ne-load-double-r-simm nlddi 0 DI OP_45 GR (ne-DI-size) 0 NA 4400 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load double word") 4401(ne-load-double-r-simm nlddfi 1 DF OP_4B FR (ne-DI-size) 1 FR-ACCESS 4402 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load double float") 4403 4404(define-pmacro (load-quad-r-simm name op regtype attr profile comment) 4405 (dni name 4406 (comment) 4407 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr) 4408 (.str name "$pack @($GRi,$d12),$" regtype "k") 4409 (+ pack (.sym regtype k) op GRi d12) 4410 (sequence ((WI address)) 4411 (load-quad-semantics regtype address d12)) 4412 profile 4413 ) 4414) 4415 4416(load-quad-r-simm ldqi OP_34 GR NA 4417 ((fr500 (unit u-gr-load))) "Load quad word") 4418(load-quad-r-simm ldqfi OP_3C FRint FR-ACCESS 4419 ((fr500 (unit u-fr-load))) "Load quad float") 4420 4421(define-pmacro (ne-load-quad-r-simm 4422 name op regtype size is_float attr profile comment) 4423 (dni name 4424 (comment) 4425 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING attr) 4426 (.str name "$pack @($GRi,$d12),$" regtype "k") 4427 (+ pack (.sym regtype k) op GRi d12) 4428 (sequence ((WI address)) 4429 (ne-load-semantics GRi -1 (.sym regtype k) d12 size is_float 4430 (load-quad-semantics regtype address d12))) 4431 profile 4432 ) 4433) 4434 4435(ne-load-quad-r-simm nldqfi OP_4C FRint (ne-XI-size) 1 FR-ACCESS 4436 ((fr500 (unit u-fr-load))) "Load quad float") 4437 4438(define-pmacro (store-r-r name mode op ope reg attr profile comment) 4439 (dni name 4440 (comment) 4441 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) 4442 (.str name "$pack $" reg "k,@($GRi,$GRj)") 4443 (+ pack (.sym reg k) op GRi ope GRj) 4444 (c-call VOID (.str "@cpu@_write_mem_" mode) 4445 pc (add GRi GRj) (.sym reg k)) 4446 profile 4447 ) 4448) 4449 4450(store-r-r stb QI OP_03 OPE1_00 GR NA 4451 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4452 "Store unsigned byte") 4453(store-r-r sth HI OP_03 OPE1_01 GR NA 4454 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4455 "Store unsigned half") 4456(store-r-r st SI OP_03 OPE1_02 GR NA 4457 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4458 "Store word") 4459 4460(store-r-r stbf QI OP_03 OPE1_08 FRint FR-ACCESS 4461 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4462 "Store byte float") 4463(store-r-r sthf HI OP_03 OPE1_09 FRint FR-ACCESS 4464 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4465 "Store half float") 4466(store-r-r stf SI OP_03 OPE1_0A FRint FR-ACCESS 4467 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4468 "Store word float") 4469 4470(store-r-r stc SI OP_03 OPE1_25 CPR (MACH frv) () "Store coprocessor word") 4471 4472(define-pmacro (r-store name mode op ope reg size is_float profile comment) 4473 (dni name 4474 (comment) 4475 ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv)) 4476 (.str name "$pack $" reg "k,@($GRi,$GRj)") 4477 (+ pack (.sym reg k) op GRi ope GRj) 4478 (sequence ((WI address)) 4479 (set address (add GRi GRj)) 4480 (c-call VOID (.str "@cpu@_write_mem_" mode) 4481 pc address (.sym reg k)) 4482 (c-call VOID "@cpu@_check_recovering_store" 4483 address (index-of (.sym reg k)) size is_float)) 4484 profile 4485 ) 4486) 4487 4488(r-store rstb QI OP_03 OPE1_20 GR 1 0 4489 ((fr500 (unit u-gr-r-store))) "Store unsigned byte") 4490(r-store rsth HI OP_03 OPE1_21 GR 2 0 4491 ((fr500 (unit u-gr-r-store))) "Store unsigned half") 4492(r-store rst SI OP_03 OPE1_22 GR 4 0 4493 ((fr500 (unit u-gr-r-store))) "Store word") 4494 4495(r-store rstbf QI OP_03 OPE1_28 FRint 1 1 4496 ((fr500 (unit u-fr-r-store))) "Store byte float") 4497(r-store rsthf HI OP_03 OPE1_29 FRint 2 1 4498 ((fr500 (unit u-fr-r-store))) "Store half float") 4499(r-store rstf SI OP_03 OPE1_2A FRint 4 1 4500 ((fr500 (unit u-fr-r-store))) "Store word float") 4501 4502; Semantics for a store-double insn 4503; 4504(define-pmacro (store-double-semantics mode regtype address arg) 4505 (sequence () 4506 (set address (add GRi arg)) 4507 (c-call VOID (.str "@cpu@_write_mem_" mode) 4508 pc address (.sym regtype doublek))) 4509) 4510 4511(define-pmacro (store-double-r-r name mode op ope regtype attr profile comment) 4512 (dni name 4513 (comment) 4514 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) 4515 (.str name "$pack $" regtype "doublek,@($GRi,$GRj)") 4516 (+ pack (.sym regtype doublek) op GRi ope GRj) 4517 (sequence ((WI address)) 4518 (store-double-semantics mode regtype address GRj)) 4519 profile 4520 ) 4521) 4522 4523(store-double-r-r std DI OP_03 OPE1_03 GR NA 4524 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4525 "Store double word") 4526(store-double-r-r stdf DF OP_03 OPE1_0B FR FR-ACCESS 4527 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4528 "Store double float") 4529 4530(store-double-r-r stdc DI OP_03 OPE1_26 CPR (MACH frv) 4531 () "Store coprocessor double word") 4532 4533(define-pmacro (r-store-double 4534 name mode op ope regtype is_float attr profile comment) 4535 (dni name 4536 (comment) 4537 ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) 4538 (.str name "$pack $" regtype "doublek,@($GRi,$GRj)") 4539 (+ pack (.sym regtype doublek) op GRi ope GRj) 4540 (sequence ((WI address)) 4541 (store-double-semantics mode regtype address GRj) 4542 (c-call VOID "@cpu@_check_recovering_store" 4543 address (index-of (.sym regtype doublek)) 8 is_float)) 4544 profile 4545 ) 4546) 4547 4548(r-store-double rstd DI OP_03 OPE1_23 GR 0 NA 4549 ((fr500 (unit u-gr-r-store))) "Store double word") 4550(r-store-double rstdf DF OP_03 OPE1_2B FR 1 FR-ACCESS 4551 ((fr500 (unit u-fr-r-store))) "Store double float") 4552 4553; Semantics for a store-quad insn 4554; 4555(define-pmacro (store-quad-semantics regtype address arg) 4556 (sequence () 4557 (set address (add GRi arg)) 4558 (c-call VOID (.str "@cpu@_store_quad_" regtype) 4559 pc address (index-of (.sym regtype k)))) 4560) 4561 4562(define-pmacro (store-quad-r-r name op ope regtype attr profile comment) 4563 (dni name 4564 (comment) 4565 ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) 4566 (.str name "$pack $" regtype "k,@($GRi,$GRj)") 4567 (+ pack (.sym regtype k) op GRi ope GRj) 4568 (sequence ((WI address)) 4569 (store-quad-semantics regtype address GRj)) 4570 profile 4571 ) 4572) 4573 4574(store-quad-r-r stq OP_03 OPE1_04 GR NA 4575 ((fr500 (unit u-gr-store))) "Store quad word") 4576(store-quad-r-r stqf OP_03 OPE1_0C FRint FR-ACCESS 4577 ((fr500 (unit u-fr-store))) 4578 "Store quad float") 4579(store-quad-r-r stqc OP_03 OPE1_27 CPR NA 4580 () "Store coprocessor quad word") 4581 4582(define-pmacro (r-store-quad name op ope regtype is_float attr profile comment) 4583 (dni name 4584 (comment) 4585 ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) 4586 (.str name "$pack $" regtype "k,@($GRi,$GRj)") 4587 (+ pack (.sym regtype k) op GRi ope GRj) 4588 (sequence ((WI address)) 4589 (store-quad-semantics regtype address GRj) 4590 (c-call VOID "@cpu@_check_recovering_store" 4591 address (index-of (.sym regtype k)) 16 is_float)) 4592 profile 4593 ) 4594) 4595 4596(r-store-quad rstq OP_03 OPE1_24 GR 0 NA 4597 ((fr500 (unit u-gr-r-store))) "Store quad word") 4598(r-store-quad rstqf OP_03 OPE1_2C FRint 1 FR-ACCESS 4599 ((fr500 (unit u-fr-r-store))) "Store quad float") 4600 4601(define-pmacro (store-r-r-u name mode op ope regtype attr profile comment) 4602 (dni name 4603 (comment) 4604 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) 4605 (.str name "$pack $" regtype "k,@($GRi,$GRj)") 4606 (+ pack (.sym regtype k) op GRi ope GRj) 4607 (sequence ((UWI address)) 4608 (set address (add GRi GRj)) 4609 (c-call VOID (.str "@cpu@_write_mem_" mode) 4610 pc address (.sym regtype k)) 4611 (set GRi address)) 4612 profile 4613 ) 4614) 4615 4616(store-r-r-u stbu QI OP_03 OPE1_10 GR NA 4617 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4618 "Store unsigned byte, update index") 4619(store-r-r-u sthu HI OP_03 OPE1_11 GR NA 4620 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4621 "Store unsigned half, update index") 4622(store-r-r-u stu WI OP_03 OPE1_12 GR NA 4623 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4624 "Store word, update index") 4625 4626(store-r-r-u stbfu QI OP_03 OPE1_18 FRint FR-ACCESS 4627 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4628 "Store byte float, update index") 4629(store-r-r-u sthfu HI OP_03 OPE1_19 FRint FR-ACCESS 4630 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4631 "Store half float, update index") 4632(store-r-r-u stfu SI OP_03 OPE1_1A FRint FR-ACCESS 4633 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4634 "Store word float, update index") 4635 4636(store-r-r-u stcu SI OP_03 OPE1_2D CPR (MACH frv) () 4637 "Store coprocessor word, update index") 4638 4639(define-pmacro (store-double-r-r-u 4640 name mode op ope regtype attr profile comment) 4641 (dni name 4642 (comment) 4643 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) 4644 (.str name "$pack $" regtype "doublek,@($GRi,$GRj)") 4645 (+ pack (.sym regtype doublek) op GRi ope GRj) 4646 (sequence ((WI address)) 4647 (store-double-semantics mode regtype address GRj) 4648 (set GRi address)) 4649 profile 4650 ) 4651) 4652 4653(store-double-r-r-u stdu DI OP_03 OPE1_13 GR NA 4654 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4655 "Store double word, update index") 4656(store-double-r-r-u stdfu DF OP_03 OPE1_1B FR FR-ACCESS 4657 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4658 "Store double float,update index") 4659(store-double-r-r-u stdcu DI OP_03 OPE1_2E CPR (MACH frv) () 4660 "Store coprocessor double word, update index") 4661 4662(define-pmacro (store-quad-r-r-u name op ope regtype attr profile comment) 4663 (dni name 4664 (comment) 4665 ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) 4666 (.str name "$pack $" regtype "k,@($GRi,$GRj)") 4667 (+ pack (.sym regtype k) op GRi ope GRj) 4668 (sequence ((WI address)) 4669 (store-quad-semantics regtype address GRj) 4670 (set GRi address)) 4671 profile 4672 ) 4673) 4674 4675(store-quad-r-r-u stqu OP_03 OPE1_14 GR NA 4676 ((fr500 (unit u-gr-store))) 4677 "Store quad word, update index") 4678(store-quad-r-r-u stqfu OP_03 OPE1_1C FRint FR-ACCESS 4679 ((fr500 (unit u-fr-store))) 4680 "Store quad float, update index") 4681(store-quad-r-r-u stqcu OP_03 OPE1_2F CPR NA () 4682 "Store coprocessor quad word, update index") 4683 4684(define-pmacro (conditional-load name mode op ope regtype profile comment) 4685 (dni name 4686 (comment) 4687 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL) 4688 (.str name "$pack @($GRi,$GRj),$" regtype "k,$CCi,$cond") 4689 (+ pack (.sym regtype k) op GRi CCi cond ope GRj) 4690 (if (eq CCi (or cond 2)) 4691 (set (.sym regtype k) 4692 (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj)))) 4693 profile 4694 ) 4695) 4696 4697(conditional-load cldsb QI OP_5E OPE4_0 GR 4698 ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4699 "Load signed byte") 4700(conditional-load cldub UQI OP_5E OPE4_1 GR 4701 ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4702 "Load unsigned byte") 4703(conditional-load cldsh HI OP_5E OPE4_2 GR 4704 ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4705 "Load signed half") 4706(conditional-load clduh UHI OP_5E OPE4_3 GR 4707 ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4708 "Load unsigned half") 4709(conditional-load cld SI OP_5F OPE4_0 GR 4710 ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4711 "Load word") 4712 4713(conditional-load cldbf UQI OP_60 OPE4_0 FRint 4714 ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4715 "Load byte float") 4716(conditional-load cldhf UHI OP_60 OPE4_1 FRint 4717 ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4718 "Load half float") 4719(conditional-load cldf SI OP_60 OPE4_2 FRint 4720 ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4721 "Load word float") 4722 4723(define-pmacro (conditional-load-double 4724 name not_gr mode op ope regtype attr profile comment) 4725 (dni name 4726 (comment) 4727 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL attr) 4728 (.str name "$pack @($GRi,$GRj),$" regtype "doublek,$CCi,$cond") 4729 (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) 4730 (if (eq CCi (or cond 2)) 4731 (sequence ((WI address)) 4732 (load-double-semantics not_gr mode regtype address GRj))) 4733 profile 4734 ) 4735) 4736 4737(conditional-load-double cldd 0 DI OP_5F OPE4_1 GR NA 4738 ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4739 "Load double word") 4740(conditional-load-double clddf 1 DF OP_60 OPE4_3 FR FR-ACCESS 4741 ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-fr-load))) 4742 "Load double float") 4743 4744(dni cldq 4745 "conditional load quad integer" 4746 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) CONDITIONAL) 4747 "cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond" 4748 (+ pack GRk OP_5F GRi CCi cond OPE4_2 GRj) 4749 (if (eq CCi (or cond 2)) 4750 (sequence ((WI address)) 4751 (load-quad-semantics GR address GRj))) 4752 ((fr500 (unit u-gr-load))) 4753) 4754 4755(define-pmacro (conditional-load-gr-u name mode op ope comment) 4756 (dni name 4757 (comment) 4758 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL) 4759 (.str name "$pack @($GRi,$GRj),$GRk,$CCi,$cond") 4760 (+ pack GRk op GRi CCi cond ope GRj) 4761 (if (eq CCi (or cond 2)) 4762 (sequence ((WI address)) 4763 (set address (add GRi GRj)) 4764 (set GRk 4765 (c-call mode (.str "@cpu@_read_mem_" mode) 4766 pc address)) 4767 (if (ne (index-of GRi) (index-of GRk)) 4768 (set GRi address)))) 4769 ((fr400 (unit u-gr-load)) 4770 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4771 ) 4772) 4773 4774(conditional-load-gr-u cldsbu QI OP_61 OPE4_0 "Load signed byte, update") 4775(conditional-load-gr-u cldubu UQI OP_61 OPE4_1 "Load unsigned byte, update") 4776(conditional-load-gr-u cldshu HI OP_61 OPE4_2 "Load signed half, update") 4777(conditional-load-gr-u clduhu UHI OP_61 OPE4_3 "Load unsigned half, update") 4778(conditional-load-gr-u cldu SI OP_62 OPE4_0 "Load word, update") 4779 4780(define-pmacro (conditional-load-non-gr-u name mode op ope regtype comment) 4781 (dni name 4782 (comment) 4783 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL FR-ACCESS) 4784 (.str name "$pack @($GRi,$GRj),$" regtype "k,$CCi,$cond") 4785 (+ pack (.sym regtype k) op GRi CCi cond ope GRj) 4786 (if (eq CCi (or cond 2)) 4787 (sequence ((WI address)) 4788 (set address (add GRi GRj)) 4789 (set (.sym regtype k) 4790 (c-call mode (.str "@cpu@_read_mem_" mode) 4791 pc address)) 4792 (set GRi address))) 4793 ((fr400 (unit u-fr-load)) 4794 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4795 ) 4796) 4797 4798(conditional-load-non-gr-u cldbfu UQI OP_63 OPE4_0 FRint "Load byte float, update") 4799(conditional-load-non-gr-u cldhfu UHI OP_63 OPE4_1 FRint "Load half float, update") 4800(conditional-load-non-gr-u cldfu SI OP_63 OPE4_2 FRint "Load word float, update") 4801 4802 4803(dni clddu 4804 "Load double word, update" 4805 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL) 4806 "clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond" 4807 (+ pack GRdoublek OP_62 GRi CCi cond OPE4_1 GRj) 4808 (if (eq CCi (or cond 2)) 4809 (sequence ((WI address)) 4810 (load-double-semantics 0 DI GR address GRj) 4811 (if (ne (index-of GRi) (index-of GRdoublek)) 4812 (set GRi address)))) 4813 ((fr400 (unit u-gr-load)) 4814 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4815) 4816 4817(dni clddfu 4818 "Load double float, update" 4819 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL FR-ACCESS) 4820 "clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond" 4821 (+ pack FRdoublek OP_63 GRi CCi cond OPE4_3 GRj) 4822 (if (eq CCi (or cond 2)) 4823 (sequence ((WI address)) 4824 (load-double-semantics 1 DF FR address GRj) 4825 (set GRi address))) 4826 ((fr400 (unit u-fr-load)) 4827 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4828) 4829 4830(dni cldqu 4831 "conditional load quad integer and update index" 4832 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) CONDITIONAL) 4833 "cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond" 4834 (+ pack GRk OP_62 GRi CCi cond OPE4_2 GRj) 4835 (if (eq CCi (or cond 2)) 4836 (sequence ((WI address)) 4837 (load-quad-semantics GR address GRj) 4838 (if (ne (index-of GRi) (index-of GRk)) 4839 (set GRi address)))) 4840 ((fr500 (unit u-gr-load))) 4841) 4842 4843(define-pmacro (conditional-store name mode op ope regtype profile comment) 4844 (dni name 4845 (comment) 4846 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL) 4847 (.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond") 4848 (+ pack (.sym regtype k) op GRi CCi cond ope GRj) 4849 (if (eq CCi (or cond 2)) 4850 (c-call VOID (.str "@cpu@_write_mem_" mode) 4851 pc (add GRi GRj) (.sym regtype k))) 4852 profile 4853 ) 4854) 4855 4856(conditional-store cstb QI OP_64 OPE4_0 GR 4857 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4858 "Store unsigned byte") 4859(conditional-store csth HI OP_64 OPE4_1 GR 4860 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4861 "Store unsigned half") 4862(conditional-store cst SI OP_64 OPE4_2 GR 4863 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4864 "Store word") 4865 4866(conditional-store cstbf QI OP_66 OPE4_0 FRint 4867 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4868 "Store byte float") 4869(conditional-store csthf HI OP_66 OPE4_1 FRint 4870 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4871 "Store half float") 4872(conditional-store cstf SI OP_66 OPE4_2 FRint 4873 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4874 "Store word float") 4875 4876(define-pmacro (conditional-store-double 4877 name mode op ope regtype attr profile comment) 4878 (dni name 4879 (comment) 4880 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr) 4881 (.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond") 4882 (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) 4883 (if (eq CCi (or cond 2)) 4884 (sequence ((WI address)) 4885 (store-double-semantics mode regtype address GRj))) 4886 profile 4887 ) 4888) 4889 4890(conditional-store-double cstd DI OP_64 OPE4_3 GR NA 4891 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4892 "Store double word") 4893(conditional-store-double cstdf DF OP_66 OPE4_3 FR FR-ACCESS 4894 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4895 "Store double float") 4896 4897(dni cstq 4898 "conditionally store quad word" 4899 ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) CONDITIONAL) 4900 "cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond" 4901 (+ pack GRk OP_65 GRi CCi cond OPE4_0 GRj) 4902 (if (eq CCi (or cond 2)) 4903 (sequence ((WI address)) 4904 (store-quad-semantics GR address GRj))) 4905 ((fr500 (unit u-gr-store))) 4906) 4907 4908(define-pmacro (conditional-store-u 4909 name mode op ope regtype attr profile comment) 4910 (dni name 4911 (comment) 4912 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr) 4913 (.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond") 4914 (+ pack (.sym regtype k) op GRi CCi cond ope GRj) 4915 (if (eq CCi (or cond 2)) 4916 (sequence ((WI address)) 4917 (set address (add GRi GRj)) 4918 (c-call VOID (.str "@cpu@_write_mem_" mode) 4919 pc address (.sym regtype k)) 4920 (set GRi address))) 4921 profile 4922 ) 4923) 4924 4925(conditional-store-u cstbu QI OP_67 OPE4_0 GR NA 4926 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4927 "Store unsigned byte, update index") 4928(conditional-store-u csthu HI OP_67 OPE4_1 GR NA 4929 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4930 "Store unsigned half, update index") 4931(conditional-store-u cstu SI OP_67 OPE4_2 GR NA 4932 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4933 "Store word, update index") 4934 4935(conditional-store-u cstbfu QI OP_68 OPE4_0 FRint FR-ACCESS 4936 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4937 "Store byte float, update index") 4938(conditional-store-u csthfu HI OP_68 OPE4_1 FRint FR-ACCESS 4939 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4940 "Store half float, update index") 4941(conditional-store-u cstfu SI OP_68 OPE4_2 FRint FR-ACCESS 4942 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4943 "Store word float, update index") 4944 4945(define-pmacro (conditional-store-double-u 4946 name mode op ope regtype attr profile comment) 4947 (dni name 4948 (comment) 4949 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr) 4950 (.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond") 4951 (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) 4952 (if (eq CCi (or cond 2)) 4953 (sequence ((WI address)) 4954 (store-double-semantics mode regtype address GRj) 4955 (set GRi address))) 4956 profile 4957 ) 4958) 4959 4960(conditional-store-double-u cstdu DI OP_67 OPE4_3 GR NA 4961 ((fr400 (unit u-gr-store)) 4962 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4963 "Store double word, update index") 4964(conditional-store-double-u cstdfu DF OP_68 OPE4_3 FR FR-ACCESS 4965 ((fr400 (unit u-fr-store)) 4966 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4967 "Store double float, update index") 4968 4969(define-pmacro (store-r-simm name mode op regtype attr profile comment) 4970 (dni name 4971 (comment) 4972 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) 4973 (.str name "$pack $" regtype "k,@($GRi,$d12)") 4974 (+ pack (.sym regtype k) op GRi d12) 4975 (c-call VOID (.str "@cpu@_write_mem_" mode) 4976 pc (add GRi d12) (.sym regtype k)) 4977 profile 4978 ) 4979) 4980 4981(store-r-simm stbi QI OP_50 GR NA 4982 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4983 "Store unsigned byte") 4984(store-r-simm sthi HI OP_51 GR NA 4985 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4986 "Store unsigned half") 4987(store-r-simm sti SI OP_52 GR NA 4988 ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4989 "Store word") 4990 4991(store-r-simm stbfi QI OP_4E FRint FR-ACCESS 4992 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4993 "Store byte float") 4994(store-r-simm sthfi HI OP_4F FRint FR-ACCESS 4995 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4996 "Store half float") 4997(store-r-simm stfi SI OP_55 FRint FR-ACCESS 4998 ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 4999 "Store word float") 5000 5001(define-pmacro (store-double-r-simm name mode op regtype attr profile comment) 5002 (dni name 5003 (comment) 5004 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr) 5005 (.str name "$pack $" regtype "doublek,@($GRi,$d12)") 5006 (+ pack (.sym regtype doublek) op GRi d12) 5007 (sequence ((WI address)) 5008 (store-double-semantics mode regtype address d12)) 5009 profile 5010 ) 5011) 5012 5013(store-double-r-simm stdi DI OP_53 GR NA 5014 ((fr400 (unit u-gr-store)) 5015 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5016 "Store double word") 5017(store-double-r-simm stdfi DF OP_56 FR FR-ACCESS 5018 ((fr400 (unit u-fr-store)) 5019 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5020 "Store double float") 5021 5022(define-pmacro (store-quad-r-simm name op regtype attr profile comment) 5023 (dni name 5024 (comment) 5025 ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) 5026 (.str name "$pack $" regtype "k,@($GRi,$d12)") 5027 (+ pack (.sym regtype k) op GRi d12) 5028 (sequence ((WI address)) 5029 (store-quad-semantics regtype address d12)) 5030 profile 5031 ) 5032) 5033 5034(store-quad-r-simm stqi OP_54 GR NA ((fr500 (unit u-gr-store))) 5035 "Store quad word") 5036(store-quad-r-simm stqfi OP_57 FRint FR-ACCESS () 5037 "Store quad float") 5038 5039(define-pmacro (swap-semantics base offset arg) 5040 (sequence ((WI tmp) (WI address)) 5041 (set tmp arg) 5042 (set address (add base offset)) 5043 (c-call VOID "@cpu@_check_swap_address" address) 5044 (set arg (c-call WI "@cpu@_read_mem_WI" pc address)) 5045 (c-call VOID "@cpu@_write_mem_WI" pc address tmp)) 5046) 5047 5048(dni swap 5049 "Swap contents of memory with GR" 5050 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) 5051 "swap$pack @($GRi,$GRj),$GRk" 5052 (+ pack GRk OP_03 GRi OPE1_05 GRj) 5053 (swap-semantics GRi GRj GRk) 5054 ((fr400 (unit u-swap)) 5055 (fr500 (unit u-swap)) (fr550 (unit u-swap))) 5056) 5057 5058(dni "swapi" 5059 "Swap contents of memory with GR" 5060 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) 5061 ("swapi$pack @($GRi,$d12),$GRk") 5062 (+ pack GRk OP_4D GRi d12) 5063 (swap-semantics GRi d12 GRk) 5064 ((fr400 (unit u-swap)) 5065 (fr500 (unit u-swap)) (fr550 (unit u-swap))) 5066) 5067 5068(dni cswap 5069 "Conditionally swap contents of memory with GR" 5070 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2) CONDITIONAL) 5071 "cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond" 5072 (+ pack GRk OP_65 GRi CCi cond OPE4_2 GRj) 5073 (if (eq CCi (or cond 2)) 5074 (swap-semantics GRi GRj GRk)) 5075 ((fr400 (unit u-swap)) 5076 (fr500 (unit u-swap)) (fr550 (unit u-swap))) 5077) 5078 5079(define-pmacro (register-transfer 5080 name op ope reg_src reg_targ pipe attrs profile comment) 5081 (dni name 5082 (comment) 5083 (.splice (UNIT pipe) (.unsplice attrs)) 5084 (.str name "$pack $" reg_src ",$" reg_targ) 5085 (+ pack reg_targ op (rs-null) ope reg_src) 5086 (set reg_targ reg_src) 5087 profile 5088 ) 5089) 5090 5091(register-transfer movgf OP_03 OPE1_15 5092 GRj FRintk I0 5093 ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS) 5094 ((fr400 (unit u-gr2fr)) (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) 5095 "transfer gr to fr") 5096(register-transfer movfg OP_03 OPE1_0D 5097 FRintk GRj I0 5098 ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS) 5099 ((fr400 (unit u-fr2gr)) (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) 5100 "transfer fr to gr") 5101 5102(define-pmacro (nextreg hw r offset) (reg hw (add (index-of r) offset))) 5103 5104(define-pmacro (register-transfer-double-from-gr-semantics cond) 5105 (if cond 5106 (if (eq (index-of GRj) 0) 5107 (sequence () 5108 (set FRintk 0) 5109 (set (nextreg h-fr_int FRintk 1) 0)) 5110 (sequence () 5111 (set FRintk GRj) 5112 (set (nextreg h-fr_int FRintk 1) (nextreg h-gr GRj 1))))) 5113) 5114 5115(dni movgfd 5116 "move GR for FR double" 5117 ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS) 5118 "movgfd$pack $GRj,$FRintk" 5119 (+ pack FRintk OP_03 (rs-null) OPE1_16 GRj) 5120 (register-transfer-double-from-gr-semantics 1) 5121 ; TODO -- doesn't handle second register in the pair 5122 ((fr400 (unit u-gr2fr)) 5123 (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) 5124) 5125 5126(define-pmacro (register-transfer-double-to-gr-semantics cond) 5127 (if (andif (ne (index-of GRj) 0) cond) 5128 (sequence () 5129 (set GRj FRintk) 5130 (set (nextreg h-gr GRj 1) (nextreg h-fr_int FRintk 1)))) 5131) 5132 5133(dni movfgd 5134 "move FR for GR double" 5135 ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS) 5136 "movfgd$pack $FRintk,$GRj" 5137 (+ pack FRintk OP_03 (rs-null) OPE1_0E GRj) 5138 (register-transfer-double-to-gr-semantics 1) 5139 ; TODO -- doesn't handle second register in the pair 5140 ((fr400 (unit u-fr2gr)) 5141 (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) 5142) 5143 5144(dni movgfq 5145 "move GR for FR quad" 5146 ((UNIT I0) (FR500-MAJOR I-4) (MACH frv) FR-ACCESS) 5147 "movgfq$pack $GRj,$FRintk" 5148 (+ pack FRintk OP_03 (rs-null) OPE1_17 GRj) 5149 (if (eq (index-of GRj) 0) 5150 (sequence () 5151 (set FRintk 0) 5152 (set (reg h-fr_int (add (index-of FRintk) 1)) 0) 5153 (set (reg h-fr_int (add (index-of FRintk) 2)) 0) 5154 (set (reg h-fr_int (add (index-of FRintk) 3)) 0)) 5155 (sequence () 5156 (set FRintk GRj) 5157 (set (reg h-fr_int (add (index-of FRintk) 1)) 5158 (reg h-gr (add (index-of GRj) 1))) 5159 (set (reg h-fr_int (add (index-of FRintk) 2)) 5160 (reg h-gr (add (index-of GRj) 2))) 5161 (set (reg h-fr_int (add (index-of FRintk) 3)) 5162 (reg h-gr (add (index-of GRj) 3))))) 5163 () 5164) 5165 5166(dni movfgq 5167 "move FR for GR quad" 5168 ((UNIT I0) (FR500-MAJOR I-4) (MACH frv) FR-ACCESS) 5169 "movfgq$pack $FRintk,$GRj" 5170 (+ pack FRintk OP_03 (rs-null) OPE1_0F GRj) 5171 (if (ne (index-of GRj) 0) 5172 (sequence () 5173 (set GRj FRintk) 5174 (set (reg h-gr (add (index-of GRj) 1)) 5175 (reg h-fr_int (add (index-of FRintk) 1))) 5176 (set (reg h-gr (add (index-of GRj) 2)) 5177 (reg h-fr_int (add (index-of FRintk) 2))) 5178 (set (reg h-gr (add (index-of GRj) 3)) 5179 (reg h-fr_int (add (index-of FRintk) 3))))) 5180 () 5181) 5182 5183(define-pmacro (conditional-register-transfer 5184 name op ope reg_src reg_targ pipe attrs profile comment) 5185 (dni name 5186 (comment) 5187 (.splice (UNIT pipe) CONDITIONAL FR-ACCESS (.unsplice attrs)) 5188 (.str name "$pack $" reg_src ",$" reg_targ ",$CCi,$cond") 5189 (+ pack reg_targ op (rs-null) CCi cond ope reg_src) 5190 (if (eq CCi (or cond 2)) 5191 (set reg_targ reg_src)) 5192 profile 5193 ) 5194) 5195 5196(conditional-register-transfer cmovgf OP_69 OPE4_0 GRj FRintk I0 5197 ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4)) 5198 ((fr400 (unit u-gr2fr)) (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) 5199 "transfer gr to fr") 5200(conditional-register-transfer cmovfg OP_69 OPE4_2 FRintk GRj I0 5201 ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4)) 5202 ((fr400 (unit u-fr2gr)) (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) 5203 "transfer fr to gr") 5204 5205 5206(dni cmovgfd 5207 "Conditional move GR to FR double" 5208 ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) CONDITIONAL FR-ACCESS) 5209 "cmovgfd$pack $GRj,$FRintk,$CCi,$cond" 5210 (+ pack FRintk OP_69 (rs-null) CCi cond OPE4_1 GRj) 5211 (register-transfer-double-from-gr-semantics (eq CCi (or cond 2))) 5212 ; TODO -- doesn't handle extra registers in double 5213 ((fr400 (unit u-gr2fr)) 5214 (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) 5215) 5216 5217(dni cmovfgd 5218 "Conditional move FR to GR double" 5219 ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) CONDITIONAL FR-ACCESS) 5220 "cmovfgd$pack $FRintk,$GRj,$CCi,$cond" 5221 (+ pack FRintk OP_69 (rs-null) CCi cond OPE4_3 GRj) 5222 (register-transfer-double-to-gr-semantics (eq CCi (or cond 2))) 5223 ; TODO -- doesn't handle second register in the pair 5224 ((fr400 (unit u-fr2gr)) 5225 (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) 5226) 5227 5228(define-pmacro (register-transfer-spr 5229 name op ope reg_src reg_targ unitname comment) 5230 (dni name 5231 (comment) 5232 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) 5233 (.str name "$pack $" reg_src ",$" reg_targ) 5234 (+ pack reg_targ op ope reg_src) 5235 (set reg_targ reg_src) 5236 ((fr400 (unit unitname)) 5237 (fr500 (unit unitname)) (fr550 (unit unitname))) 5238 ) 5239) 5240 5241(register-transfer-spr movgs OP_03 OPE1_06 GRj spr u-gr2spr "transfer gr->spr") 5242(register-transfer-spr movsg OP_03 OPE1_07 spr GRj u-spr2gr "transfer spr->gr") 5243 5244; Integer Branch Conditions 5245(define-pmacro (Inev cc) (const BI 0)) 5246(define-pmacro (Ira cc) (const BI 1)) 5247(define-pmacro (Ieq cc) ( zbit cc)) 5248(define-pmacro (Ine cc) (not (zbit cc))) 5249(define-pmacro (Ile cc) ( orif (zbit cc) (xor (nbit cc) (vbit cc)))) 5250(define-pmacro (Igt cc) (not (orif (zbit cc) (xor (nbit cc) (vbit cc))))) 5251(define-pmacro (Ilt cc) ( xor (nbit cc) (vbit cc))) 5252(define-pmacro (Ige cc) (not (xor (nbit cc) (vbit cc)))) 5253(define-pmacro (Ils cc) ( orif (cbit cc) (zbit cc))) 5254(define-pmacro (Ihi cc) (not (orif (cbit cc) (zbit cc)))) 5255(define-pmacro (Ic cc) ( cbit cc)) 5256(define-pmacro (Inc cc) (not (cbit cc))) 5257(define-pmacro (In cc) ( nbit cc)) 5258(define-pmacro (Ip cc) (not (nbit cc))) 5259(define-pmacro (Iv cc) ( vbit cc)) 5260(define-pmacro (Inv cc) (not (vbit cc))) 5261 5262; Float Branch Conditions 5263(define-pmacro (Fnev cc) (const BI 0)) 5264(define-pmacro (Fra cc) (const BI 1)) 5265(define-pmacro (Fne cc) (orif (lbit cc) (orif (gbit cc) (ubit cc)))) 5266(define-pmacro (Feq cc) (ebit cc)) 5267(define-pmacro (Flg cc) (orif (lbit cc) (gbit cc))) 5268(define-pmacro (Fue cc) (orif (ebit cc) (ubit cc))) 5269(define-pmacro (Ful cc) (orif (lbit cc) (ubit cc))) 5270(define-pmacro (Fge cc) (orif (ebit cc) (gbit cc))) 5271(define-pmacro (Flt cc) (lbit cc)) 5272(define-pmacro (Fuge cc) (orif (ebit cc) (orif (gbit cc) (ubit cc)))) 5273(define-pmacro (Fug cc) (orif (gbit cc) (ubit cc))) 5274(define-pmacro (Fle cc) (orif (ebit cc) (lbit cc))) 5275(define-pmacro (Fgt cc) (gbit cc)) 5276(define-pmacro (Fule cc) (orif (ebit cc) (orif (lbit cc) (ubit cc)))) 5277(define-pmacro (Fu cc) (ubit cc)) 5278(define-pmacro (Fo cc) (orif (ebit cc) (orif (lbit cc) (gbit cc)))) 5279 5280(define-pmacro (conditional-branch-i prefix cc op cond comment) 5281 (dni (.sym prefix cc) 5282 (comment) 5283 ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1)) 5284 (.str (.sym prefix cc) "$pack $ICCi_2,$hint,$label16") 5285 (+ pack (.sym ICC_ cc) ICCi_2 op hint label16) 5286 (sequence () 5287 (c-call VOID "@cpu@_model_branch" label16 hint) 5288 (if (cond ICCi_2) 5289 (set pc label16))) 5290 ((fr400 (unit u-branch)) 5291 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5292 ) 5293) 5294 5295(dni bra 5296 "integer branch equal" 5297 ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1)) 5298 "bra$pack $hint_taken$label16" 5299 (+ pack ICC_ra (ICCi_2-null) OP_06 hint_taken label16) 5300 (sequence () 5301 (c-call VOID "@cpu@_model_branch" label16 hint_taken) 5302 (set pc label16)) 5303 ((fr400 (unit u-branch)) 5304 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5305) 5306 5307(dni bno 5308 "integer branch never" 5309 ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1)) 5310 "bno$pack$hint_not_taken" 5311 (+ pack ICC_nev (ICCi_2-null) OP_06 hint_not_taken (label16-null)) 5312 (c-call VOID "@cpu@_model_branch" label16 hint_not_taken) 5313 ((fr400 (unit u-branch)) 5314 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5315) 5316 5317(conditional-branch-i b eq OP_06 Ieq "integer branch equal") 5318(conditional-branch-i b ne OP_06 Ine "integer branch not equal") 5319(conditional-branch-i b le OP_06 Ile "integer branch less or equal") 5320(conditional-branch-i b gt OP_06 Igt "integer branch greater") 5321(conditional-branch-i b lt OP_06 Ilt "integer branch less") 5322(conditional-branch-i b ge OP_06 Ige "integer branch greater or equal") 5323(conditional-branch-i b ls OP_06 Ils "integer branch less or equal unsigned") 5324(conditional-branch-i b hi OP_06 Ihi "integer branch greater unsigned") 5325(conditional-branch-i b c OP_06 Ic "integer branch carry set") 5326(conditional-branch-i b nc OP_06 Inc "integer branch carry clear") 5327(conditional-branch-i b n OP_06 In "integer branch negative") 5328(conditional-branch-i b p OP_06 Ip "integer branch positive") 5329(conditional-branch-i b v OP_06 Iv "integer branch overflow set") 5330(conditional-branch-i b nv OP_06 Inv "integer branch overflow clear") 5331 5332(define-pmacro (conditional-branch-f prefix cc op cond comment) 5333 (dni (.sym prefix cc) 5334 (comment) 5335 ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1) FR-ACCESS) 5336 (.str (.sym prefix cc) "$pack $FCCi_2,$hint,$label16") 5337 (+ pack (.sym FCC_ cc) FCCi_2 op hint label16) 5338 (sequence () 5339 (c-call VOID "@cpu@_model_branch" label16 hint) 5340 (if (cond FCCi_2) (set pc label16))) 5341 ((fr400 (unit u-branch)) 5342 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5343 ) 5344) 5345 5346(dni fbra 5347 "float branch equal" 5348 ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1) FR-ACCESS) 5349 "fbra$pack $hint_taken$label16" 5350 (+ pack FCC_ra (FCCi_2-null) OP_07 hint_taken label16) 5351 (sequence () 5352 (c-call VOID "@cpu@_model_branch" label16 hint_taken) 5353 (set pc label16)) 5354 ((fr400 (unit u-branch)) 5355 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5356) 5357 5358(dni fbno 5359 "float branch never" 5360 ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1) FR-ACCESS) 5361 "fbno$pack$hint_not_taken" 5362 (+ pack FCC_nev (FCCi_2-null) OP_07 hint_not_taken (label16-null)) 5363 (c-call VOID "@cpu@_model_branch" label16 hint_not_taken) 5364 ((fr400 (unit u-branch)) 5365 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5366) 5367 5368(conditional-branch-f fb ne OP_07 Fne "float branch not equal") 5369(conditional-branch-f fb eq OP_07 Feq "float branch equal") 5370(conditional-branch-f fb lg OP_07 Flg "float branch less or greater") 5371(conditional-branch-f fb ue OP_07 Fue "float branch unordered or equal") 5372(conditional-branch-f fb ul OP_07 Ful "float branch unordered or less") 5373(conditional-branch-f fb ge OP_07 Fge "float branch greater or equal") 5374(conditional-branch-f fb lt OP_07 Flt "float branch less") 5375(conditional-branch-f fb uge OP_07 Fuge "float branch unordered, greater,equal") 5376(conditional-branch-f fb ug OP_07 Fug "float branch unordered or greater") 5377(conditional-branch-f fb le OP_07 Fle "float branch less or equal") 5378(conditional-branch-f fb gt OP_07 Fgt "float branch greater") 5379(conditional-branch-f fb ule OP_07 Fule "float branch unordered, less or equal") 5380(conditional-branch-f fb u OP_07 Fu "float branch unordered") 5381(conditional-branch-f fb o OP_07 Fo "float branch ordered") 5382 5383(define-pmacro (ctrlr-branch-semantics cond ccond) 5384 (sequence ((SI tmp)) 5385 (set tmp (sub (spr-lcr) 1)) 5386 (set (spr-lcr) tmp) 5387 (if cond 5388 (if (eq ccond 0) 5389 (if (ne tmp 0) 5390 (set pc (spr-lr))) 5391 (if (eq tmp 0) 5392 (set pc (spr-lr)))))) 5393) 5394 5395(dni bctrlr 5396 "LCR conditional branch to lr" 5397 ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2)) 5398 ("bctrlr$pack $ccond,$hint") 5399 (+ pack (cond-null) (ICCi_2-null) OP_0E hint OPE3_01 ccond (s12-null)) 5400 (sequence () 5401 (c-call VOID "@cpu@_model_branch" (spr-lr) hint) 5402 (ctrlr-branch-semantics (const BI 1) ccond)) 5403 ((fr400 (unit u-branch)) 5404 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5405) 5406 5407(define-pmacro (conditional-branch-cclr prefix cc i-f op ope cond attr comment) 5408 (dni (.sym prefix cc lr) 5409 (comment) 5410 ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3) attr) 5411 (.str (.sym prefix cc lr) "$pack $" i-f "CCi_2,$hint") 5412 (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op hint ope 5413 (ccond-null) (s12-null)) 5414 (sequence () 5415 (c-call VOID "@cpu@_model_branch" (spr-lr) hint) 5416 (if (cond (.sym i-f CCi_2)) (set pc (spr-lr)))) 5417 ((fr400 (unit u-branch)) 5418 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5419 ) 5420) 5421 5422(dni bralr 5423 "integer cclr branch always" 5424 ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3)) 5425 "bralr$pack$hint_taken" 5426 (+ pack ICC_ra (ICCi_2-null) OP_0E hint_taken OPE3_02 (ccond-null) (s12-null)) 5427 (sequence () 5428 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) 5429 (set pc (spr-lr))) 5430 ((fr400 (unit u-branch)) 5431 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5432) 5433 5434(dni bnolr 5435 "integer cclr branch never" 5436 ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3)) 5437 "bnolr$pack$hint_not_taken" 5438 (+ pack ICC_nev (ICCi_2-null) OP_0E hint_not_taken OPE3_02 (ccond-null) (s12-null)) 5439 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) 5440 ((fr400 (unit u-branch)) 5441 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5442) 5443 5444(conditional-branch-cclr b eq I OP_0E OPE3_02 Ieq NA "integer cclr branch equal") 5445(conditional-branch-cclr b ne I OP_0E OPE3_02 Ine NA "integer cclr branch not equal") 5446(conditional-branch-cclr b le I OP_0E OPE3_02 Ile NA "integer cclr branch less or equal") 5447(conditional-branch-cclr b gt I OP_0E OPE3_02 Igt NA "integer cclr branch greater") 5448(conditional-branch-cclr b lt I OP_0E OPE3_02 Ilt NA "integer cclr branch less") 5449(conditional-branch-cclr b ge I OP_0E OPE3_02 Ige NA "integer cclr branch greater or equal") 5450(conditional-branch-cclr b ls I OP_0E OPE3_02 Ils NA "integer cclr branch less or equal unsigned") 5451(conditional-branch-cclr b hi I OP_0E OPE3_02 Ihi NA "integer cclr branch greater unsigned") 5452(conditional-branch-cclr b c I OP_0E OPE3_02 Ic NA "integer cclr branch carry set") 5453(conditional-branch-cclr b nc I OP_0E OPE3_02 Inc NA "integer cclr branch carry clear") 5454(conditional-branch-cclr b n I OP_0E OPE3_02 In NA "integer cclr branch negative") 5455(conditional-branch-cclr b p I OP_0E OPE3_02 Ip NA "integer cclr branch positive") 5456(conditional-branch-cclr b v I OP_0E OPE3_02 Iv NA "integer cclr branch overflow set") 5457(conditional-branch-cclr b nv I OP_0E OPE3_02 Inv NA "integer cclr branch overflow clear") 5458 5459(dni fbralr 5460 "float cclr branch always" 5461 ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3) FR-ACCESS) 5462 "fbralr$pack$hint_taken" 5463 (+ pack FCC_ra (FCCi_2-null) OP_0E hint_taken OPE3_06 (ccond-null) (s12-null)) 5464 (sequence () 5465 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) 5466 (set pc (spr-lr))) 5467 ((fr400 (unit u-branch)) 5468 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5469) 5470 5471(dni fbnolr 5472 "float cclr branch never" 5473 ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3) FR-ACCESS) 5474 "fbnolr$pack$hint_not_taken" 5475 (+ pack FCC_nev (FCCi_2-null) OP_0E hint_not_taken OPE3_06 (ccond-null) (s12-null)) 5476 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) 5477 ((fr400 (unit u-branch)) 5478 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5479) 5480 5481(conditional-branch-cclr fb eq F OP_0E OPE3_06 Feq FR-ACCESS "float cclr branch equal") 5482(conditional-branch-cclr fb ne F OP_0E OPE3_06 Fne FR-ACCESS "float cclr branch not equal") 5483(conditional-branch-cclr fb lg F OP_0E OPE3_06 Flg FR-ACCESS "float branch less or greater") 5484(conditional-branch-cclr fb ue F OP_0E OPE3_06 Fue FR-ACCESS "float branch unordered or equal") 5485(conditional-branch-cclr fb ul F OP_0E OPE3_06 Ful FR-ACCESS "float branch unordered or less") 5486(conditional-branch-cclr fb ge F OP_0E OPE3_06 Fge FR-ACCESS "float branch greater or equal") 5487(conditional-branch-cclr fb lt F OP_0E OPE3_06 Flt FR-ACCESS "float branch less") 5488(conditional-branch-cclr fb uge F OP_0E OPE3_06 Fuge FR-ACCESS "float branch unordered, greater, equal") 5489(conditional-branch-cclr fb ug F OP_0E OPE3_06 Fug FR-ACCESS "float branch unordered or greater") 5490(conditional-branch-cclr fb le F OP_0E OPE3_06 Fle FR-ACCESS "float branch less or equal") 5491(conditional-branch-cclr fb gt F OP_0E OPE3_06 Fgt FR-ACCESS "float branch greater") 5492(conditional-branch-cclr fb ule F OP_0E OPE3_06 Fule FR-ACCESS "float branch unordered, less or equal") 5493(conditional-branch-cclr fb u F OP_0E OPE3_06 Fu FR-ACCESS "float branch unordered") 5494(conditional-branch-cclr fb o F OP_0E OPE3_06 Fo FR-ACCESS "float branch ordered") 5495 5496(define-pmacro (conditional-branch-ctrlr prefix cc i-f op ope cond attr comment) 5497 (dni (.sym prefix cc lr) 5498 (comment) 5499 ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2) attr) 5500 (.str (.sym prefix cc lr) "$pack $" i-f "CCi_2,$ccond,$hint") 5501 (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op hint ope ccond (s12-null)) 5502 (sequence () 5503 (c-call VOID "@cpu@_model_branch" (spr-lr) hint) 5504 (ctrlr-branch-semantics (cond (.sym i-f CCi_2)) ccond)) 5505 ((fr400 (unit u-branch)) 5506 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5507 ) 5508) 5509 5510(dni bcralr 5511 "integer ctrlr branch always" 5512 ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2)) 5513 "bcralr$pack $ccond$hint_taken" 5514 (+ pack ICC_ra (ICCi_2-null) OP_0E hint_taken OPE3_03 ccond (s12-null)) 5515 (sequence () 5516 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) 5517 (ctrlr-branch-semantics (const BI 1) ccond)) 5518 ((fr400 (unit u-branch)) 5519 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5520) 5521 5522(dni bcnolr 5523 "integer ctrlr branch never" 5524 ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2)) 5525 "bcnolr$pack$hint_not_taken" 5526 (+ pack ICC_nev (ICCi_2-null) OP_0E hint_not_taken OPE3_03 (ccond-null) (s12-null)) 5527 (sequence () 5528 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) 5529 (ctrlr-branch-semantics (const BI 0) ccond)) 5530 ((fr400 (unit u-branch)) 5531 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5532) 5533 5534(conditional-branch-ctrlr bc eq I OP_0E OPE3_03 Ieq NA "integer ctrlr branch equal") 5535(conditional-branch-ctrlr bc ne I OP_0E OPE3_03 Ine NA "integer ctrlr branch not equal") 5536(conditional-branch-ctrlr bc le I OP_0E OPE3_03 Ile NA "integer ctrlr branch less equal") 5537(conditional-branch-ctrlr bc gt I OP_0E OPE3_03 Igt NA "integer ctrlr branch greater") 5538(conditional-branch-ctrlr bc lt I OP_0E OPE3_03 Ilt NA "integer ctrlr branch less") 5539(conditional-branch-ctrlr bc ge I OP_0E OPE3_03 Ige NA "integer ctrlr branch greater equal") 5540(conditional-branch-ctrlr bc ls I OP_0E OPE3_03 Ils NA "integer ctrlr branch less equal unsigned") 5541(conditional-branch-ctrlr bc hi I OP_0E OPE3_03 Ihi NA "integer ctrlr branch greater unsigned") 5542(conditional-branch-ctrlr bc c I OP_0E OPE3_03 Ic NA "integer ctrlr branch carry set") 5543(conditional-branch-ctrlr bc nc I OP_0E OPE3_03 Inc NA "integer ctrlr branch carry clear") 5544(conditional-branch-ctrlr bc n I OP_0E OPE3_03 In NA "integer ctrlr branch negative") 5545(conditional-branch-ctrlr bc p I OP_0E OPE3_03 Ip NA "integer ctrlr branch positive") 5546(conditional-branch-ctrlr bc v I OP_0E OPE3_03 Iv NA "integer ctrlr branch overflow set") 5547(conditional-branch-ctrlr bc nv I OP_0E OPE3_03 Inv NA "integer ctrlr branch overflow clear") 5548 5549(dni fcbralr 5550 "float ctrlr branch always" 5551 ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2) FR-ACCESS) 5552 "fcbralr$pack $ccond$hint_taken" 5553 (+ pack FCC_ra (FCCi_2-null) OP_0E hint_taken OPE3_07 ccond (s12-null)) 5554 (sequence () 5555 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) 5556 (ctrlr-branch-semantics (const BI 1) ccond)) 5557 ((fr400 (unit u-branch)) 5558 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5559) 5560 5561(dni fcbnolr 5562 "float ctrlr branch never" 5563 ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2) FR-ACCESS) 5564 "fcbnolr$pack$hint_not_taken" 5565 (+ pack FCC_nev (FCCi_2-null) OP_0E hint_not_taken OPE3_07 (ccond-null) (s12-null)) 5566 (sequence () 5567 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) 5568 (ctrlr-branch-semantics (const BI 0) ccond)) 5569 ((fr400 (unit u-branch)) 5570 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5571) 5572 5573(conditional-branch-ctrlr fcb eq F OP_0E OPE3_07 Feq FR-ACCESS "float cclr branch equal") 5574(conditional-branch-ctrlr fcb ne F OP_0E OPE3_07 Fne FR-ACCESS "float cclr branch not equal") 5575(conditional-branch-ctrlr fcb lg F OP_0E OPE3_07 Flg FR-ACCESS "float branch less or greater") 5576(conditional-branch-ctrlr fcb ue F OP_0E OPE3_07 Fue FR-ACCESS "float branch unordered or equal") 5577(conditional-branch-ctrlr fcb ul F OP_0E OPE3_07 Ful FR-ACCESS "float branch unordered or less") 5578(conditional-branch-ctrlr fcb ge F OP_0E OPE3_07 Fge FR-ACCESS "float branch greater or equal") 5579(conditional-branch-ctrlr fcb lt F OP_0E OPE3_07 Flt FR-ACCESS "float branch less") 5580(conditional-branch-ctrlr fcb uge F OP_0E OPE3_07 Fuge FR-ACCESS "float branch unordered, greater, equal") 5581(conditional-branch-ctrlr fcb ug F OP_0E OPE3_07 Fug FR-ACCESS "float branch unordered or greater") 5582(conditional-branch-ctrlr fcb le F OP_0E OPE3_07 Fle FR-ACCESS "float branch less or equal") 5583(conditional-branch-ctrlr fcb gt F OP_0E OPE3_07 Fgt FR-ACCESS "float branch greater") 5584(conditional-branch-ctrlr fcb ule F OP_0E OPE3_07 Fule FR-ACCESS "float branch unordered, less or equal") 5585(conditional-branch-ctrlr fcb u F OP_0E OPE3_07 Fu FR-ACCESS "float branch unordered") 5586(conditional-branch-ctrlr fcb o F OP_0E OPE3_07 Fo FR-ACCESS "float branch ordered") 5587 5588(define-pmacro (jump-and-link-semantics base offset LI) 5589 (sequence () 5590 (if (eq LI 1) 5591 (c-call VOID "@cpu@_set_write_next_vliw_addr_to_LR" 1)) 5592 ; Target address gets aligned here 5593 (set pc (and (add base offset) #xfffffffc)) 5594 (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken 5595) 5596 5597(dni jmpl 5598 "jump and link" 5599 ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5)) 5600 "jmpl$pack @($GRi,$GRj)" 5601 (+ pack (misc-null-1) (LI-off) OP_0C GRi (misc-null-2) GRj) 5602 (jump-and-link-semantics GRi GRj LI) 5603 ((fr400 (unit u-branch)) 5604 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5605) 5606 5607(dni calll 5608 "call and link" 5609 ((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5)) 5610 "calll$pack @($GRi,$GRj)" 5611 (+ pack (misc-null-1) (LI-on) OP_0C GRi (misc-null-2) GRj) 5612 (jump-and-link-semantics GRi GRj LI) 5613 ((fr400 (unit u-branch)) 5614 (fr500 (unit u-branch))) 5615) 5616 5617(dni jmpil 5618 "jump immediate and link" 5619 ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5)) 5620 "jmpil$pack @($GRi,$s12)" 5621 (+ pack (misc-null-1) (LI-off) OP_0D GRi s12) 5622 (jump-and-link-semantics GRi s12 LI) 5623 ((fr400 (unit u-branch)) 5624 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5625) 5626 5627(dni callil 5628 "call immediate and link" 5629 ((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5)) 5630 "callil$pack @($GRi,$s12)" 5631 (+ pack (misc-null-1) (LI-on) OP_0D GRi s12) 5632 (jump-and-link-semantics GRi s12 LI) 5633 ((fr400 (unit u-branch)) 5634 (fr500 (unit u-branch))) 5635) 5636 5637(dni call 5638 "call and link" 5639 ((UNIT B0) (FR500-MAJOR B-4) (FR550-MAJOR B-4) (FR400-MAJOR B-4)) 5640 "call$pack $label24" 5641 (+ pack OP_0F label24) 5642 (sequence () 5643 (c-call VOID "@cpu@_set_write_next_vliw_addr_to_LR" 1) 5644 (set pc label24) 5645 (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken 5646 ((fr400 (unit u-branch)) 5647 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5648) 5649 5650(dni rett 5651 "return from trap" 5652 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2) PRIVILEGED) 5653 "rett$pack $debug" 5654 (+ pack (misc-null-1) debug OP_05 (rs-null) (s12-null)) 5655 ; frv_rett handles operating vs user mode 5656 (sequence () 5657 (set pc (c-call UWI "frv_rett" pc debug)) 5658 (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken 5659 () 5660) 5661 5662(dni rei 5663 "run exception instruction" 5664 ((UNIT C) (FR500-MAJOR C-1) (MACH frv) PRIVILEGED) 5665 "rei$pack $eir" 5666 (+ pack (rd-null) OP_37 eir (s12-null)) 5667 (nop) ; for now 5668 () 5669) 5670 5671(define-pmacro (trap-semantics cond base offset) 5672 (if cond 5673 (sequence () 5674 ; This is defered to frv_itrap because for the breakpoint 5675 ; case we want to change as little of the machine state as 5676 ; possible. 5677 ; 5678 ; PCSR=PC 5679 ; PSR.PS=PSR.S 5680 ; PSR.ET=0 5681 ; if PSR.ESR==1 5682 ; SR0 through SR3=GR4 through GR7 5683 ; TBR.TT=0x80 + ((GRi + s12) & 0x7f) 5684 ; PC=TBR 5685 ; We still should indicate what is modified by this insn. 5686 (clobber (spr-pcsr)) 5687 (clobber psr_ps) 5688 (clobber psr_et) 5689 (clobber tbr_tt) 5690 (if (ne psr_esr (const 0)) 5691 (sequence () 5692 (clobber (spr-sr0)) 5693 (clobber (spr-sr1)) 5694 (clobber (spr-sr2)) 5695 (clobber (spr-sr3)))) 5696 ; frv_itrap handles operating vs user mode 5697 (c-call VOID "frv_itrap" pc base offset))) 5698) 5699 5700(define-pmacro (trap-r prefix cc i-f op ope cond attr comment) 5701 (dni (.sym prefix cc) 5702 (comment) 5703 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) attr) 5704 (.str (.sym prefix cc) "$pack $" i-f "CCi_2,$GRi,$GRj") 5705 (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op GRi (misc-null-3) ope GRj) 5706 (trap-semantics (cond (.sym i-f CCi_2)) GRi GRj) 5707 ((fr400 (unit u-trap)) 5708 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 5709 ) 5710) 5711 5712(dni tra 5713 "integer trap always" 5714 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) 5715 "tra$pack $GRi,$GRj" 5716 (+ pack ICC_ra (ICCi_2-null) OP_04 GRi (misc-null-3) OPE4_0 GRj) 5717 (trap-semantics (const BI 1) GRi GRj) 5718 ((fr400 (unit u-trap)) 5719 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 5720) 5721 5722(dni tno 5723 "integer trap never" 5724 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) 5725 "tno$pack" 5726 (+ pack ICC_nev (ICCi_2-null) OP_04 (GRi-null) (misc-null-3) OPE4_0 (GRj-null)) 5727 (trap-semantics (const BI 0) GRi GRj) 5728 ((fr400 (unit u-trap)) 5729 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 5730) 5731 5732(trap-r t eq I OP_04 OPE4_0 Ieq NA "integer trap equal") 5733(trap-r t ne I OP_04 OPE4_0 Ine NA "integer trap not equal") 5734(trap-r t le I OP_04 OPE4_0 Ile NA "integer trap less or equal") 5735(trap-r t gt I OP_04 OPE4_0 Igt NA "integer trap greater") 5736(trap-r t lt I OP_04 OPE4_0 Ilt NA "integer trap less") 5737(trap-r t ge I OP_04 OPE4_0 Ige NA "integer trap greater or equal") 5738(trap-r t ls I OP_04 OPE4_0 Ils NA "integer trap less or equal unsigned") 5739(trap-r t hi I OP_04 OPE4_0 Ihi NA "integer trap greater unsigned") 5740(trap-r t c I OP_04 OPE4_0 Ic NA "integer trap carry set") 5741(trap-r t nc I OP_04 OPE4_0 Inc NA "integer trap carry clear") 5742(trap-r t n I OP_04 OPE4_0 In NA "integer trap negative") 5743(trap-r t p I OP_04 OPE4_0 Ip NA "integer trap positive") 5744(trap-r t v I OP_04 OPE4_0 Iv NA "integer trap overflow set") 5745(trap-r t nv I OP_04 OPE4_0 Inv NA "integer trap overflow clear") 5746 5747(dni ftra 5748 "float trap always" 5749 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) 5750 "ftra$pack $GRi,$GRj" 5751 (+ pack FCC_ra (FCCi_2-null) OP_04 GRi (misc-null-3) OPE4_1 GRj) 5752 (trap-semantics (const BI 1) GRi GRj) 5753 ((fr400 (unit u-trap)) 5754 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 5755) 5756 5757(dni ftno 5758 "flost trap never" 5759 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) 5760 "ftno$pack" 5761 (+ pack FCC_nev (FCCi_2-null) OP_04 (GRi-null) (misc-null-3) OPE4_1 (GRj-null)) 5762 (trap-semantics (const BI 0) GRi GRj) 5763 ((fr400 (unit u-trap)) 5764 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 5765) 5766 5767(trap-r ft ne F OP_04 OPE4_1 Fne FR-ACCESS "float trap not equal") 5768(trap-r ft eq F OP_04 OPE4_1 Feq FR-ACCESS "float trap equal") 5769(trap-r ft lg F OP_04 OPE4_1 Flg FR-ACCESS "float trap greater or less") 5770(trap-r ft ue F OP_04 OPE4_1 Fue FR-ACCESS "float trap unordered or equal") 5771(trap-r ft ul F OP_04 OPE4_1 Ful FR-ACCESS "float trap unordered or less") 5772(trap-r ft ge F OP_04 OPE4_1 Fge FR-ACCESS "float trap greater or equal") 5773(trap-r ft lt F OP_04 OPE4_1 Flt FR-ACCESS "float trap less") 5774(trap-r ft uge F OP_04 OPE4_1 Fuge FR-ACCESS "float trap unordered greater or equal") 5775(trap-r ft ug F OP_04 OPE4_1 Fug FR-ACCESS "float trap unordered or greater") 5776(trap-r ft le F OP_04 OPE4_1 Fle FR-ACCESS "float trap less or equal") 5777(trap-r ft gt F OP_04 OPE4_1 Fgt FR-ACCESS "float trap greater") 5778(trap-r ft ule F OP_04 OPE4_1 Fule FR-ACCESS "float trap unordered less or equal") 5779(trap-r ft u F OP_04 OPE4_1 Fu FR-ACCESS "float trap unordered") 5780(trap-r ft o F OP_04 OPE4_1 Fo FR-ACCESS "float trap ordered") 5781 5782(define-pmacro (trap-immed prefix cc i-f op cond attr comment) 5783 (dni (.sym prefix cc) 5784 (comment) 5785 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) attr) 5786 (.str (.sym prefix cc) "$pack $" i-f "CCi_2,$GRi,$s12") 5787 (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op GRi s12) 5788 (trap-semantics (cond (.sym i-f CCi_2)) GRi s12) 5789 ((fr400 (unit u-trap)) 5790 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 5791 ) 5792) 5793 5794(dni tira 5795 "integer trap always" 5796 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) 5797 "tira$pack $GRi,$s12" 5798 (+ pack ICC_ra (ICCi_2-null) OP_1C GRi s12) 5799 (trap-semantics (const BI 1) GRi s12) 5800 ((fr400 (unit u-trap)) 5801 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 5802) 5803 5804(dni tino 5805 "integer trap never" 5806 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) 5807 "tino$pack" 5808 (+ pack ICC_nev (ICCi_2-null) OP_1C (GRi-null) (s12-null)) 5809 (trap-semantics (const BI 0) GRi s12) 5810 ((fr400 (unit u-trap)) 5811 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 5812) 5813 5814(trap-immed ti eq I OP_1C Ieq NA "integer trap equal") 5815(trap-immed ti ne I OP_1C Ine NA "integer trap not equal") 5816(trap-immed ti le I OP_1C Ile NA "integer trap less or equal") 5817(trap-immed ti gt I OP_1C Igt NA "integer trap greater") 5818(trap-immed ti lt I OP_1C Ilt NA "integer trap less") 5819(trap-immed ti ge I OP_1C Ige NA "integer trap greater or equal") 5820(trap-immed ti ls I OP_1C Ils NA "integer trap less or equal unsigned") 5821(trap-immed ti hi I OP_1C Ihi NA "integer trap greater unsigned") 5822(trap-immed ti c I OP_1C Ic NA "integer trap carry set") 5823(trap-immed ti nc I OP_1C Inc NA "integer trap carry clear") 5824(trap-immed ti n I OP_1C In NA "integer trap negative") 5825(trap-immed ti p I OP_1C Ip NA "integer trap positive") 5826(trap-immed ti v I OP_1C Iv NA "integer trap overflow set") 5827(trap-immed ti nv I OP_1C Inv NA "integer trap overflow clear") 5828 5829(dni ftira 5830 "float trap always" 5831 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) 5832 "ftira$pack $GRi,$s12" 5833 (+ pack FCC_ra (ICCi_2-null) OP_1D GRi s12) 5834 (trap-semantics (const BI 1) GRi s12) 5835 ((fr400 (unit u-trap)) 5836 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 5837) 5838 5839(dni ftino 5840 "float trap never" 5841 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) 5842 "ftino$pack" 5843 (+ pack FCC_nev (FCCi_2-null) OP_1D (GRi-null) (s12-null)) 5844 (trap-semantics (const BI 0) GRi s12) 5845 ((fr400 (unit u-trap)) 5846 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 5847) 5848 5849(trap-immed fti ne F OP_1D Fne FR-ACCESS "float trap not equal") 5850(trap-immed fti eq F OP_1D Feq FR-ACCESS "float trap equal") 5851(trap-immed fti lg F OP_1D Flg FR-ACCESS "float trap greater or less") 5852(trap-immed fti ue F OP_1D Fue FR-ACCESS "float trap unordered or equal") 5853(trap-immed fti ul F OP_1D Ful FR-ACCESS "float trap unordered or less") 5854(trap-immed fti ge F OP_1D Fge FR-ACCESS "float trap greater or equal") 5855(trap-immed fti lt F OP_1D Flt FR-ACCESS "float trap less") 5856(trap-immed fti uge F OP_1D Fuge FR-ACCESS "float trap unordered greater or equal") 5857(trap-immed fti ug F OP_1D Fug FR-ACCESS "float trap unordered or greater") 5858(trap-immed fti le F OP_1D Fle FR-ACCESS "float trap less or equal") 5859(trap-immed fti gt F OP_1D Fgt FR-ACCESS "float trap greater") 5860(trap-immed fti ule F OP_1D Fule FR-ACCESS "float trap unordered less or equal") 5861(trap-immed fti u F OP_1D Fu FR-ACCESS "float trap unordered") 5862(trap-immed fti o F OP_1D Fo FR-ACCESS "float trap ordered") 5863 5864(dni break 5865 "break trap" 5866 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1)) 5867 "break$pack" 5868 (+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_3 (GRj-null)) 5869 (sequence () 5870 ; This is defered to frv_break because for the breakpoint 5871 ; case we want to change as little of the machine state as 5872 ; possible. 5873 ; 5874 ; BPCSR=PC 5875 ; BPSR.BS=PSR.S 5876 ; BPSR.BET=PSR.ET 5877 ; PSR.S=1 5878 ; PSR.ET=0 5879 ; TBR.TT=0xff 5880 ; PC=TBR 5881 ; We still should indicate what is modified by this insn. 5882 (clobber (spr-bpcsr)) 5883 (clobber bpsr_bs) 5884 (clobber bpsr_bet) 5885 (clobber psr_s) 5886 (clobber psr_et) 5887 (clobber tbr_tt) 5888 (c-call VOID "frv_break")) 5889 () 5890) 5891 5892(dni mtrap 5893 "media trap" 5894 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS) 5895 "mtrap$pack" 5896 (+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_2 (GRj-null)) 5897 (c-call VOID "frv_mtrap") 5898 () 5899) 5900 5901(define-pmacro (condition-code-logic name operation ope comment) 5902 (dni name 5903 (comment) 5904 ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6) (FR400-MAJOR B-6)) 5905 (.str name "$pack $CRi,$CRj,$CRk") 5906 (+ pack (misc-null-6) CRk OP_0A (misc-null-7) CRi ope (misc-null-8) CRj) 5907 (set CRk (c-call UQI "@cpu@_cr_logic" operation CRi CRj)) 5908 () 5909 ) 5910) 5911(define-pmacro (op-andcr) 0) 5912(define-pmacro (op-orcr) 1) 5913(define-pmacro (op-xorcr) 2) 5914(define-pmacro (op-nandcr) 3) 5915(define-pmacro (op-norcr) 4) 5916(define-pmacro (op-andncr) 5) 5917(define-pmacro (op-orncr) 6) 5918(define-pmacro (op-nandncr) 7) 5919(define-pmacro (op-norncr) 8) 5920 5921(define-pmacro (cr-true) 3) 5922(define-pmacro (cr-false) 2) 5923(define-pmacro (cr-undefined) 0) 5924 5925(condition-code-logic andcr (op-andcr) OPE1_08 "and condition code regs") 5926(condition-code-logic orcr (op-orcr) OPE1_09 "or condition code regs") 5927(condition-code-logic xorcr (op-xorcr) OPE1_0A "xor condition code regs") 5928(condition-code-logic nandcr (op-nandcr) OPE1_0C "nand condition code regs") 5929(condition-code-logic norcr (op-norcr) OPE1_0D "nor condition code regs") 5930(condition-code-logic andncr (op-andncr) OPE1_10 "andn condition code regs") 5931(condition-code-logic orncr (op-orncr) OPE1_11 "orn condition code regs") 5932(condition-code-logic nandncr (op-nandncr) OPE1_14 "nandn condition code regs") 5933(condition-code-logic norncr (op-norncr) OPE1_15 "norn condition code regs") 5934 5935(dni notcr 5936 ("not cccr register") 5937 ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6) (FR400-MAJOR B-6)) 5938 (.str notcr "$pack $CRj,$CRk") 5939 (+ pack (misc-null-6) CRk OP_0A (rs-null) OPE1_0B (misc-null-8) CRj) 5940 (set CRk (xor CRj 1)) 5941 () 5942) 5943 5944(define-pmacro (check-semantics cond cr) 5945 (if cond (set cr (cr-true)) (set cr (cr-false))) 5946) 5947 5948(define-pmacro (check-int-condition-code prefix cc op cond comment) 5949 (dni (.sym prefix cc) 5950 (comment) 5951 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5)) 5952 (.str (.sym prefix cc) "$pack $ICCi_3,$CRj_int") 5953 (+ pack (.sym ICC_ cc) CRj_int op (misc-null-5) ICCi_3) 5954 (check-semantics (cond ICCi_3) CRj_int) 5955 ((fr400 (unit u-check)) 5956 (fr500 (unit u-check)) (fr550 (unit u-check))) 5957 ) 5958) 5959 5960(dni ckra 5961 "check integer cc always" 5962 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5)) 5963 "ckra$pack $CRj_int" 5964 (+ pack ICC_ra CRj_int OP_08 (misc-null-5) (ICCi_3-null)) 5965 (check-semantics (const BI 1) CRj_int) 5966 ((fr400 (unit u-check)) 5967 (fr500 (unit u-check)) (fr550 (unit u-check))) 5968) 5969 5970(dni ckno 5971 "check integer cc never" 5972 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5)) 5973 "ckno$pack $CRj_int" 5974 (+ pack ICC_nev CRj_int OP_08 (misc-null-5) (ICCi_3-null)) 5975 (check-semantics (const BI 0) CRj_int) 5976 ((fr400 (unit u-check)) 5977 (fr500 (unit u-check)) (fr550 (unit u-check))) 5978) 5979 5980(check-int-condition-code ck eq OP_08 Ieq "check integer cc equal") 5981(check-int-condition-code ck ne OP_08 Ine "check integer cc not equal") 5982(check-int-condition-code ck le OP_08 Ile "check integer cc less or equal") 5983(check-int-condition-code ck gt OP_08 Igt "check integer cc greater") 5984(check-int-condition-code ck lt OP_08 Ilt "check integer cc less") 5985(check-int-condition-code ck ge OP_08 Ige "check integer cc greater or equal") 5986(check-int-condition-code ck ls OP_08 Ils "check integer cc less or equal unsigned") 5987(check-int-condition-code ck hi OP_08 Ihi "check integer cc greater unsigned") 5988(check-int-condition-code ck c OP_08 Ic "check integer cc carry set") 5989(check-int-condition-code ck nc OP_08 Inc "check integer cc carry clear") 5990(check-int-condition-code ck n OP_08 In "check integer cc negative") 5991(check-int-condition-code ck p OP_08 Ip "check integer cc positive") 5992(check-int-condition-code ck v OP_08 Iv "check integer cc overflow set") 5993(check-int-condition-code ck nv OP_08 Inv "check integer cc overflow clear") 5994 5995(define-pmacro (check-float-condition-code prefix cc op cond comment) 5996 (dni (.sym prefix cc) 5997 (comment) 5998 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) FR-ACCESS) 5999 (.str (.sym prefix cc) "$pack $FCCi_3,$CRj_float") 6000 (+ pack (.sym FCC_ cc) CRj_float op (misc-null-5) FCCi_3) 6001 (check-semantics (cond FCCi_3) CRj_float) 6002 ((fr400 (unit u-check)) 6003 (fr500 (unit u-check)) (fr550 (unit u-check))) 6004 ) 6005) 6006 6007(dni fckra 6008 "check float cc always" 6009 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) FR-ACCESS) 6010 "fckra$pack $CRj_float" 6011 (+ pack FCC_ra CRj_float OP_09 (misc-null-5) FCCi_3) 6012 (check-semantics (const BI 1) CRj_float) 6013 ((fr400 (unit u-check)) 6014 (fr500 (unit u-check)) (fr550 (unit u-check))) 6015) 6016 6017(dni fckno 6018 "check float cc never" 6019 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) FR-ACCESS) 6020 "fckno$pack $CRj_float" 6021 (+ pack FCC_nev CRj_float OP_09 (misc-null-5) FCCi_3) 6022 (check-semantics (const BI 0) CRj_float) 6023 ((fr400 (unit u-check)) 6024 (fr500 (unit u-check)) (fr550 (unit u-check))) 6025) 6026 6027(check-float-condition-code fck ne OP_09 Fne "check float cc not equal") 6028(check-float-condition-code fck eq OP_09 Feq "check float cc equal") 6029(check-float-condition-code fck lg OP_09 Flg "check float cc greater or less") 6030(check-float-condition-code fck ue OP_09 Fue "check float cc unordered or equal") 6031(check-float-condition-code fck ul OP_09 Ful "check float cc unordered or less") 6032(check-float-condition-code fck ge OP_09 Fge "check float cc greater or equal") 6033(check-float-condition-code fck lt OP_09 Flt "check float cc less") 6034(check-float-condition-code fck uge OP_09 Fuge "check float cc unordered greater or equal") 6035(check-float-condition-code fck ug OP_09 Fug "check float cc unordered or greater") 6036(check-float-condition-code fck le OP_09 Fle "check float cc less or equal") 6037(check-float-condition-code fck gt OP_09 Fgt "check float cc greater") 6038(check-float-condition-code fck ule OP_09 Fule "check float cc unordered less or equal") 6039(check-float-condition-code fck u OP_09 Fu "check float cc unordered") 6040(check-float-condition-code fck o OP_09 Fo "check float cc ordered") 6041 6042(define-pmacro (conditional-check-int-condition-code prefix cc op ope test comment) 6043 (dni (.sym prefix cc) 6044 (comment) 6045 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL) 6046 (.str (.sym prefix cc) "$pack $ICCi_3,$CRj_int,$CCi,$cond") 6047 (+ pack (.sym ICC_ cc) CRj_int op (rs-null) CCi cond ope 6048 (misc-null-9) ICCi_3) 6049 (if (eq CCi (or cond 2)) 6050 (check-semantics (test ICCi_3) CRj_int) 6051 (set CRj_int (cr-undefined))) 6052 ((fr400 (unit u-check)) 6053 (fr500 (unit u-check)) (fr550 (unit u-check))) 6054 ) 6055) 6056 6057(dni cckra 6058 "conditional check integer cc always" 6059 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL) 6060 "cckra$pack $CRj_int,$CCi,$cond" 6061 (+ pack ICC_ra CRj_int OP_6A (rs-null) CCi cond OPE4_0 6062 (misc-null-9) (ICCi_3-null)) 6063 (if (eq CCi (or cond 2)) 6064 (check-semantics (const BI 1) CRj_int) 6065 (set CRj_int (cr-undefined))) 6066 ((fr400 (unit u-check)) 6067 (fr500 (unit u-check)) (fr550 (unit u-check))) 6068) 6069 6070(dni cckno 6071 "conditional check integer cc never" 6072 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL) 6073 "cckno$pack $CRj_int,$CCi,$cond" 6074 (+ pack ICC_nev CRj_int OP_6A (rs-null) CCi cond OPE4_0 6075 (misc-null-9) (ICCi_3-null)) 6076 (if (eq CCi (or cond 2)) 6077 (check-semantics (const BI 0) CRj_int) 6078 (set CRj_int (cr-undefined))) 6079 ((fr400 (unit u-check)) 6080 (fr500 (unit u-check)) (fr550 (unit u-check))) 6081) 6082 6083(conditional-check-int-condition-code cck eq OP_6A OPE4_0 Ieq "check integer cc equal") 6084(conditional-check-int-condition-code cck ne OP_6A OPE4_0 Ine "check integer cc not equal") 6085(conditional-check-int-condition-code cck le OP_6A OPE4_0 Ile "check integer cc less or equal") 6086(conditional-check-int-condition-code cck gt OP_6A OPE4_0 Igt "check integer cc greater") 6087(conditional-check-int-condition-code cck lt OP_6A OPE4_0 Ilt "check integer cc less") 6088(conditional-check-int-condition-code cck ge OP_6A OPE4_0 Ige "check integer cc greater or equal") 6089(conditional-check-int-condition-code cck ls OP_6A OPE4_0 Ils "check integer cc less or equal unsigned") 6090(conditional-check-int-condition-code cck hi OP_6A OPE4_0 Ihi "check integer cc greater unsigned") 6091(conditional-check-int-condition-code cck c OP_6A OPE4_0 Ic "check integer cc carry set") 6092(conditional-check-int-condition-code cck nc OP_6A OPE4_0 Inc "check integer cc carry clear") 6093(conditional-check-int-condition-code cck n OP_6A OPE4_0 In "check integer cc negative") 6094(conditional-check-int-condition-code cck p OP_6A OPE4_0 Ip "check integer cc positive") 6095(conditional-check-int-condition-code cck v OP_6A OPE4_0 Iv "check integer cc overflow set") 6096(conditional-check-int-condition-code cck nv OP_6A OPE4_0 Inv "check integer cc overflow clear") 6097 6098(define-pmacro (conditional-check-float-condition-code prefix cc op ope test comment) 6099 (dni (.sym prefix cc) 6100 (comment) 6101 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL FR-ACCESS) 6102 (.str (.sym prefix cc) "$pack $FCCi_3,$CRj_float,$CCi,$cond") 6103 (+ pack (.sym FCC_ cc) CRj_float op (rs-null) CCi cond ope 6104 (misc-null-9) FCCi_3) 6105 (if (eq CCi (or cond 2)) 6106 (check-semantics (test FCCi_3) CRj_float) 6107 (set CRj_float (cr-undefined))) 6108 ((fr400 (unit u-check)) 6109 (fr500 (unit u-check)) (fr550 (unit u-check))) 6110 ) 6111) 6112 6113(dni cfckra 6114 "conditional check float cc always" 6115 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL FR-ACCESS) 6116 "cfckra$pack $CRj_float,$CCi,$cond" 6117 (+ pack FCC_ra CRj_float OP_6A (rs-null) CCi cond OPE4_1 6118 (misc-null-9) (FCCi_3-null)) 6119 (if (eq CCi (or cond 2)) 6120 (check-semantics (const BI 1) CRj_float) 6121 (set CRj_float (cr-undefined))) 6122 ((fr400 (unit u-check)) 6123 (fr500 (unit u-check)) (fr550 (unit u-check))) 6124) 6125 6126(dni cfckno 6127 "conditional check float cc never" 6128 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL FR-ACCESS) 6129 "cfckno$pack $CRj_float,$CCi,$cond" 6130 (+ pack FCC_nev CRj_float OP_6A (rs-null) CCi cond OPE4_1 6131 (misc-null-9) (FCCi_3-null)) 6132 (if (eq CCi (or cond 2)) 6133 (check-semantics (const BI 0) CRj_float) 6134 (set CRj_float (cr-undefined))) 6135 ((fr400 (unit u-check)) 6136 (fr500 (unit u-check)) (fr550 (unit u-check))) 6137) 6138 6139(conditional-check-float-condition-code cfck ne OP_6A OPE4_1 Fne "check float cc not equal") 6140(conditional-check-float-condition-code cfck eq OP_6A OPE4_1 Feq "check float cc equal") 6141(conditional-check-float-condition-code cfck lg OP_6A OPE4_1 Flg "check float cc greater or less") 6142(conditional-check-float-condition-code cfck ue OP_6A OPE4_1 Fue "check float cc unordered or equal") 6143(conditional-check-float-condition-code cfck ul OP_6A OPE4_1 Ful "check float cc unordered or less") 6144(conditional-check-float-condition-code cfck ge OP_6A OPE4_1 Fge "check float cc greater or equal") 6145(conditional-check-float-condition-code cfck lt OP_6A OPE4_1 Flt "check float cc less") 6146(conditional-check-float-condition-code cfck uge OP_6A OPE4_1 Fuge "check float cc unordered greater or equal") 6147(conditional-check-float-condition-code cfck ug OP_6A OPE4_1 Fug "check float cc unordered or greater") 6148(conditional-check-float-condition-code cfck le OP_6A OPE4_1 Fle "check float cc less or equal") 6149(conditional-check-float-condition-code cfck gt OP_6A OPE4_1 Fgt "check float cc greater") 6150(conditional-check-float-condition-code cfck ule OP_6A OPE4_1 Fule "check float cc unordered less or equal") 6151(conditional-check-float-condition-code cfck u OP_6A OPE4_1 Fu "check float cc unordered") 6152(conditional-check-float-condition-code cfck o OP_6A OPE4_1 Fo "check float cc ordered") 6153 6154(dni cjmpl 6155 "conditional jump and link" 6156 ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5) CONDITIONAL) 6157 "cjmpl$pack @($GRi,$GRj),$CCi,$cond" 6158 (+ pack (misc-null-1) (LI-off) OP_6A GRi CCi cond OPE4_2 GRj) 6159 (if (eq CCi (or cond 2)) 6160 (jump-and-link-semantics GRi GRj LI)) 6161 ((fr400 (unit u-branch)) 6162 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6163) 6164 6165(dni ccalll 6166 "conditional call and link" 6167 ((UNIT I0) (FR500-MAJOR I-5) (FR400-MAJOR I-5) CONDITIONAL) 6168 "ccalll$pack @($GRi,$GRj),$CCi,$cond" 6169 (+ pack (misc-null-1) (LI-on) OP_6A GRi CCi cond OPE4_2 GRj) 6170 (if (eq CCi (or cond 2)) 6171 (jump-and-link-semantics GRi GRj LI)) 6172 ((fr400 (unit u-branch)) 6173 (fr500 (unit u-branch))) 6174) 6175 6176(define-pmacro (cache-invalidate name cache all op ope profile comment) 6177 (dni name 6178 (comment) 6179 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) 6180 (.str name "$pack @($GRi,$GRj)") 6181 (+ pack (rd-null) op GRi ope GRj) 6182 (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) all) 6183 profile 6184 ) 6185) 6186 6187(cache-invalidate ici insn 0 OP_03 OPE1_38 6188 ((fr400 (unit u-ici)) (fr500 (unit u-ici)) (fr550 (unit u-ici))) 6189 "invalidate insn cache") 6190(cache-invalidate dci data 0 OP_03 OPE1_3C 6191 ((fr400 (unit u-dci)) (fr500 (unit u-dci)) (fr550 (unit u-dci))) 6192 "invalidate data cache") 6193 6194(define-pmacro (cache-invalidate-entry name cache op ope profile comment) 6195 (dni name 6196 (comment) 6197 ((UNIT C) (FR400-MAJOR C-2) (FR550-MAJOR C-2) (MACH fr400,fr550)) 6198 (.str name "$pack @($GRi,$GRj),$ae") 6199 (+ pack (misc-null-1) ae op GRi ope GRj) 6200 (if (eq ae 0) 6201 (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) -1) ; Invalid ae setting for this insn 6202 (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) ae)) 6203 profile 6204 ) 6205) 6206 6207(cache-invalidate-entry icei insn OP_03 OPE1_39 6208 ((fr400 (unit u-ici)) (fr550 (unit u-ici))) 6209 "invalidate insn cache entry") 6210(cache-invalidate-entry dcei data OP_03 OPE1_3A 6211 ((fr400 (unit u-dci)) (fr550 (unit u-dci))) 6212 "invalidate data cache entry") 6213 6214(dni dcf 6215 "Data cache flush" 6216 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) 6217 "dcf$pack @($GRi,$GRj)" 6218 (+ pack (rd-null) OP_03 GRi OPE1_3D GRj) 6219 (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) 0) 6220 ((fr400 (unit u-dcf)) 6221 (fr500 (unit u-dcf)) (fr550 (unit u-dcf))) 6222) 6223 6224(dni dcef 6225 "Data cache entry flush" 6226 ((UNIT C) (FR400-MAJOR C-2) (FR550-MAJOR C-2) (MACH fr400,fr550)) 6227 "dcef$pack @($GRi,$GRj),$ae" 6228 (+ pack (misc-null-1) ae OP_03 GRi OPE1_3B GRj) 6229 (if (eq ae 0) 6230 (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) -1) 6231 (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) ae)) 6232 ((fr400 (unit u-dcf)) (fr550 (unit u-dcf))) 6233) 6234 6235(define-pmacro (write-TLB name insn op ope comment) 6236 (dni name 6237 (comment) 6238 ((UNIT C) (FR500-MAJOR C-2) (MACH frv) PRIVILEGED) 6239 (.str insn "$pack $GRk,@($GRi,$GRj)") 6240 (+ pack GRk op GRi ope GRj) 6241 (nop) ; for now 6242 () 6243 ) 6244) 6245 6246(write-TLB witlb witlb OP_03 OPE1_32 "write for insn TLB") 6247(write-TLB wdtlb wdtlb OP_03 OPE1_36 "write for data TLB") 6248 6249(define-pmacro (invalidate-TLB name insn op ope comment) 6250 (dni name 6251 (comment) 6252 ((UNIT C) (FR500-MAJOR C-2) (MACH frv) PRIVILEGED) 6253 (.str insn "$pack @($GRi,$GRj)") 6254 (+ pack (rd-null) op GRi ope GRj) 6255 (nop) ; for now 6256 () 6257 ) 6258) 6259 6260(invalidate-TLB itlbi itlbi OP_03 OPE1_33 "invalidate insn TLB") 6261(invalidate-TLB dtlbi dtlbi OP_03 OPE1_37 "invalidate data TLB") 6262 6263(define-pmacro (cache-preload name cache pipe attrs op ope profile comment) 6264 (dni name 6265 (comment) 6266 (.splice (UNIT pipe) (FR500-MAJOR C-2) (FR400-MAJOR C-2) (.unsplice attrs)) 6267 (.str name "$pack $GRi,$GRj,$lock") 6268 (+ pack (misc-null-1) lock op GRi ope GRj) 6269 (c-call VOID (.str "@cpu@_" cache "_cache_preload") GRi GRj lock) 6270 profile 6271 ) 6272) 6273 6274(cache-preload icpl insn C ((FR550-MAJOR C-2)) OP_03 OPE1_30 6275 ((fr400 (unit u-icpl)) (fr500 (unit u-icpl)) (fr550 (unit u-icpl))) 6276 "preload insn cache") 6277(cache-preload dcpl data DCPL ((FR550-MAJOR I-8)) OP_03 OPE1_34 6278 ((fr400 (unit u-dcpl)) (fr500 (unit u-dcpl)) (fr550 (unit u-dcpl))) 6279 "preload data cache") 6280 6281(define-pmacro (cache-unlock name cache op ope profile comment) 6282 (dni name 6283 (comment) 6284 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) 6285 (.str name "$pack $GRi") 6286 (+ pack (rd-null) op GRi ope (GRj-null)) 6287 (c-call VOID (.str "@cpu@_" cache "_cache_unlock") GRi) 6288 profile 6289 ) 6290) 6291 6292(cache-unlock icul insn OP_03 OPE1_31 6293 ((fr400 (unit u-icul)) (fr500 (unit u-icul)) (fr550 (unit u-icul))) 6294 "unlock insn cache") 6295(cache-unlock dcul data OP_03 OPE1_35 6296 ((fr400 (unit u-dcul)) (fr500 (unit u-dcul)) (fr550 (unit u-dcul))) 6297 "unlock data cache") 6298 6299(define-pmacro (barrier name insn op ope profile comment) 6300 (dni name 6301 (comment) 6302 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2)) 6303 (.str insn "$pack") 6304 (+ pack (rd-null) op (rs-null) ope (GRj-null)) 6305 (nop) ; sufficient implementation 6306 profile 6307 ) 6308) 6309 6310(barrier bar bar OP_03 OPE1_3E 6311 ((fr400 (unit u-barrier)) (fr500 (unit u-barrier))) 6312 "barrier") 6313(barrier membar membar OP_03 OPE1_3F 6314 ((fr400 (unit u-membar)) (fr500 (unit u-membar))) 6315 "memory barrier") 6316 6317; Coprocessor operations 6318(define-pmacro (cop-op num op) 6319 (dni (.sym cop num) 6320 "Coprocessor operation" 6321 ((UNIT C) (FR500-MAJOR C-2) (MACH frv)) 6322 (.str "cop" num "$pack $s6_1,$CPRi,$CPRj,$CPRk") 6323 (+ pack CPRk op CPRi s6_1 CPRj) 6324 (nop) ; sufficient implementation 6325 () 6326 ) 6327) 6328 6329(cop-op 1 OP_7E) 6330(cop-op 2 OP_7F) 6331 6332(define-pmacro (clear-ne-flag-semantics target_index is_float) 6333 (c-call VOID "@cpu@_clear_ne_flags" target_index is_float) 6334) 6335 6336(define-pmacro (clear-ne-flag-r name op ope reg is_float attr profile comment) 6337 (dni name 6338 (comment) 6339 ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH simple,tomcat,fr500,fr550,frv) attr) 6340 (.str name "$pack $" reg "k") 6341 (+ pack (.sym reg k) op (rs-null) ope (GRj-null)) 6342 (sequence () 6343 ; hack to get this referenced for profiling 6344 (c-raw-call VOID "frv_ref_SI" (.sym reg k)) 6345 (clear-ne-flag-semantics (index-of (.sym reg k)) is_float)) 6346 profile 6347 ) 6348) 6349 6350(clear-ne-flag-r clrgr OP_0A OPE1_00 GR 0 NA 6351 ((fr500 (unit u-clrgr)) (fr550 (unit u-clrgr))) 6352 "Clear GR NE flag") 6353(clear-ne-flag-r clrfr OP_0A OPE1_02 FR 1 FR-ACCESS 6354 ((fr500 (unit u-clrfr)) (fr550 (unit u-clrfr))) 6355 "Clear FR NE flag") 6356 6357(define-pmacro (clear-ne-flag-all name op ope is_float attr profile comment) 6358 (dni name 6359 (comment) 6360 ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH simple,tomcat,fr500,fr550,frv) attr) 6361 (.str name "$pack") 6362 (+ pack (rd-null) op (rs-null) ope (GRj-null)) 6363 (clear-ne-flag-semantics -1 is_float) 6364 profile 6365 ) 6366) 6367 6368(clear-ne-flag-all clrga OP_0A OPE1_01 0 NA 6369 ((fr500 (unit u-clrgr)) (fr550 (unit u-clrgr))) 6370 "Clear GR NE flag ALL") 6371(clear-ne-flag-all clrfa OP_0A OPE1_03 1 FR-ACCESS 6372 ((fr500 (unit u-clrfr)) (fr550 (unit u-clrfr))) 6373 "Clear FR NE flag ALL") 6374 6375(define-pmacro (commit-semantics target_index is_float) 6376 (c-call VOID "@cpu@_commit" target_index is_float) 6377) 6378 6379(define-pmacro (commit-r name op ope reg is_float attr comment) 6380 (dni name 6381 (comment) 6382 ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH frv,fr500,fr550) attr) 6383 (.str name "$pack $" reg "k") 6384 (+ pack (.sym reg k) op (rs-null) ope (GRj-null)) 6385 (commit-semantics (index-of (.sym reg k)) is_float) 6386 ((fr500 (unit u-commit)) (fr550 (unit u-commit))) 6387 ) 6388) 6389 6390(commit-r commitgr OP_0A OPE1_04 GR 0 NA "commit exceptions, specific GR") 6391(commit-r commitfr OP_0A OPE1_06 FR 1 FR-ACCESS "commit exceptions, specific FR") 6392 6393(define-pmacro (commit name op ope is_float attr comment) 6394 (dni name 6395 (comment) 6396 ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH frv,fr500,fr550) attr) 6397 (.str name "$pack") 6398 (+ pack (rd-null) op (rs-null) ope (GRj-null)) 6399 (commit-semantics -1 is_float) 6400 ((fr500 (unit u-commit)) (fr550 (unit u-commit))) 6401 ) 6402) 6403 6404(commit commitga OP_0A OPE1_05 0 NA "commit exceptions, any GR") 6405(commit commitfa OP_0A OPE1_07 1 FR-ACCESS "commit exceptions, any FR") 6406 6407(define-pmacro (floating-point-conversion 6408 name op ope conv mode src targ attr comment) 6409 (dni name 6410 (comment) 6411 (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr)) 6412 (.str name "$pack $" src ",$" targ) 6413 (+ pack targ op (rs-null) ope src) 6414 (set targ (conv mode src)) 6415 ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert))) 6416 ) 6417) 6418 6419(floating-point-conversion fitos OP_79 OPE1_00 float SF FRintj FRk 6420 ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 6421 "Convert Integer to Single") 6422(floating-point-conversion fstoi OP_79 OPE1_01 fix SI FRj FRintk 6423 ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 6424 "Convert Single to Integer") 6425(floating-point-conversion fitod OP_7A OPE1_00 float DF FRintj FRdoublek 6426 ((MACH frv)) 6427 "Convert Integer to Double") 6428(floating-point-conversion fdtoi OP_7A OPE1_01 fix SI FRdoublej FRintk 6429 ((MACH frv)) 6430 "Convert Double to Integer") 6431 6432(define-pmacro (floating-point-dual-conversion 6433 name op ope conv mode src src_hw targ targ_hw attr comment) 6434 (dni name 6435 (comment) 6436 ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1) attr) 6437 (.str name "$pack $" src ",$" targ) 6438 (+ pack targ op (rs-null) ope src) 6439 (sequence () 6440 (set targ (conv mode src)) 6441 (set (nextreg targ_hw targ 1) 6442 (conv mode (nextreg src_hw src 1)))) 6443 ((fr500 (unit u-float-dual-convert))) 6444 ) 6445) 6446 6447(floating-point-dual-conversion fditos OP_79 OPE1_10 float SF FRintj h-fr_int FRk h-fr NA "Dual Convert Integer to Single") 6448(floating-point-dual-conversion fdstoi OP_79 OPE1_11 fix SI FRj h-fr FRintk h-fr_int NA "Dual Convert Single to Integer") 6449 6450(define-pmacro (ne-floating-point-dual-conversion 6451 name op ope conv mode src src_hw targ targ_hw attr comment) 6452 (dni name 6453 (comment) 6454 ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1) NON-EXCEPTING attr) 6455 (.str name "$pack $" src ",$" targ) 6456 (+ pack targ op (rs-null) ope src) 6457 (sequence () 6458 (c-call VOID "@cpu@_set_ne_index" (index-of targ)) 6459 (set targ (conv mode src)) 6460 (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 1)) 6461 (set (nextreg targ_hw targ 1) 6462 (conv mode (nextreg src_hw src 1)))) 6463 ((fr500 (unit u-float-dual-convert))) 6464 ) 6465) 6466 6467(ne-floating-point-dual-conversion nfditos OP_79 OPE1_30 float SF FRintj h-fr_int FRk h-fr NA "Non excepting dual Convert Integer to Single") 6468(ne-floating-point-dual-conversion nfdstoi OP_79 OPE1_31 fix SI FRj h-fr FRintk h-fr_int NA "Non excepting dual Convert Single to Integer") 6469 6470(define-pmacro (conditional-floating-point-conversion 6471 name op ope conv mode src targ comment) 6472 (dni name 6473 (comment) 6474 ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 6475 (.str name "$pack $" src ",$" targ ",$CCi,$cond") 6476 (+ pack targ op (rs-null) CCi cond ope src) 6477 (if (eq CCi (or cond 2)) 6478 (set targ (conv mode src))) 6479 ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert))) 6480 ) 6481) 6482 6483(conditional-floating-point-conversion cfitos OP_6B OPE4_0 float SF FRintj FRk "Conditional convert Integer to Single") 6484(conditional-floating-point-conversion cfstoi OP_6B OPE4_1 fix SI FRj FRintk "Conditional convert Single to Integer") 6485 6486(define-pmacro (ne-floating-point-conversion 6487 name op ope conv mode src targ comment) 6488 (dni name 6489 (comment) 6490 ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 6491 (.str name "$pack $" src ",$" targ) 6492 (+ pack targ op (rs-null) ope src) 6493 (sequence () 6494 (c-call VOID "@cpu@_set_ne_index" (index-of targ)) 6495 (set targ (conv mode src))) 6496 ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert))) 6497 ) 6498) 6499 6500(ne-floating-point-conversion nfitos OP_79 OPE1_20 float SF FRintj FRk "NE convert Integer to Single") 6501(ne-floating-point-conversion nfstoi OP_79 OPE1_21 fix SI FRj FRintk "NE convert Single to Integer") 6502 6503(register-transfer fmovs OP_79 OPE1_02 6504 FRj FRk FMALL 6505 ((FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 6506 ((fr500 (unit u-fr2fr))) 6507 "Move Single Float") 6508(register-transfer fmovd OP_7A OPE1_02 6509 ; TODO -- unit doesn't handle extra register 6510 FRdoublej FRdoublek FM01 6511 ((FR500-MAJOR F-1) (MACH frv)) 6512 ((fr500 (unit u-fr2fr)) (fr550 (unit u-fr2fr))) 6513 "Move Double Float") 6514 6515(dni fdmovs 6516 "Dual move single float" 6517 ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1)) 6518 "fdmovs$pack $FRj,$FRk" 6519 (+ pack FRk OP_79 (rs-null) OPE1_12 FRj) 6520 (sequence () 6521 (set FRk FRj) 6522 (set (nextreg h-fr FRk 1) (nextreg h-fr FRj 1))) 6523 ; TODO -- unit doesn't handle extra register 6524 ((fr500 (unit u-fr2fr))) 6525) 6526 6527(conditional-register-transfer cfmovs OP_6C OPE4_0 FRj FRk FM01 6528 ((FR500-MAJOR F-1) (FR550-MAJOR F-2) 6529 (MACH simple,tomcat,fr500,fr550,frv)) 6530 ((fr500 (unit u-fr2fr)) (fr550 (unit u-fr2fr))) 6531 "Conditional move Single Float") 6532 6533(define-pmacro (floating-point-neg name src targ op ope attr comment) 6534 (dni name 6535 (comment) 6536 (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr)) 6537 (.str name "$pack $" src ",$" targ) 6538 (+ pack src op (rs-null) ope targ) 6539 (set targ (neg src)) 6540 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 6541 ) 6542) 6543 6544(floating-point-neg fnegs FRj FRk OP_79 OPE1_03 ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) "Floating point negate, single") 6545(floating-point-neg fnegd FRdoublej FRdoublek OP_7A OPE1_03 ((MACH frv)) "Floating point negate, double") 6546 6547(dni fdnegs 6548 "Floating point dual negate, single" 6549 ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1)) 6550 "fdnegs$pack $FRj,$FRk" 6551 (+ pack FRk OP_79 (rs-null) OPE1_13 FRj) 6552 (sequence () 6553 (set FRk (neg FRj)) 6554 (set (nextreg h-fr FRk 1) (neg (nextreg h-fr FRj 1)))) 6555 ((fr500 (unit u-float-dual-arith))) 6556) 6557 6558(dni cfnegs 6559 "Conditional floating point negate, single" 6560 ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 6561 "cfnegs$pack $FRj,$FRk,$CCi,$cond" 6562 (+ pack FRj OP_6C (rs-null) CCi cond OPE4_1 FRk) 6563 (if (eq CCi (or cond 2)) 6564 (set FRk (neg FRj))) 6565 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 6566) 6567 6568(define-pmacro (float-abs name src targ op ope attr comment) 6569 (dni name 6570 (comment) 6571 (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr)) 6572 (.str name "$pack $" src ",$" targ ) 6573 (+ pack targ op (rs-null) ope src) 6574 (set targ (abs src)) 6575 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 6576 ) 6577) 6578 6579(float-abs fabss FRj FRk OP_79 OPE1_04 ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) "Float absolute value, single") 6580(float-abs fabsd FRdoublej FRdoublek OP_7A OPE1_04 ((MACH frv)) "Float absolute value, double") 6581 6582(dni fdabss 6583 "Floating point dual absolute value, single" 6584 ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1)) 6585 "fdabss$pack $FRj,$FRk" 6586 (+ pack FRk OP_79 (rs-null) OPE1_14 FRj) 6587 (sequence () 6588 (set FRk (abs FRj)) 6589 (set (nextreg h-fr FRk 1) (abs (nextreg h-fr FRj 1)))) 6590 ((fr500 (unit u-float-dual-arith))) 6591) 6592 6593(dni cfabss 6594 "Conditional floating point absolute value, single" 6595 ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 6596 "cfabss$pack $FRj,$FRk,$CCi,$cond" 6597 (+ pack FRj OP_6C (rs-null) CCi cond OPE4_2 FRk) 6598 (if (eq CCi (or cond 2)) 6599 (set FRk (abs FRj))) 6600 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 6601) 6602 6603(dni fsqrts 6604 "Square root single" 6605 ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) 6606 "fsqrts$pack $FRj,$FRk" 6607 (+ pack FRk OP_79 (rs-null) OPE1_05 FRj) 6608 (set FRk (sqrt SF FRj)) 6609 ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt))) 6610) 6611 6612(dni fdsqrts 6613 "Dual square root single" 6614 ((MACH frv) (UNIT FM01) (FR500-MAJOR F-4)) 6615 "fdsqrts$pack $FRj,$FRk" 6616 (+ pack FRk OP_79 (rs-null) OPE1_15 FRj) 6617 (sequence () 6618 (set FRk (sqrt SF FRj)) 6619 (set (nextreg h-fr FRk 1) (sqrt (nextreg h-fr FRj 1)))) 6620 ((fr500 (unit u-float-dual-sqrt))) 6621) 6622 6623(dni nfdsqrts 6624 "Non excepting Dual square root single" 6625 ((MACH frv) (UNIT FM01) (FR500-MAJOR F-4) NON-EXCEPTING) 6626 "nfdsqrts$pack $FRj,$FRk" 6627 (+ pack FRk OP_79 (rs-null) OPE1_35 FRj) 6628 (sequence () 6629 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 6630 (set FRk (sqrt SF FRj)) 6631 (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) 6632 (set (nextreg h-fr FRk 1) (sqrt (nextreg h-fr FRj 1)))) 6633 ((fr500 (unit u-float-dual-sqrt))) 6634) 6635 6636(dni fsqrtd 6637 "Square root double" 6638 ((UNIT FM01) (FR500-MAJOR F-4) (MACH frv)) 6639 "fsqrtd$pack $FRdoublej,$FRdoublek" 6640 (+ pack FRdoublek OP_7A (rs-null) OPE1_05 FRdoublej) 6641 (set FRdoublek (sqrt DF FRdoublej)) 6642 ((fr500 (unit u-float-sqrt))) 6643) 6644 6645(dni cfsqrts 6646 "Conditional square root single" 6647 ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) 6648 "cfsqrts$pack $FRj,$FRk,$CCi,$cond" 6649 (+ pack FRk OP_6E (rs-null) CCi cond OPE4_2 FRj) 6650 (if (eq CCi (or cond 2)) 6651 (set FRk (sqrt SF FRj))) 6652 ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt))) 6653) 6654 6655(dni nfsqrts 6656 "Non exception square root, single" 6657 ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) 6658 "nfsqrts$pack $FRj,$FRk" 6659 (+ pack FRk OP_79 (rs-null) OPE1_25 FRj) 6660 (sequence () 6661 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 6662 (set FRk (sqrt SF FRj))) 6663 ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt))) 6664) 6665 6666(define-pmacro (float-binary-op-s name pipe attr operation op ope comment) 6667 (dni name 6668 (comment) 6669 (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv) (.unsplice attr)) 6670 (.str name "$pack $FRi,$FRj,$FRk") 6671 (+ pack FRk op FRi ope FRj) 6672 (set FRk (operation FRi FRj)) 6673 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 6674 ) 6675) 6676 6677(float-binary-op-s fadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_79 OPE1_06 "add single float") 6678(float-binary-op-s fsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_79 OPE1_07 "sub single float") 6679(float-binary-op-s fmuls FM01 ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_79 OPE1_08 "mul single float") 6680 6681(dni fdivs 6682 "div single float" 6683 ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) 6684 "fdivs$pack $FRi,$FRj,$FRk" 6685 (+ pack FRk OP_79 FRi OPE1_09 FRj) 6686 (set FRk (div FRi FRj)) 6687 ((fr500 (unit u-float-div)) 6688 (fr550 (unit u-float-div))) 6689) 6690 6691(define-pmacro (float-binary-op-d name operation op ope major comment) 6692 (dni name 6693 (comment) 6694 ((UNIT FMALL) (FR500-MAJOR major) (MACH frv)) 6695 (.str name "$pack $FRdoublei,$FRdoublej,$FRdoublek") 6696 (+ pack FRdoublek op FRdoublei ope FRdoublej) 6697 (set FRdoublek (operation FRdoublei FRdoublej)) 6698 ((fr500 (unit u-float-arith))) 6699 ) 6700) 6701 6702(float-binary-op-d faddd add OP_7A OPE1_06 F-2 "add double float") 6703(float-binary-op-d fsubd sub OP_7A OPE1_07 F-2 "sub double float") 6704(float-binary-op-d fmuld mul OP_7A OPE1_08 F-3 "mul double float") 6705(float-binary-op-d fdivd div OP_7A OPE1_09 F-4 "div double float") 6706 6707(define-pmacro (conditional-float-binary-op name pipe attr operation op ope profile comment) 6708 (dni name 6709 (comment) 6710 (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv) 6711 (.unsplice attr)) 6712 (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond") 6713 (+ pack FRk op FRi CCi cond ope FRj) 6714 (if (eq CCi (or cond 2)) 6715 (set FRk (operation FRi FRj))) 6716 profile 6717 ) 6718) 6719 6720(conditional-float-binary-op cfadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_6D OPE4_0 6721 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 6722 "cond add single") 6723(conditional-float-binary-op cfsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_6D OPE4_1 6724 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 6725 "cond sub single") 6726(conditional-float-binary-op cfmuls FM01 ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_6E OPE4_0 6727 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 6728 "cond mul single") 6729(conditional-float-binary-op cfdivs FM01 ((FR500-MAJOR F-4) (FR550-MAJOR F-3)) div OP_6E OPE4_1 6730 ((fr500 (unit u-float-div)) (fr550 (unit u-float-div))) 6731 "cond div single") 6732 6733(define-pmacro (ne-float-binary-op name pipe attr operation op ope profile comment) 6734 (dni name 6735 (comment) 6736 (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv) 6737 (.unsplice attr)) 6738 (.str name "$pack $FRi,$FRj,$FRk") 6739 (+ pack FRk op FRi ope FRj) 6740 (sequence () 6741 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 6742 (set FRk (operation FRi FRj))) 6743 profile 6744 ) 6745) 6746 6747(ne-float-binary-op nfadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_79 OPE1_26 6748 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 6749 "ne add single") 6750(ne-float-binary-op nfsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_79 OPE1_27 6751 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 6752 "ne sub single") 6753(ne-float-binary-op nfmuls FM01 ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_79 OPE1_28 6754 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 6755 "ne mul single") 6756(ne-float-binary-op nfdivs FM01 ((FR500-MAJOR F-4) (FR550-MAJOR F-3)) div OP_79 OPE1_29 6757 ((fr500 (unit u-float-div)) (fr550 (unit u-float-div))) 6758 "ne div single") 6759 6760(define-pmacro (fcc-eq) 8) 6761(define-pmacro (fcc-lt) 4) 6762(define-pmacro (fcc-gt) 2) 6763(define-pmacro (fcc-uo) 1) 6764 6765(define-pmacro (compare-and-set-fcc arg1 arg2 fcc) 6766 (if (gt arg1 arg2) 6767 (set fcc (fcc-gt)) 6768 (if (eq arg1 arg2) 6769 (set fcc (fcc-eq)) 6770 (if (lt arg1 arg2) 6771 (set fcc (fcc-lt)) 6772 (set fcc (fcc-uo))))) 6773) 6774 6775(dni fcmps 6776 "compare single float" 6777 ((UNIT FMALL) (FR500-MAJOR F-2) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 6778 "fcmps$pack $FRi,$FRj,$FCCi_2" 6779 (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_0A FRj) 6780 (compare-and-set-fcc FRi FRj FCCi_2) 6781 ((fr500 (unit u-float-compare)) (fr550 (unit u-float-compare))) 6782) 6783 6784(dni fcmpd 6785 "compare double float" 6786 ((UNIT FMALL) (FR500-MAJOR F-2) (MACH frv)) 6787 "fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2" 6788 (+ pack (cond-null) FCCi_2 OP_7A FRdoublei OPE1_0A FRdoublej) 6789 (compare-and-set-fcc FRdoublei FRdoublej FCCi_2) 6790 ((fr500 (unit u-float-compare))) 6791) 6792 6793(dni cfcmps 6794 "Conditional compare single, float" 6795 ((UNIT FMALL) (FR500-MAJOR F-2) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 6796 "cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond" 6797 (+ pack (cond-null) FCCi_2 OP_6D FRi CCi cond OPE4_2 FRj) 6798 (if (eq CCi (or cond 2)) 6799 (compare-and-set-fcc FRi FRj FCCi_2)) 6800 ((fr500 (unit u-float-compare)) (fr550 (unit u-float-compare))) 6801) 6802 6803(dni fdcmps 6804 "float dual compare single" 6805 ((UNIT FMALL) (FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) 6806 "fdcmps$pack $FRi,$FRj,$FCCi_2" 6807 (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_1A FRj) 6808 (sequence () 6809 (compare-and-set-fcc FRi FRj FCCi_2) 6810 (compare-and-set-fcc (nextreg h-fr FRi 1) (nextreg h-fr FRj 1) 6811 (nextreg h-fccr FCCi_2 1))) 6812 ((fr500 (unit u-float-dual-compare)) (fr550 (unit u-float-dual-compare))) 6813) 6814 6815(define-pmacro (float-mul-with-add name add_sub arg1 arg2 targ op ope comment) 6816 (dni name 6817 (comment) 6818 ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv)) 6819 (.str name "$pack $" arg1 ",$" arg2 ",$" targ) 6820 (+ pack targ op arg1 ope arg2) 6821 (set targ (add_sub (mul arg1 arg2) targ)) 6822 ((fr500 (unit u-float-dual-arith))) 6823 ) 6824) 6825 6826(float-mul-with-add fmadds add FRi FRj FRk OP_79 OPE1_0B "mul with add, single") 6827(float-mul-with-add fmsubs sub FRi FRj FRk OP_79 OPE1_0C "mul with sub, single") 6828 6829(float-mul-with-add fmaddd add FRdoublei FRdoublej FRdoublek OP_7A OPE1_0B "mul with add, double") 6830(float-mul-with-add fmsubd sub FRdoublei FRdoublej FRdoublek OP_7A OPE1_0C "mul with sub, double") 6831 6832(dni fdmadds 6833 "Float dual multiply with add" 6834 ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv)) 6835 "fdmadds$pack $FRi,$FRj,$FRk" 6836 (+ pack FRk OP_79 FRi OPE1_1B FRj) 6837 (sequence () 6838 (set FRk (add (mul FRi FRj) FRk)) 6839 (set (nextreg h-fr FRk 1) 6840 (add (mul (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)) 6841 (nextreg h-fr FRk 1)))) 6842 ; TODO dual registers not referenced for profiling 6843 ((fr500 (unit u-float-dual-arith))) 6844) 6845 6846(dni nfdmadds 6847 "Non excepting float dual multiply with add" 6848 ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv)) 6849 "nfdmadds$pack $FRi,$FRj,$FRk" 6850 (+ pack FRk OP_79 FRi OPE1_3B FRj) 6851 (sequence () 6852 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 6853 (set FRk (add (mul FRi FRj) FRk)) 6854 (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) 6855 (set (nextreg h-fr FRk 1) 6856 (add (mul (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)) 6857 (nextreg h-fr FRk 1)))) 6858 ; TODO dual registers not referenced for profiling 6859 ((fr500 (unit u-float-dual-arith))) 6860) 6861 6862(define-pmacro (conditional-float-mul-with-add 6863 name add_sub arg1 arg2 targ op ope comment) 6864 (dni name 6865 (comment) 6866 ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv) CONDITIONAL) 6867 (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond") 6868 (+ pack FRk op FRi CCi cond ope FRj) 6869 (if (eq CCi (or cond 2)) 6870 (set targ (add_sub (mul arg1 arg2) targ))) 6871 ((fr500 (unit u-float-dual-arith))) 6872 ) 6873) 6874 6875(conditional-float-mul-with-add cfmadds add FRi FRj FRk OP_6F OPE4_0 "conditional mul with add, single") 6876(conditional-float-mul-with-add cfmsubs sub FRi FRj FRk OP_6F OPE4_1 "conditional mul with sub, single") 6877 6878(define-pmacro (ne-float-mul-with-add name add_sub arg1 arg2 targ op ope comment) 6879 (dni name 6880 (comment) 6881 ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv) NON-EXCEPTING) 6882 (.str name "$pack $" arg1 ",$" arg2 ",$" targ) 6883 (+ pack targ op arg1 ope arg2) 6884 (sequence () 6885 (c-call VOID "@cpu@_set_ne_index" (index-of targ)) 6886 (set targ (add_sub (mul arg1 arg2) targ))) 6887 ((fr500 (unit u-float-dual-arith))) 6888 ) 6889) 6890 6891(ne-float-mul-with-add nfmadds add FRi FRj FRk OP_79 OPE1_2B "non excepting mul with add, single") 6892(ne-float-mul-with-add nfmsubs sub FRi FRj FRk OP_79 OPE1_2C "non excepting mul with sub, single") 6893 6894(define-pmacro (float-parallel-mul-add-semantics cond add_sub arg1 arg2 targ) 6895 (if cond 6896 (sequence () 6897 (set targ (mul arg1 arg2)) 6898 (set (nextreg h-fr targ 1) 6899 (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1))))) 6900) 6901 6902(define-pmacro (float-parallel-mul-add 6903 name add_sub arg1 arg2 targ op ope comment) 6904 (dni name 6905 (comment) 6906 ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) 6907 (.str name "$pack $" arg1 ",$" arg2 ",$" targ) 6908 (+ pack targ op arg1 ope arg2) 6909 (float-parallel-mul-add-semantics 1 add_sub arg1 arg2 targ) 6910 ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) 6911 ) 6912) 6913 6914(float-parallel-mul-add fmas add FRi FRj FRk OP_79 OPE1_0E "parallel mul/add, single") 6915(float-parallel-mul-add fmss sub FRi FRj FRk OP_79 OPE1_0F "parallel mul/sub, single") 6916 6917(define-pmacro (float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) 6918 (sequence () 6919 (set targ (mul arg1 arg2)) 6920 (set (nextreg h-fr targ 1) 6921 (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1))) 6922 (set (nextreg h-fr targ 2) 6923 (mul (nextreg h-fr arg1 2) (nextreg h-fr arg2 2))) 6924 (set (nextreg h-fr targ 3) 6925 (add_sub (nextreg h-fr arg1 3) (nextreg h-fr arg2 3)))) 6926) 6927 6928(define-pmacro (float-dual-parallel-mul-add 6929 name add_sub arg1 arg2 targ op ope comment) 6930 (dni name 6931 (comment) 6932 ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv)) 6933 (.str name "$pack $" arg1 ",$" arg2 ",$" targ) 6934 (+ pack targ op arg1 ope arg2) 6935 (float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) 6936 () 6937 ) 6938) 6939 6940(float-dual-parallel-mul-add fdmas add FRi FRj FRk OP_79 OPE1_1C "dual parallel mul/add, single") 6941(float-dual-parallel-mul-add fdmss sub FRi FRj FRk OP_79 OPE1_1D "dual parallel mul/sub, single") 6942 6943(define-pmacro (ne-float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) 6944 (sequence () 6945 (c-call VOID "@cpu@_set_ne_index" (index-of targ)) 6946 (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 1)) 6947 (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 2)) 6948 (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 3)) 6949 (set targ (mul arg1 arg2)) 6950 (set (nextreg h-fr targ 1) 6951 (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1))) 6952 (set (nextreg h-fr targ 2) 6953 (mul (nextreg h-fr arg1 2) (nextreg h-fr arg2 2))) 6954 (set (nextreg h-fr targ 3) 6955 (add_sub (nextreg h-fr arg1 3) (nextreg h-fr arg2 3)))) 6956) 6957 6958(define-pmacro (ne-float-dual-parallel-mul-add 6959 name add_sub arg1 arg2 targ op ope comment) 6960 (dni name 6961 (comment) 6962 ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv)) 6963 (.str name "$pack $" arg1 ",$" arg2 ",$" targ) 6964 (+ pack targ op arg1 ope arg2) 6965 (ne-float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) 6966 () 6967 ) 6968) 6969 6970(ne-float-dual-parallel-mul-add nfdmas add FRi FRj FRk OP_79 OPE1_3C "non excepting dual parallel mul/add, single") 6971(ne-float-dual-parallel-mul-add nfdmss sub FRi FRj FRk OP_79 OPE1_3D "non excepting dual parallel mul/sub, single") 6972 6973(define-pmacro (conditional-float-parallel-mul-add name add_sub op ope comment) 6974 (dni name 6975 (comment) 6976 ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) CONDITIONAL (MACH simple,tomcat,fr500,fr550,frv)) 6977 (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond") 6978 (+ pack FRk op FRi CCi cond ope FRj) 6979 (float-parallel-mul-add-semantics (eq CCi (or cond 2)) 6980 add_sub FRi FRj FRk) 6981 ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) 6982 ) 6983) 6984 6985(conditional-float-parallel-mul-add cfmas add OP_6F OPE4_2 "conditional parallel mul/add, single") 6986(conditional-float-parallel-mul-add cfmss sub OP_6F OPE4_3 "conditional parallel mul/sub, single") 6987 6988(define-pmacro (float-parallel-mul-add-double-semantics add_sub arg1 arg2 targ) 6989 (sequence () 6990 (set targ (ftrunc SF (mul DF (fext DF arg1) (fext DF arg2)))) 6991 (set (nextreg h-fr targ 1) 6992 (ftrunc SF (add_sub DF 6993 (fext DF (nextreg h-fr arg1 1)) 6994 (fext DF (nextreg h-fr arg2 1)))))) 6995) 6996 6997(define-pmacro (float-parallel-mul-add-double 6998 name add_sub arg1 arg2 targ op ope comment) 6999 (dni name 7000 (comment) 7001 ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv)) 7002 (.str name "$pack $" arg1 ",$" arg2 ",$" targ) 7003 (+ pack targ op arg1 ope arg2) 7004 (float-parallel-mul-add-double-semantics add_sub arg1 arg2 targ) 7005 () 7006 ) 7007) 7008 7009(float-parallel-mul-add-double fmad add FRi FRj FRk OP_7A OPE1_0E "parallel mul/add, double") 7010(float-parallel-mul-add-double fmsd sub FRi FRj FRk OP_7A OPE1_0F "parallel mul/sub, double") 7011 7012(define-pmacro (ne-float-parallel-mul-add name add_sub op ope comment) 7013 (dni name 7014 (comment) 7015 ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) 7016 (.str name "$pack $FRi,$FRj,$FRk") 7017 (+ pack FRk op FRi ope FRj) 7018 (sequence () 7019 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 7020 (set FRk (mul FRi FRj)) 7021 (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) 7022 (set (nextreg h-fr FRk 1) 7023 (add_sub (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)))) 7024 ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) 7025 ) 7026) 7027 7028(ne-float-parallel-mul-add nfmas add OP_79 OPE1_2E "ne parallel mul/add,single") 7029(ne-float-parallel-mul-add nfmss sub OP_79 OPE1_2F "ne parallel mul/sub,single") 7030 7031(define-pmacro (float-dual-arith name attr oper1 oper2 op ope comment) 7032 (dni name 7033 (comment) 7034 (.splice (UNIT FM01) (.unsplice attr)) 7035 (.str name "$pack $FRi,$FRj,$FRk") 7036 (+ pack FRk op FRi ope FRj) 7037 (sequence () 7038 (set FRk (oper1 FRi FRj)) 7039 (set (nextreg h-fr FRk 1) 7040 (oper2 (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)))) 7041 ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) 7042 ) 7043) 7044 7045(float-dual-arith fdadds ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add add OP_79 OPE1_16 "dual add, single") 7046(float-dual-arith fdsubs ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) sub sub OP_79 OPE1_17 "dual sub, single") 7047(float-dual-arith fdmuls ((FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) mul mul OP_79 OPE1_18 "dual mul, single") 7048(float-dual-arith fddivs ((FR500-MAJOR F-7) (MACH frv)) div div OP_79 OPE1_19 "dual div,single") 7049(float-dual-arith fdsads ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add sub OP_79 OPE1_1E "dual add/sub, single") 7050 7051(dni fdmulcs 7052 "Float dual cross multiply single" 7053 ((UNIT FM01) (FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) 7054 "fdmulcs$pack $FRi,$FRj,$FRk" 7055 (+ pack FRk OP_79 FRi OPE1_1F FRj) 7056 (sequence () 7057 (set FRk (mul FRi (nextreg h-fr FRj 1))) 7058 (set (nextreg h-fr FRk 1) (mul (nextreg h-fr FRi 1) FRj))) 7059 ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) 7060) 7061 7062(dni nfdmulcs 7063 "NE float dual cross multiply single" 7064 ((UNIT FM01) (FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) 7065 "nfdmulcs$pack $FRi,$FRj,$FRk" 7066 (+ pack FRk OP_79 FRi OPE1_3F FRj) 7067 (sequence () 7068 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 7069 (set FRk (mul FRi (nextreg h-fr FRj 1))) 7070 (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) 7071 (set (nextreg h-fr FRk 1) (mul (nextreg h-fr FRi 1) FRj))) 7072 ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) 7073) 7074 7075(define-pmacro (ne-float-dual-arith name attr oper1 oper2 op ope comment) 7076 (dni name 7077 (comment) 7078 (.splice (UNIT FM01) (.unsplice attr)) 7079 (.str name "$pack $FRi,$FRj,$FRk") 7080 (+ pack FRk op FRi ope FRj) 7081 (sequence () 7082 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 7083 (set FRk (oper1 FRi FRj)) 7084 (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) 7085 (set (nextreg h-fr FRk 1) 7086 (oper2 (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)))) 7087 ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) 7088 ) 7089) 7090 7091(ne-float-dual-arith nfdadds ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add add OP_79 OPE1_36 "ne dual add, single") 7092(ne-float-dual-arith nfdsubs ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) sub sub OP_79 OPE1_37 "ne dual sub, single") 7093(ne-float-dual-arith nfdmuls ((FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) mul mul OP_79 OPE1_38 "ne dual mul, single") 7094(ne-float-dual-arith nfddivs ((FR500-MAJOR F-7) (MACH frv)) div div OP_79 OPE1_39 "ne dual div,single") 7095(ne-float-dual-arith nfdsads ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add sub OP_79 OPE1_3E "ne dual add/sub, single") 7096 7097(dni nfdcmps 7098 "non-excepting dual float compare" 7099 ((UNIT FM01) (FR500-MAJOR F-6) (MACH simple,tomcat,frv)) 7100 "nfdcmps$pack $FRi,$FRj,$FCCi_2" 7101 (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_3A FRj) 7102 (sequence () 7103 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 7104 (compare-and-set-fcc FRi FRj FCCi_2) 7105 (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) 7106 (compare-and-set-fcc (nextreg h-fr FRi 1) (nextreg h-fr FRj 1) 7107 (nextreg h-fccr FCCi_2 1))) 7108 ((fr500 (unit u-float-dual-compare))) 7109) 7110 7111; Media Instructions 7112; 7113(define-pmacro (halfword hilo arg offset) 7114 (reg (.sym h-fr_ hilo) (add (index-of arg) offset))) 7115 7116(dni mhsetlos 7117 "Media set lower signed 12 bits" 7118 ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) 7119 "mhsetlos$pack $u12,$FRklo" 7120 (+ pack FRklo OP_78 OPE1_20 u12) 7121 (set FRklo u12) 7122 ((fr400 (unit u-media-hilo)) (fr550 (unit u-media-set (out FRintk FRklo)))) 7123) 7124 7125(dni mhsethis 7126 "Media set upper signed 12 bits" 7127 ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) 7128 "mhsethis$pack $u12,$FRkhi" 7129 (+ pack FRkhi OP_78 OPE1_22 u12) 7130 (set FRkhi u12) 7131 ((fr400 (unit u-media-hilo)) (fr550 (unit u-media-set (out FRintk FRkhi)))) 7132) 7133 7134(dni mhdsets 7135 "Media dual set halfword signed 12 bits" 7136 ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) 7137 "mhdsets$pack $u12,$FRintk" 7138 (+ pack FRintk OP_78 OPE1_24 u12) 7139 (sequence () 7140 ; hack to get FRintk passed to modelling functions 7141 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 7142 (set (halfword hi FRintk 0) u12) 7143 (set (halfword lo FRintk 0) u12)) 7144 ((fr400 (unit u-media-1)) (fr550 (unit u-media-set))) 7145) 7146 7147(define-pmacro (set-5-semantics target value) 7148 (sequence ((HI tmp)) 7149 (set tmp target) 7150 (set tmp (and tmp #x07ff)) 7151 (set tmp (or tmp (sll (and s5 #x1f) 11))) 7152 (set target tmp)) 7153) 7154 7155(define-pmacro (media-set-5 name hilo op ope comment) 7156 (dni name 7157 (comment) 7158 ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) 7159 (.str name "$pack $s5,$FRk" hilo) 7160 (+ pack (.sym FRk hilo) op (FRi-null) ope (misc-null-11) s5) 7161 (set-5-semantics (.sym FRk hilo) s5) 7162 ((fr400 (unit u-media-hilo)) (fr550 (unit u-media-set (out FRintk (.sym FRk hilo))))) 7163 ) 7164) 7165 7166(media-set-5 mhsetloh lo OP_78 OPE1_21 "Media set upper 5 bits lo") 7167(media-set-5 mhsethih hi OP_78 OPE1_23 "Media set upper 5 bits hi") 7168 7169(dni mhdseth 7170 "Media dual set halfword upper 5 bits" 7171 ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1)) 7172 "mhdseth$pack $s5,$FRintk" 7173 (+ pack FRintk OP_78 (FRi-null) OPE1_25 (misc-null-11) s5) 7174 (sequence () 7175 ; hack to get FRintk passed to modelling functions 7176 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 7177 (set-5-semantics (halfword hi FRintk 0) s5) 7178 (set-5-semantics (halfword lo FRintk 0) s5)) 7179 ((fr400 (unit u-media-1)) (fr550 (unit u-media-set))) 7180) 7181 7182(define-pmacro (media-logic-r-r name operation op ope comment) 7183 (dni name 7184 (comment) 7185 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) 7186 (.str name "$pack $FRinti,$FRintj,$FRintk") 7187 (+ pack FRintk op FRinti ope FRintj) 7188 (set FRintk (operation FRinti FRintj)) 7189 ((fr400 (unit u-media-1)) 7190 (fr500 (unit u-media)) (fr550 (unit u-media))) 7191 ) 7192) 7193 7194(media-logic-r-r mand and OP_7B OPE1_00 "and reg/reg") 7195(media-logic-r-r mor or OP_7B OPE1_01 "or reg/reg") 7196(media-logic-r-r mxor xor OP_7B OPE1_02 "xor reg/reg") 7197 7198(define-pmacro (conditional-media-logic name operation op ope comment) 7199 (dni name 7200 (comment) 7201 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1) CONDITIONAL) 7202 (.str name "$pack $FRinti,$FRintj,$FRintk,$CCi,$cond") 7203 (+ pack FRintk op FRinti CCi cond ope FRintj) 7204 (if (eq CCi (or cond 2)) 7205 (set FRintk (operation FRinti FRintj))) 7206 ((fr400 (unit u-media-1)) 7207 (fr500 (unit u-media)) (fr550 (unit u-media))) 7208 ) 7209) 7210 7211(conditional-media-logic cmand and OP_70 OPE4_0 "conditional and reg/reg") 7212(conditional-media-logic cmor or OP_70 OPE4_1 "conditional or reg/reg") 7213(conditional-media-logic cmxor xor OP_70 OPE4_2 "conditional xor reg/reg") 7214 7215(dni mnot 7216 ("mnot") 7217 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) 7218 ("mnot$pack $FRintj,$FRintk") 7219 (+ pack FRintk OP_7B (rs-null) OPE1_03 FRintj) 7220 (set FRintk (inv FRintj)) 7221 ((fr400 (unit u-media-1)) 7222 (fr500 (unit u-media)) (fr550 (unit u-media))) 7223) 7224 7225(dni cmnot 7226 ("cmnot") 7227 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1) CONDITIONAL) 7228 ("cmnot$pack $FRintj,$FRintk,$CCi,$cond") 7229 (+ pack FRintk OP_70 (rs-null) CCi cond OPE4_3 FRintj) 7230 (if (eq CCi (or cond 2)) 7231 (set FRintk (inv FRintj))) 7232 ((fr400 (unit u-media-1)) 7233 (fr500 (unit u-media)) (fr550 (unit u-media))) 7234) 7235 7236(define-pmacro (media-rotate-r-r name operation op ope comment) 7237 (dni name 7238 (comment) 7239 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) 7240 (.str name "$pack $FRinti,$u6,$FRintk") 7241 (+ pack FRintk op FRinti ope u6) 7242 (set FRintk (operation FRinti (and u6 #x1f))) 7243 ((fr400 (unit u-media-3)) 7244 (fr500 (unit u-media)) (fr550 (unit u-media))) 7245 ) 7246) 7247 7248(media-rotate-r-r mrotli rol OP_7B OPE1_04 "rotate left reg/reg") 7249(media-rotate-r-r mrotri ror OP_7B OPE1_05 "rotate right reg/reg") 7250 7251(define-pmacro (media-cut-r-r name arg op ope comment) 7252 (dni name 7253 (comment) 7254 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) 7255 (.str name "$pack $FRinti,$" arg ",$FRintk") 7256 (+ pack FRintk op FRinti ope arg) 7257 (set FRintk (c-call SI "@cpu@_cut" FRinti (nextreg h-fr_int FRinti 1) arg)) 7258 ((fr400 (unit u-media-3)) 7259 (fr500 (unit u-media)) (fr550 (unit u-media))) 7260 ) 7261) 7262 7263(media-cut-r-r mwcut FRintj OP_7B OPE1_06 "media cut") 7264(media-cut-r-r mwcuti u6 OP_7B OPE1_07 "media cut") 7265 7266(define-pmacro (media-cut-acc name arg op ope comment) 7267 (dni name 7268 (comment) 7269 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) 7270 (.str name "$pack $ACC40Si,$" arg ",$FRintk") 7271 (+ pack FRintk op ACC40Si ope arg) 7272 (set FRintk (c-call SI "@cpu@_media_cut" ACC40Si arg)) 7273 ((fr400 (unit u-media-4)) 7274 (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) 7275 ) 7276) 7277 7278(media-cut-acc mcut FRintj OP_7B OPE1_2C "media accumulator cut reg") 7279(media-cut-acc mcuti s6 OP_7B OPE1_2E "media accumulator cut immed") 7280 7281(define-pmacro (media-cut-acc-ss name arg op ope comment) 7282 (dni name 7283 (comment) 7284 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) 7285 (.str name "$pack $ACC40Si,$" arg ",$FRintk") 7286 (+ pack FRintk op ACC40Si ope arg) 7287 (set FRintk (c-call SI "@cpu@_media_cut_ss" ACC40Si arg)) 7288 ((fr400 (unit u-media-4)) 7289 (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) 7290 ) 7291) 7292 7293(media-cut-acc-ss mcutss FRintj OP_7B OPE1_2D "media accumulator cut reg with saturation") 7294(media-cut-acc-ss mcutssi s6 OP_7B OPE1_2F "media accumulator cut immed with saturation") 7295 7296; Dual Media Instructions 7297; 7298(define-pmacro (register-unaligned register alignment) 7299 (and (index-of register) (sub alignment 1)) 7300) 7301 7302(dni mdcutssi 7303 "Media dual cut with signed saturation" 7304 ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) 7305 "mdcutssi$pack $ACC40Si,$s6,$FRintkeven" 7306 (+ pack FRintkeven OP_78 ACC40Si OPE1_0E s6) 7307 (if (register-unaligned ACC40Si 2) 7308 (c-call VOID "@cpu@_media_acc_not_aligned") 7309 (if (register-unaligned FRintkeven 2) 7310 (c-call VOID "@cpu@_media_register_not_aligned") 7311 (sequence () 7312 (set FRintkeven (c-call SI "@cpu@_media_cut_ss" ACC40Si s6)) 7313 (set (nextreg h-fr_int FRintkeven 1) 7314 (c-call SI "@cpu@_media_cut_ss" 7315 (nextreg h-acc40S ACC40Si 1) s6))))) 7316 ((fr400 (unit u-media-4-acc-dual 7317 (out FRintk FRintkeven))) (fr550 (unit u-media-3-acc-dual))) 7318) 7319 7320; The (add (xxxx) (mul arg 0)) is a hack to get a reference to arg generated 7321; so it will be passed to the unit modelers. YUCK!!!!! 7322(define-pmacro (extract-hilo reg1 off1 reg2 off2 arg1hi arg1lo arg2hi arg2lo) 7323 (sequence () 7324 (set arg1hi (add (halfword hi reg1 off1) (mul reg1 0))) 7325 (set arg1lo (add (halfword lo reg1 off1) (mul reg1 0))) 7326 (set arg2hi (add (halfword hi reg2 off2) (mul reg2 0))) 7327 (set arg2lo (add (halfword lo reg2 off2) (mul reg2 0)))) 7328) 7329 7330(dni maveh 7331 "Media dual average" 7332 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) 7333 "maveh$pack $FRinti,$FRintj,$FRintk" 7334 (+ pack FRintk OP_7B FRinti OPE1_08 FRintj) 7335 (set FRintk (c-call SI "@cpu@_media_average" FRinti FRintj)) 7336 ((fr400 (unit u-media-1)) 7337 (fr500 (unit u-media)) (fr550 (unit u-media))) 7338) 7339 7340(define-pmacro (media-dual-shift name operation op ope profile comment) 7341 (dni name 7342 (comment) 7343 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) 7344 (.str name "$pack $FRinti,$u6,$FRintk") 7345 (+ pack FRintk op FRinti ope u6) 7346 (sequence () 7347 ; hack to get these referenced for profiling 7348 (set FRinti (c-raw-call SI "frv_ref_SI" FRinti)) 7349 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 7350 (set (halfword hi FRintk 0) 7351 (operation (halfword hi FRinti 0) (and u6 #xf))) 7352 (set (halfword lo FRintk 0) 7353 (operation (halfword lo FRinti 0) (and u6 #xf)))) 7354 profile 7355 ) 7356) 7357 7358(media-dual-shift msllhi sll OP_7B OPE1_09 7359 ((fr400 (unit u-media-3)) (fr500 (unit u-media)) (fr550 (unit u-media))) 7360 "Media dual shift left logical") 7361(media-dual-shift msrlhi srl OP_7B OPE1_0A 7362 ((fr400 (unit u-media-3)) (fr500 (unit u-media)) (fr550 (unit u-media))) 7363 "Media dual shift right logical") 7364(media-dual-shift msrahi sra OP_7B OPE1_0B 7365 ((fr400 (unit u-media-6)) (fr500 (unit u-media)) (fr550 (unit u-media))) 7366 "Media dual shift right arithmetic") 7367 7368(define-pmacro (media-dual-word-rotate-r-r name operation op ope comment) 7369 (dni name 7370 (comment) 7371 ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) 7372 (.str name "$pack $FRintieven,$s6,$FRintkeven") 7373 (+ pack FRintkeven op FRintieven ope s6) 7374 (if (orif (register-unaligned FRintieven 2) 7375 (register-unaligned FRintkeven 2)) 7376 (c-call VOID "@cpu@_media_register_not_aligned") 7377 (sequence () 7378 (set FRintkeven (operation FRintieven (and s6 #x1f))) 7379 (set (nextreg h-fr_int FRintkeven 1) 7380 (operation (nextreg h-fr_int FRintieven 1) 7381 (and s6 #x1f))))) 7382 ((fr400 (unit u-media-3-quad 7383 (in FRinti FRintieven) 7384 (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) 7385 ) 7386) 7387 7388(media-dual-word-rotate-r-r mdrotli rol OP_78 OPE1_0B "rotate left reg/reg") 7389 7390(dni mcplhi 7391 "Media bit concatenate, halfword" 7392 ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) 7393 "mcplhi$pack $FRinti,$u6,$FRintk" 7394 (+ pack FRintk OP_78 FRinti OPE1_0C u6) 7395 (sequence ((HI arg1) (HI arg2) (HI shift)) 7396 (set FRinti (c-raw-call SI "frv_ref_SI" FRinti)) 7397 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 7398 (set shift (and u6 #xf)) 7399 (set arg1 (sll (halfword hi FRinti 0) shift)) 7400 (if (ne shift 0) 7401 (sequence () 7402 (set arg2 (halfword hi FRinti 1)) 7403 (set arg2 (srl HI (sll HI arg2 (sub 15 shift)) 7404 (sub 15 shift))) 7405 (set arg1 (or HI arg1 arg2)))) 7406 (set (halfword hi FRintk 0) arg1)) 7407 ((fr400 (unit u-media-3-dual)) (fr550 (unit u-media-3-dual))) 7408) 7409 7410(dni mcpli 7411 "Media bit concatenate, word" 7412 ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) 7413 "mcpli$pack $FRinti,$u6,$FRintk" 7414 (+ pack FRintk OP_78 FRinti OPE1_0D u6) 7415 (sequence ((SI tmp) (SI shift)) 7416 (set shift (and u6 #x1f)) 7417 (set tmp (sll FRinti shift)) 7418 (if (ne shift 0) 7419 (sequence ((SI tmp1)) 7420 (set tmp1 (srl (sll (nextreg h-fr_int FRinti 1) 7421 (sub 31 shift)) 7422 (sub 31 shift))) 7423 (set tmp (or tmp tmp1)))) 7424 (set FRintk tmp)) 7425 ((fr400 (unit u-media-3-dual)) (fr550 (unit u-media-3-dual))) 7426) 7427 7428(define-pmacro (saturate arg max min result) 7429 (if (gt arg max) 7430 (set result max) 7431 (if (lt arg min) 7432 (set result min) 7433 (set result arg))) 7434) 7435 7436(dni msaths 7437 "Media dual saturation signed" 7438 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) 7439 "msaths$pack $FRinti,$FRintj,$FRintk" 7440 (+ pack FRintk OP_7B FRinti OPE1_0C FRintj) 7441 (sequence ((HI argihi) (HI argilo) (HI argjhi) (HI argjlo)) 7442 (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) 7443 (saturate argihi argjhi (inv argjhi) (halfword hi FRintk 0)) 7444 (saturate argilo argjlo (inv argjlo) (halfword lo FRintk 0))) 7445 ((fr400 (unit u-media-1)) 7446 (fr500 (unit u-media)) (fr550 (unit u-media))) 7447) 7448 7449(dni mqsaths 7450 "Media quad saturation signed" 7451 ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) 7452 "mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven" 7453 (+ pack FRintkeven OP_78 FRintieven OPE1_0F FRintjeven) 7454 (if (orif (register-unaligned FRintieven 2) 7455 (orif (register-unaligned FRintjeven 2) 7456 (register-unaligned FRintkeven 2))) 7457 (c-call VOID "@cpu@_media_register_not_aligned") 7458 (sequence ((HI argihi) (HI argilo) (HI argjhi) (HI argjlo)) 7459 ; hack to get FRintkeven referenced as a target for profiling 7460 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 7461 (extract-hilo FRintieven 0 FRintjeven 0 argihi argilo argjhi argjlo) 7462 (saturate argihi argjhi (inv argjhi) (halfword hi FRintkeven 0)) 7463 (saturate argilo argjlo (inv argjlo) (halfword lo FRintkeven 0)) 7464 (extract-hilo FRintieven 1 FRintjeven 1 argihi argilo argjhi argjlo) 7465 (saturate argihi argjhi (inv argjhi) (halfword hi FRintkeven 1)) 7466 (saturate argilo argjlo (inv argjlo) (halfword lo FRintkeven 1)))) 7467 ((fr400 (unit u-media-1-quad 7468 (in FRinti FRintieven) 7469 (in FRintj FRintjeven) 7470 (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) 7471) 7472 7473(define-pmacro (saturate-unsigned arg max result) 7474 (if (gt arg max) 7475 (set result max) 7476 (set result arg)) 7477) 7478 7479(dni msathu 7480 "Media dual saturation unsigned" 7481 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) 7482 "msathu$pack $FRinti,$FRintj,$FRintk" 7483 (+ pack FRintk OP_7B FRinti OPE1_0D FRintj) 7484 (sequence ((UHI argihi) (UHI argilo) (UHI argjhi) (UHI argjlo)) 7485 (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) 7486 (saturate-unsigned argihi argjhi (halfword hi FRintk 0)) 7487 (saturate-unsigned argilo argjlo (halfword lo FRintk 0))) 7488 ((fr400 (unit u-media-1)) 7489 (fr500 (unit u-media)) (fr550 (unit u-media))) 7490) 7491 7492(define-pmacro (media-dual-compare name mode op ope comment) 7493 (dni name 7494 (comment) 7495 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) 7496 (.str name "$pack $FRinti,$FRintj,$FCCk") 7497 (+ pack (cond-null) FCCk op FRinti ope FRintj) 7498 (if (register-unaligned FCCk 2) 7499 (c-call VOID "@cpu@_media_cr_not_aligned") 7500 (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) 7501 (extract-hilo FRinti 0 FRintj 0 7502 argihi argilo argjhi argjlo) 7503 (compare-and-set-fcc argihi argjhi FCCk) 7504 (compare-and-set-fcc argilo argjlo (nextreg h-fccr FCCk 1)))) 7505 ; TODO - doesn't handle second FCC 7506 ((fr400 (unit u-media-7)) 7507 (fr500 (unit u-media)) (fr550 (unit u-media))) 7508 ) 7509) 7510 7511(media-dual-compare mcmpsh HI OP_7B OPE1_0E "Media dual compare signed") 7512(media-dual-compare mcmpuh UHI OP_7B OPE1_0F "Media dual compare unsigned") 7513 7514; Bits for the MSR.SIE field 7515(define-pmacro (msr-sie-nil) 0) 7516(define-pmacro (msr-sie-fri-hi) 8) 7517(define-pmacro (msr-sie-fri-lo) 4) 7518(define-pmacro (msr-sie-fri-1-hi) 2) 7519(define-pmacro (msr-sie-fri-1-lo) 1) 7520(define-pmacro (msr-sie-acci) 8) 7521(define-pmacro (msr-sie-acci-1) 4) 7522(define-pmacro (msr-sie-acci-2) 2) 7523(define-pmacro (msr-sie-acci-3) 1) 7524 7525(define-pmacro (saturate-v arg max min sie result) 7526 (if (gt DI arg max) 7527 (sequence () 7528 (set result max) 7529 (c-call VOID "@cpu@_media_overflow" sie)) 7530 (if (lt DI arg min) 7531 (sequence () 7532 (set result min) 7533 (c-call VOID "@cpu@_media_overflow" sie)) 7534 (set result arg))) 7535) 7536 7537(dni mabshs 7538 "Media dual absolute value, halfword" 7539 ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) 7540 "mabshs$pack $FRintj,$FRintk" 7541 (+ pack FRintk OP_78 (FRi-null) OPE1_0A FRintj) 7542 (sequence ((HI arghi) (HI arglo)) 7543 (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) 7544 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 7545 (set arghi (halfword hi FRintj 0)) 7546 (set arglo (halfword lo FRintj 0)) 7547 (saturate-v (abs arghi) 32767 -32768 (msr-sie-fri-hi) 7548 (halfword hi FRintk 0)) 7549 (saturate-v (abs arglo) 32767 -32768 (msr-sie-fri-lo) 7550 (halfword lo FRintk 0))) 7551 ((fr400 (unit u-media-1)) (fr550 (unit u-media))) 7552) 7553 7554(define-pmacro (media-arith-sat-semantics 7555 operation arg1 arg2 res mode max min sie) 7556 (sequence ((DI tmp)) 7557 (set tmp (operation arg1 arg2)) 7558 (saturate-v tmp max min sie res)) 7559) 7560 7561(define-pmacro (media-dual-arith-sat-semantics operation mode max min) 7562 (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) 7563 (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) 7564 (media-arith-sat-semantics operation argihi argjhi 7565 (halfword hi FRintk 0) mode max min 7566 (msr-sie-fri-hi)) 7567 (media-arith-sat-semantics operation argilo argjlo 7568 (halfword lo FRintk 0) mode max min 7569 (msr-sie-fri-lo))) 7570) 7571 7572(define-pmacro (media-dual-arith-sat name operation mode max min op ope comment) 7573 (dni name 7574 (comment) 7575 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1)) 7576 (.str name "$pack $FRinti,$FRintj,$FRintk") 7577 (+ pack FRintk op FRinti ope FRintj) 7578 (media-dual-arith-sat-semantics operation mode max min) 7579 ((fr400 (unit u-media-1)) 7580 (fr500 (unit u-media)) (fr550 (unit u-media))) 7581 ) 7582) 7583 7584(media-dual-arith-sat maddhss add HI 32767 -32768 OP_7B OPE1_10 "Media dual add signed with saturation") 7585(media-dual-arith-sat maddhus add UHI 65535 0 OP_7B OPE1_11 "Media dual add unsigned with saturation") 7586 7587(media-dual-arith-sat msubhss sub HI 32767 -32768 OP_7B OPE1_12 "Media dual sub signed with saturation") 7588(media-dual-arith-sat msubhus sub UHI 65535 0 OP_7B OPE1_13 "Media dual sub unsigned with saturation") 7589 7590(define-pmacro (conditional-media-dual-arith-sat 7591 name operation mode max min op ope comment) 7592 (dni name 7593 (comment) 7594 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1) CONDITIONAL) 7595 (.str name "$pack $FRinti,$FRintj,$FRintk,$CCi,$cond") 7596 (+ pack FRintk op FRinti CCi cond ope FRintj) 7597 (if (eq CCi (or cond 2)) 7598 (media-dual-arith-sat-semantics operation mode max min)) 7599 ((fr400 (unit u-media-1)) 7600 (fr500 (unit u-media)) (fr550 (unit u-media))) 7601 ) 7602) 7603 7604(conditional-media-dual-arith-sat cmaddhss add HI 32767 -32768 OP_71 OPE4_0 "Conditional Media dual add signed with saturation") 7605(conditional-media-dual-arith-sat cmaddhus add UHI 65535 0 OP_71 OPE4_1 "Conditional Media dual add unsigned with saturation") 7606 7607(conditional-media-dual-arith-sat cmsubhss sub HI 32767 -32768 OP_71 OPE4_2 "Conditional Media dual sub signed with saturation") 7608(conditional-media-dual-arith-sat cmsubhus sub UHI 65535 0 OP_71 OPE4_3 "Conditional Media dual sub unsigned with saturation") 7609 7610(define-pmacro (media-quad-arith-sat-semantics cond operation mode max min) 7611 (if (orif (register-unaligned FRintieven 2) 7612 (orif (register-unaligned FRintjeven 2) 7613 (register-unaligned FRintkeven 2))) 7614 (c-call VOID "@cpu@_media_register_not_aligned") 7615 (if cond 7616 (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) 7617 ; hack to get FRintkeven referenced as a target for profiling 7618 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 7619 (extract-hilo FRintieven 0 FRintjeven 0 7620 argihi argilo argjhi argjlo) 7621 (media-arith-sat-semantics operation argihi argjhi 7622 (halfword hi FRintkeven 0) mode 7623 max min (msr-sie-fri-hi)) 7624 (media-arith-sat-semantics operation argilo argjlo 7625 (halfword lo FRintkeven 0) mode 7626 max min (msr-sie-fri-lo)) 7627 (extract-hilo FRintieven 1 FRintjeven 1 7628 argihi argilo argjhi argjlo) 7629 (media-arith-sat-semantics operation argihi argjhi 7630 (halfword hi FRintkeven 1) mode 7631 max min (msr-sie-fri-1-hi)) 7632 (media-arith-sat-semantics operation argilo argjlo 7633 (halfword lo FRintkeven 1) mode 7634 max min (msr-sie-fri-1-lo))))) 7635) 7636 7637(define-pmacro (media-quad-arith-sat name operation mode max min op ope comment) 7638 (dni name 7639 (comment) 7640 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-2)) 7641 (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven") 7642 (+ pack FRintkeven op FRintieven ope FRintjeven) 7643 (media-quad-arith-sat-semantics 1 operation mode max min) 7644 ((fr400 (unit u-media-1-quad 7645 (in FRinti FRintieven) 7646 (in FRintj FRintjeven) 7647 (out FRintk FRintkeven))) 7648 (fr500 (unit u-media-quad-arith 7649 (in FRinti FRintieven) 7650 (in FRintj FRintjeven) 7651 (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) 7652 ) 7653) 7654 7655(media-quad-arith-sat mqaddhss add HI 32767 -32768 OP_7B OPE1_18 "Media quad add signed with saturation") 7656(media-quad-arith-sat mqaddhus add UHI 65535 0 OP_7B OPE1_19 "Media quad add unsigned with saturation") 7657 7658(media-quad-arith-sat mqsubhss sub HI 32767 -32768 OP_7B OPE1_1A "Media quad sub signed with saturation") 7659(media-quad-arith-sat mqsubhus sub UHI 65535 0 OP_7B OPE1_1B "Media quad sub unsigned with saturation") 7660 7661(define-pmacro (conditional-media-quad-arith-sat 7662 name operation mode max min op ope comment) 7663 (dni name 7664 (comment) 7665 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-2) CONDITIONAL) 7666 (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond") 7667 (+ pack FRintkeven op FRintieven CCi cond ope FRintjeven) 7668 (media-quad-arith-sat-semantics (eq CCi (or cond 2)) 7669 operation mode max min) 7670 ((fr400 (unit u-media-1-quad 7671 (in FRinti FRintieven) 7672 (in FRintj FRintjeven) 7673 (out FRintk FRintkeven))) 7674 (fr500 (unit u-media-quad-arith 7675 (in FRinti FRintieven) 7676 (in FRintj FRintjeven) 7677 (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) 7678 ) 7679) 7680 7681(conditional-media-quad-arith-sat cmqaddhss add HI 32767 -32768 OP_73 OPE4_0 "Conditional Media quad add signed with saturation") 7682(conditional-media-quad-arith-sat cmqaddhus add UHI 65535 0 OP_73 OPE4_1 "Conditional Media quad add unsigned with saturation") 7683 7684(conditional-media-quad-arith-sat cmqsubhss sub HI 32767 -32768 OP_73 OPE4_2 "Conditional Media quad sub signed with saturation") 7685(conditional-media-quad-arith-sat cmqsubhus sub UHI 65535 0 OP_73 OPE4_3 "Conditional Media quad sub unsigned with saturation") 7686 7687(define-pmacro (media-acc-arith-sat name operation mode max min op ope comment) 7688 (dni name 7689 (comment) 7690 ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) 7691 (.str name "$pack $ACC40Si,$ACC40Sk") 7692 (+ pack ACC40Sk op ACC40Si ope (ACCj-null)) 7693 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) 7694 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 7695 (if (register-unaligned ACC40Si 2) 7696 (c-call VOID "@cpu@_media_acc_not_aligned") 7697 (media-arith-sat-semantics operation ACC40Si 7698 (nextreg h-acc40S ACC40Si 1) 7699 ACC40Sk mode max min (msr-sie-acci))))) 7700 ((fr400 (unit u-media-2-acc)) (fr550 (unit u-media-4-acc))) 7701 ) 7702) 7703 7704(media-acc-arith-sat maddaccs add DI #x7fffffffff (inv DI #x7fffffffff) 7705 OP_78 OPE1_04 "Media accumulator addition") 7706(media-acc-arith-sat msubaccs sub DI #x7fffffffff (inv DI #x7fffffffff) 7707 OP_78 OPE1_05 "Media accumulator subtraction") 7708 7709(define-pmacro (media-dual-acc-arith-sat name operation mode max min op ope 7710 comment) 7711 (dni name 7712 (comment) 7713 ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) 7714 (.str name "$pack $ACC40Si,$ACC40Sk") 7715 (+ pack ACC40Sk op ACC40Si ope (ACCj-null)) 7716 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) 7717 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 7718 (if (register-unaligned ACC40Si 4) 7719 (c-call VOID "@cpu@_media_acc_not_aligned") 7720 (if (register-unaligned ACC40Sk 2) 7721 (c-call VOID "@cpu@_media_acc_not_aligned") 7722 (sequence () 7723 (media-arith-sat-semantics operation ACC40Si 7724 (nextreg h-acc40S ACC40Si 1) 7725 ACC40Sk mode max min 7726 (msr-sie-acci)) 7727 (media-arith-sat-semantics operation 7728 (nextreg h-acc40S ACC40Si 2) 7729 (nextreg h-acc40S ACC40Si 3) 7730 (nextreg h-acc40S ACC40Sk 1) 7731 mode max min 7732 (msr-sie-acci-1))))))) 7733 ((fr400 (unit u-media-2-acc-dual)) (fr550 (unit u-media-4-acc-dual))) 7734 ) 7735) 7736 7737(media-dual-acc-arith-sat mdaddaccs add DI #x7fffffffff (inv DI #x7fffffffff) 7738 OP_78 OPE1_06 "Media accumulator addition") 7739(media-dual-acc-arith-sat mdsubaccs sub DI #x7fffffffff (inv DI #x7fffffffff) 7740 OP_78 OPE1_07 "Media accumulator subtraction") 7741 7742(dni masaccs 7743 "Media add and subtract signed accumulator with saturation" 7744 ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) 7745 "masaccs$pack $ACC40Si,$ACC40Sk" 7746 (+ pack ACC40Sk OP_78 ACC40Si OPE1_08 (ACCj-null)) 7747 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) 7748 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 7749 (if (register-unaligned ACC40Si 2) 7750 (c-call VOID "@cpu@_media_acc_not_aligned") 7751 (if (register-unaligned ACC40Sk 2) 7752 (c-call VOID "@cpu@_media_acc_not_aligned") 7753 (sequence () 7754 (media-arith-sat-semantics add ACC40Si 7755 (nextreg h-acc40S ACC40Si 1) 7756 ACC40Sk DI 7757 #x7fffffffff 7758 (inv DI #x7fffffffff) 7759 (msr-sie-acci)) 7760 (media-arith-sat-semantics sub ACC40Si 7761 (nextreg h-acc40S ACC40Si 1) 7762 (nextreg h-acc40S ACC40Sk 1) 7763 DI 7764 #x7fffffffff 7765 (inv DI #x7fffffffff) 7766 (msr-sie-acci-1))))))) 7767 ((fr400 (unit u-media-2-add-sub)) (fr550 (unit u-media-4-add-sub))) 7768 ) 7769 7770(dni mdasaccs 7771 "Media add and subtract signed accumulator with saturation" 7772 ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) 7773 "mdasaccs$pack $ACC40Si,$ACC40Sk" 7774 (+ pack ACC40Sk OP_78 ACC40Si OPE1_09 (ACCj-null)) 7775 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) 7776 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 7777 (if (register-unaligned ACC40Si 4) 7778 (c-call VOID "@cpu@_media_acc_not_aligned") 7779 (if (register-unaligned ACC40Sk 4) 7780 (c-call VOID "@cpu@_media_acc_not_aligned") 7781 (sequence () 7782 (media-arith-sat-semantics add ACC40Si 7783 (nextreg h-acc40S ACC40Si 1) 7784 ACC40Sk DI 7785 #x7fffffffff 7786 (inv DI #x7fffffffff) 7787 (msr-sie-acci)) 7788 (media-arith-sat-semantics sub ACC40Si 7789 (nextreg h-acc40S ACC40Si 1) 7790 (nextreg h-acc40S ACC40Sk 1) 7791 DI 7792 #x7fffffffff 7793 (inv DI #x7fffffffff) 7794 (msr-sie-acci-1)) 7795 (media-arith-sat-semantics add 7796 (nextreg h-acc40S ACC40Si 2) 7797 (nextreg h-acc40S ACC40Si 3) 7798 (nextreg h-acc40S ACC40Sk 2) 7799 DI 7800 #x7fffffffff 7801 (inv DI #x7fffffffff) 7802 (msr-sie-acci-2)) 7803 (media-arith-sat-semantics sub 7804 (nextreg h-acc40S ACC40Si 2) 7805 (nextreg h-acc40S ACC40Si 3) 7806 (nextreg h-acc40S ACC40Sk 3) 7807 DI 7808 #x7fffffffff 7809 (inv DI #x7fffffffff) 7810 (msr-sie-acci-3))))))) 7811 ((fr400 (unit u-media-2-add-sub-dual)) (fr550 (unit u-media-4-add-sub-dual))) 7812 ) 7813 7814(define-pmacro (media-multiply-semantics conv arg1 arg2 res) 7815 (set res (mul DI (conv DI arg1) (conv DI arg2))) 7816) 7817 7818(define-pmacro (media-dual-multiply-semantics cond mode conv rhs1 rhs2) 7819 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 7820 (if (register-unaligned ACC40Sk 2) 7821 (c-call VOID "@cpu@_media_acc_not_aligned") 7822 (if cond 7823 (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) 7824 (extract-hilo FRinti 0 FRintj 0 7825 argihi argilo argjhi argjlo) 7826 (media-multiply-semantics conv argihi rhs1 ACC40Sk) 7827 (media-multiply-semantics conv argilo rhs2 7828 (nextreg h-acc40S ACC40Sk 1)))))) 7829) 7830 7831(define-pmacro (media-dual-multiply name mode conv rhs1 rhs2 op ope comment) 7832 (dni name 7833 (comment) 7834 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) PRESERVE-OVF) 7835 (.str name "$pack $FRinti,$FRintj,$ACC40Sk") 7836 (+ pack ACC40Sk op FRinti ope FRintj) 7837 (media-dual-multiply-semantics 1 mode conv rhs1 rhs2) 7838 ((fr400 (unit u-media-2)) 7839 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 7840 ) 7841) 7842 7843(media-dual-multiply mmulhs HI ext argjhi argjlo OP_7B OPE1_14 "Media dual multiply signed") 7844(media-dual-multiply mmulhu UHI zext argjhi argjlo OP_7B OPE1_15 "Media dual multiply unsigned") 7845 7846(media-dual-multiply mmulxhs HI ext argjlo argjhi OP_7B OPE1_28 "Media dual cross multiply signed") 7847(media-dual-multiply mmulxhu UHI zext argjlo argjhi OP_7B OPE1_29 "Media dual cross multiply unsigned") 7848 7849(define-pmacro (conditional-media-dual-multiply 7850 name mode conv rhs1 rhs2 op ope comment) 7851 (dni name 7852 (comment) 7853 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) 7854 PRESERVE-OVF CONDITIONAL) 7855 (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") 7856 (+ pack ACC40Sk op FRinti CCi cond ope FRintj) 7857 (media-dual-multiply-semantics (eq CCi (or cond 2)) mode conv rhs1 rhs2) 7858 ((fr400 (unit u-media-2)) 7859 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 7860 ) 7861) 7862 7863(conditional-media-dual-multiply cmmulhs HI ext argjhi argjlo OP_72 OPE4_0 "Conditional Media dual multiply signed") 7864(conditional-media-dual-multiply cmmulhu UHI zext argjhi argjlo OP_72 OPE4_1 "Conditional Media dual multiply unsigned") 7865 7866(define-pmacro (media-quad-multiply-semantics cond mode conv rhs1 rhs2) 7867 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 7868 (if (register-unaligned ACC40Sk 4) 7869 (c-call VOID "@cpu@_media_acc_not_aligned") 7870 (if (orif (register-unaligned FRintieven 2) 7871 (register-unaligned FRintjeven 2)) 7872 (c-call VOID "@cpu@_media_register_not_aligned") 7873 (if cond 7874 (sequence ((mode argihi) (mode argilo) 7875 (mode argjhi) (mode argjlo)) 7876 (extract-hilo FRintieven 0 FRintjeven 0 7877 argihi argilo argjhi argjlo) 7878 (media-multiply-semantics conv argihi rhs1 ACC40Sk) 7879 (media-multiply-semantics conv argilo rhs2 7880 (nextreg h-acc40S ACC40Sk 1)) 7881 (extract-hilo FRintieven 1 FRintjeven 1 7882 argihi argilo argjhi argjlo) 7883 (media-multiply-semantics conv argihi rhs1 7884 (nextreg h-acc40S ACC40Sk 2)) 7885 (media-multiply-semantics conv argilo rhs2 7886 (nextreg h-acc40S ACC40Sk 3))))))) 7887) 7888 7889(define-pmacro (media-quad-multiply name mode conv rhs1 rhs2 op ope comment) 7890 (dni name 7891 (comment) 7892 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2) PRESERVE-OVF) 7893 (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") 7894 (+ pack ACC40Sk op FRintieven ope FRintjeven) 7895 (media-quad-multiply-semantics 1 mode conv rhs1 rhs2) 7896 ((fr400 (unit u-media-2-quad 7897 (in FRinti FRintieven) 7898 (in FRintj FRintjeven))) 7899 (fr500 (unit u-media-quad-mul 7900 (in FRinti FRintieven) 7901 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 7902 ) 7903) 7904 7905(media-quad-multiply mqmulhs HI ext argjhi argjlo OP_7B OPE1_1C "Media quad multiply signed") 7906(media-quad-multiply mqmulhu UHI zext argjhi argjlo OP_7B OPE1_1D "Media quad multiply unsigned") 7907 7908(media-quad-multiply mqmulxhs HI ext argjlo argjhi OP_7B OPE1_2A "Media quad cross multiply signed") 7909(media-quad-multiply mqmulxhu UHI zext argjlo argjhi OP_7B OPE1_2B "Media quad cross multiply unsigned") 7910 7911(define-pmacro (conditional-media-quad-multiply 7912 name mode conv rhs1 rhs2 op ope comment) 7913 (dni name 7914 (comment) 7915 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2) 7916 PRESERVE-OVF CONDITIONAL) 7917 (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond") 7918 (+ pack ACC40Sk op FRintieven CCi cond ope FRintjeven) 7919 (media-quad-multiply-semantics (eq CCi (or cond 2)) mode conv rhs1 rhs2) 7920 ((fr400 (unit u-media-2-quad 7921 (in FRinti FRintieven) 7922 (in FRintj FRintjeven))) 7923 (fr500 (unit u-media-quad-mul 7924 (in FRinti FRintieven) 7925 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 7926 ) 7927) 7928 7929(conditional-media-quad-multiply cmqmulhs HI ext argjhi argjlo OP_74 OPE4_0 "Conditional Media quad multiply signed") 7930(conditional-media-quad-multiply cmqmulhu UHI zext argjhi argjlo OP_74 OPE4_1 "Conditional Media quad multiply unsigned") 7931 7932(define-pmacro (media-multiply-acc-semantics 7933 conv arg1 addop arg2 res max min sie) 7934 (sequence ((DI tmp)) 7935 (set tmp (addop res (mul DI (conv DI arg1) (conv DI arg2)))) 7936 (saturate-v tmp max min sie res)) 7937) 7938 7939(define-pmacro (media-dual-multiply-acc-semantics 7940 cond mode conv addop rhw res max min) 7941 (if (c-call SI "@cpu@_check_acc_range" (index-of res)) 7942 (if (register-unaligned res 2) 7943 (c-call VOID "@cpu@_media_acc_not_aligned") 7944 (if cond 7945 (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) 7946 (extract-hilo FRinti 0 FRintj 0 7947 argihi argilo argjhi argjlo) 7948 (media-multiply-acc-semantics conv argihi addop argjhi 7949 res 7950 max min (msr-sie-acci)) 7951 (media-multiply-acc-semantics conv argilo addop argjlo 7952 (nextreg rhw res 1) 7953 max min (msr-sie-acci-1)))))) 7954) 7955 7956(define-pmacro (media-dual-multiply-acc 7957 name mode conv addop rhw res max min op ope comment) 7958 (dni name 7959 (comment) 7960 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) 7961 (.str name "$pack $FRinti,$FRintj,$" res) 7962 (+ pack res op FRinti ope FRintj) 7963 (media-dual-multiply-acc-semantics 1 mode conv addop rhw res max min) 7964 ((fr400 (unit u-media-2)) 7965 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 7966 ) 7967) 7968 7969(media-dual-multiply-acc mmachs HI ext add h-acc40S ACC40Sk 7970 (const DI #x7fffffffff) (const DI #xffffff8000000000) 7971 OP_7B OPE1_16 7972 "Media dual multiply and accumulate signed") 7973 7974(media-dual-multiply-acc mmachu UHI zext add h-acc40U ACC40Uk 7975 (const DI #xffffffffff) (const DI 0) 7976 OP_7B OPE1_17 7977 "Media dual multiply and accumulate unsigned") 7978 7979(media-dual-multiply-acc mmrdhs HI ext sub h-acc40S ACC40Sk 7980 (const DI #x7fffffffff) (const DI #xffffff8000000000) 7981 OP_7B OPE1_30 7982 "Media dual multiply and reduce signed") 7983 7984(media-dual-multiply-acc mmrdhu UHI zext sub h-acc40U ACC40Uk 7985 (const DI #xffffffffff) (const DI 0) 7986 OP_7B OPE1_31 7987 "Media dual multiply and reduce unsigned") 7988 7989(define-pmacro (conditional-media-dual-multiply-acc 7990 name mode conv addop rhw res max min op ope comment) 7991 (dni name 7992 (comment) 7993 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) CONDITIONAL) 7994 (.str name "$pack $FRinti,$FRintj,$" res ",$CCi,$cond") 7995 (+ pack res op FRinti CCi cond ope FRintj) 7996 (media-dual-multiply-acc-semantics (eq CCi (or cond 2)) 7997 mode conv addop rhw res max min) 7998 ((fr400 (unit u-media-2)) 7999 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 8000 ) 8001) 8002 8003(conditional-media-dual-multiply-acc cmmachs HI ext add h-acc40S ACC40Sk 8004 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8005 OP_72 OPE4_2 8006 "Conditional Media dual multiply and accumulate signed") 8007 8008(conditional-media-dual-multiply-acc cmmachu UHI zext add h-acc40U ACC40Uk 8009 (const DI #xffffffffff) (const DI 0) 8010 OP_72 OPE4_3 8011 "Conditional Media dual multiply and accumulate unsigned") 8012 8013(define-pmacro (media-quad-multiply-acc-semantics 8014 cond mode conv addop rhw res max min) 8015 (if (c-call SI "@cpu@_check_acc_range" (index-of res)) 8016 (if (register-unaligned res 4) 8017 (c-call VOID "@cpu@_media_acc_not_aligned") 8018 (if (orif (register-unaligned FRintieven 2) 8019 (register-unaligned FRintjeven 2)) 8020 (c-call VOID "@cpu@_media_register_not_aligned") 8021 (if cond 8022 (sequence ((mode argihi) (mode argilo) 8023 (mode argjhi) (mode argjlo)) 8024 (extract-hilo FRintieven 0 FRintjeven 0 8025 argihi argilo argjhi argjlo) 8026 (media-multiply-acc-semantics conv argihi addop argjhi 8027 res 8028 max min (msr-sie-acci)) 8029 (media-multiply-acc-semantics conv argilo addop argjlo 8030 (nextreg rhw res 1) 8031 max min (msr-sie-acci-1)) 8032 (extract-hilo FRintieven 1 FRintjeven 1 8033 argihi argilo argjhi argjlo) 8034 (media-multiply-acc-semantics conv argihi addop argjhi 8035 (nextreg rhw res 2) 8036 max min (msr-sie-acci-2)) 8037 (media-multiply-acc-semantics conv argilo addop argjlo 8038 (nextreg rhw res 3) 8039 max min 8040 (msr-sie-acci-3))))))) 8041) 8042 8043(define-pmacro (media-quad-multiply-acc 8044 name mode conv addop rhw res max min op ope comment) 8045 (dni name 8046 (comment) 8047 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) 8048 (.str name "$pack $FRintieven,$FRintjeven,$" res) 8049 (+ pack res op FRintieven ope FRintjeven) 8050 (media-quad-multiply-acc-semantics 1 mode conv addop rhw res max min) 8051 ((fr400 (unit u-media-2-quad 8052 (in FRinti FRintieven) 8053 (in FRintj FRintjeven))) 8054 (fr500 (unit u-media-quad-mul 8055 (in FRinti FRintieven) 8056 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 8057 ) 8058) 8059 8060(media-quad-multiply-acc mqmachs HI ext add h-acc40S ACC40Sk 8061 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8062 OP_7B OPE1_1E 8063 "Media quad multiply and accumulate signed") 8064 8065(media-quad-multiply-acc mqmachu UHI zext add h-acc40U ACC40Uk 8066 (const DI #xffffffffff) (const DI 0) 8067 OP_7B OPE1_1F 8068 "Media quad multiply and accumulate unsigned") 8069 8070(define-pmacro (conditional-media-quad-multiply-acc 8071 name mode conv addop rhw res max min op ope comment) 8072 (dni name 8073 (comment) 8074 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2) CONDITIONAL) 8075 (.str name "$pack $FRintieven,$FRintjeven,$" res ",$CCi,$cond") 8076 (+ pack res op FRintieven CCi cond ope FRintjeven) 8077 (media-quad-multiply-acc-semantics (eq CCi (or cond 2)) 8078 mode conv addop rhw res max min) 8079 ((fr400 (unit u-media-2-quad 8080 (in FRinti FRintieven) 8081 (in FRintj FRintjeven))) 8082 (fr500 (unit u-media-quad-mul 8083 (in FRinti FRintieven) 8084 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 8085 ) 8086) 8087 8088(conditional-media-quad-multiply-acc cmqmachs HI ext add h-acc40S ACC40Sk 8089 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8090 OP_74 OPE4_2 8091 "Conditional Media quad multiply and accumulate signed") 8092 8093(conditional-media-quad-multiply-acc cmqmachu UHI zext add h-acc40U ACC40Uk 8094 (const DI #xffffffffff) (const DI 0) 8095 OP_74 OPE4_3 8096 "Conditional media quad multiply and accumulate unsigned") 8097 8098(define-pmacro (media-quad-multiply-cross-acc-semantics 8099 cond mode conv addop rhw res max min) 8100 (if (c-call SI "@cpu@_check_acc_range" (index-of res)) 8101 (if (register-unaligned res 4) 8102 (c-call VOID "@cpu@_media_acc_not_aligned") 8103 (if (orif (register-unaligned FRintieven 2) 8104 (register-unaligned FRintjeven 2)) 8105 (c-call VOID "@cpu@_media_register_not_aligned") 8106 (if cond 8107 (sequence ((mode argihi) (mode argilo) 8108 (mode argjhi) (mode argjlo)) 8109 (extract-hilo FRintieven 0 FRintjeven 0 8110 argihi argilo argjhi argjlo) 8111 (media-multiply-acc-semantics conv argihi addop argjhi 8112 (nextreg rhw res 2) 8113 max min (msr-sie-acci-2)) 8114 (media-multiply-acc-semantics conv argilo addop argjlo 8115 (nextreg rhw res 3) 8116 max min (msr-sie-acci-3)) 8117 (extract-hilo FRintieven 1 FRintjeven 1 8118 argihi argilo argjhi argjlo) 8119 (media-multiply-acc-semantics conv argihi addop argjhi 8120 res 8121 max min (msr-sie-acci)) 8122 (media-multiply-acc-semantics conv argilo addop argjlo 8123 (nextreg rhw res 1) 8124 max min 8125 (msr-sie-acci-1))))))) 8126) 8127 8128(define-pmacro (media-quad-multiply-cross-acc 8129 name mode conv addop rhw res max min op ope comment) 8130 (dni name 8131 (comment) 8132 ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) 8133 (.str name "$pack $FRintieven,$FRintjeven,$" res) 8134 (+ pack res op FRintieven ope FRintjeven) 8135 (media-quad-multiply-cross-acc-semantics 1 mode conv addop rhw res 8136 max min) 8137 ((fr400 (unit u-media-2-quad 8138 (in FRinti FRintieven) 8139 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 8140 ) 8141) 8142 8143(media-quad-multiply-cross-acc mqxmachs HI ext add h-acc40S ACC40Sk 8144 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8145 OP_78 OPE1_00 8146 "Media quad multiply and cross accumulate signed") 8147 8148(define-pmacro (media-quad-cross-multiply-cross-acc-semantics 8149 cond mode conv addop rhw res max min) 8150 (if (c-call SI "@cpu@_check_acc_range" (index-of res)) 8151 (if (register-unaligned res 4) 8152 (c-call VOID "@cpu@_media_acc_not_aligned") 8153 (if (orif (register-unaligned FRintieven 2) 8154 (register-unaligned FRintjeven 2)) 8155 (c-call VOID "@cpu@_media_register_not_aligned") 8156 (if cond 8157 (sequence ((mode argihi) (mode argilo) 8158 (mode argjhi) (mode argjlo)) 8159 (extract-hilo FRintieven 0 FRintjeven 0 8160 argihi argilo argjhi argjlo) 8161 (media-multiply-acc-semantics conv argihi addop argjlo 8162 (nextreg rhw res 2) 8163 max min (msr-sie-acci-2)) 8164 (media-multiply-acc-semantics conv argilo addop argjhi 8165 (nextreg rhw res 3) 8166 max min (msr-sie-acci-3)) 8167 (extract-hilo FRintieven 1 FRintjeven 1 8168 argihi argilo argjhi argjlo) 8169 (media-multiply-acc-semantics conv argihi addop argjlo 8170 res 8171 max min (msr-sie-acci)) 8172 (media-multiply-acc-semantics conv argilo addop argjhi 8173 (nextreg rhw res 1) 8174 max min 8175 (msr-sie-acci-1))))))) 8176) 8177 8178(define-pmacro (media-quad-cross-multiply-cross-acc 8179 name mode conv addop rhw res max min op ope comment) 8180 (dni name 8181 (comment) 8182 ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) 8183 (.str name "$pack $FRintieven,$FRintjeven,$" res) 8184 (+ pack res op FRintieven ope FRintjeven) 8185 (media-quad-cross-multiply-cross-acc-semantics 1 mode conv addop rhw res 8186 max min) 8187 ((fr400 (unit u-media-2-quad 8188 (in FRinti FRintieven) 8189 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 8190 ) 8191) 8192 8193(media-quad-cross-multiply-cross-acc mqxmacxhs HI ext add h-acc40S ACC40Sk 8194 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8195 OP_78 OPE1_01 8196 "Media quad cross multiply and cross accumulate signed") 8197 8198(define-pmacro (media-quad-cross-multiply-acc-semantics 8199 cond mode conv addop rhw res max min) 8200 (if (c-call SI "@cpu@_check_acc_range" (index-of res)) 8201 (if (register-unaligned res 4) 8202 (c-call VOID "@cpu@_media_acc_not_aligned") 8203 (if (orif (register-unaligned FRintieven 2) 8204 (register-unaligned FRintjeven 2)) 8205 (c-call VOID "@cpu@_media_register_not_aligned") 8206 (if cond 8207 (sequence ((mode argihi) (mode argilo) 8208 (mode argjhi) (mode argjlo)) 8209 (extract-hilo FRintieven 0 FRintjeven 0 8210 argihi argilo argjhi argjlo) 8211 (media-multiply-acc-semantics conv argihi addop argjlo 8212 res 8213 max min (msr-sie-acci)) 8214 (media-multiply-acc-semantics conv argilo addop argjhi 8215 (nextreg rhw res 1) 8216 max min (msr-sie-acci-1)) 8217 (extract-hilo FRintieven 1 FRintjeven 1 8218 argihi argilo argjhi argjlo) 8219 (media-multiply-acc-semantics conv argihi addop argjlo 8220 (nextreg rhw res 2) 8221 max min (msr-sie-acci-2)) 8222 (media-multiply-acc-semantics conv argilo addop argjhi 8223 (nextreg rhw res 3) 8224 max min 8225 (msr-sie-acci-3))))))) 8226) 8227 8228(define-pmacro (media-quad-cross-multiply-acc 8229 name mode conv addop rhw res max min op ope comment) 8230 (dni name 8231 (comment) 8232 ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) 8233 (.str name "$pack $FRintieven,$FRintjeven,$" res) 8234 (+ pack res op FRintieven ope FRintjeven) 8235 (media-quad-cross-multiply-acc-semantics 1 mode conv addop rhw res 8236 max min) 8237 ((fr400 (unit u-media-2-quad 8238 (in FRinti FRintieven) 8239 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 8240 ) 8241) 8242 8243(media-quad-cross-multiply-acc mqmacxhs HI ext add h-acc40S ACC40Sk 8244 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8245 OP_78 OPE1_02 8246 "Media quad cross multiply and accumulate signed") 8247 8248(define-pmacro (media-complex-semantics 8249 conv lhs1 rhs1 lhs2 rhs2 res max min sie) 8250 (sequence ((DI tmp1) (DI tmp2)) 8251 (media-multiply-semantics conv lhs1 rhs1 tmp1) 8252 (media-multiply-semantics conv lhs2 rhs2 tmp2) 8253 (set tmp1 (sub tmp1 tmp2)) 8254 (saturate-v tmp1 max min sie res)) 8255) 8256 8257(define-pmacro (media-complex-semantics-i 8258 conv lhs1 rhs1 lhs2 rhs2 res max min sie) 8259 (sequence ((DI tmp1) (DI tmp2)) 8260 (media-multiply-semantics conv lhs1 rhs1 tmp1) 8261 (media-multiply-semantics conv lhs2 rhs2 tmp2) 8262 (set tmp1 (add tmp1 tmp2)) 8263 (saturate-v tmp1 max min sie res)) 8264) 8265 8266(define-pmacro (media-dual-complex-semantics mode conv rhs1 rhs2 max min) 8267 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 8268 (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) 8269 (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) 8270 (media-complex-semantics conv argihi rhs1 argilo rhs2 ACC40Sk 8271 max min (msr-sie-acci)))) 8272) 8273 8274(define-pmacro (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min) 8275 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 8276 (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) 8277 (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) 8278 (media-complex-semantics-i conv argihi rhs1 argilo rhs2 ACC40Sk 8279 max min (msr-sie-acci)))) 8280) 8281 8282(define-pmacro (media-dual-complex 8283 name mode conv rhs1 rhs2 max min op ope comment) 8284 (dni name 8285 (comment) 8286 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) 8287 (.str name "$pack $FRinti,$FRintj,$ACC40Sk") 8288 (+ pack ACC40Sk op FRinti ope FRintj) 8289 (media-dual-complex-semantics mode conv rhs1 rhs2 max min) 8290 ((fr400 (unit u-media-2)) 8291 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 8292 ) 8293) 8294 8295(define-pmacro (media-dual-complex-i 8296 name mode conv rhs1 rhs2 max min op ope comment) 8297 (dni name 8298 (comment) 8299 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1)) 8300 (.str name "$pack $FRinti,$FRintj,$ACC40Sk") 8301 (+ pack ACC40Sk op FRinti ope FRintj) 8302 (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min) 8303 ((fr400 (unit u-media-2)) 8304 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 8305 ) 8306) 8307 8308(media-dual-complex mcpxrs HI ext argjhi argjlo 8309 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8310 OP_7B OPE1_20 8311 "Media dual complex real signed with saturation") 8312 8313(media-dual-complex mcpxru UHI zext argjhi argjlo 8314 (const DI #xffffffffff) (const DI 0) 8315 OP_7B OPE1_21 8316 "Media dual complex real unsigned with saturation") 8317 8318(media-dual-complex-i mcpxis HI ext argjlo argjhi 8319 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8320 OP_7B OPE1_22 8321 "Media dual complex imaginary signed with saturation") 8322 8323(media-dual-complex-i mcpxiu UHI zext argjlo argjhi 8324 (const DI #xffffffffff) (const DI 0) 8325 OP_7B OPE1_23 8326 "Media dual complex imaginary unsigned with saturation") 8327 8328(define-pmacro (conditional-media-dual-complex 8329 name mode conv rhs1 rhs2 max min op ope comment) 8330 (dni name 8331 (comment) 8332 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) CONDITIONAL) 8333 (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") 8334 (+ pack ACC40Sk op FRinti CCi cond ope FRintj) 8335 (if (eq CCi (or cond 2)) 8336 (media-dual-complex-semantics mode conv rhs1 rhs2 max min)) 8337 ((fr400 (unit u-media-2)) 8338 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 8339 ) 8340) 8341 8342(define-pmacro (conditional-media-dual-complex-i 8343 name mode conv rhs1 rhs2 max min op ope comment) 8344 (dni name 8345 (comment) 8346 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) CONDITIONAL) 8347 (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") 8348 (+ pack ACC40Sk op FRinti CCi cond ope FRintj) 8349 (if (eq CCi (or cond 2)) 8350 (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min)) 8351 ((fr400 (unit u-media-2)) 8352 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 8353 ) 8354) 8355 8356(conditional-media-dual-complex cmcpxrs HI ext argjhi argjlo 8357 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8358 OP_75 OPE4_0 8359 "Conditional Media dual complex real signed with saturation") 8360 8361(conditional-media-dual-complex cmcpxru UHI zext argjhi argjlo 8362 (const DI #xffffffffff) (const DI 0) 8363 OP_75 OPE4_1 8364 "Conditional Media dual complex real unsigned with saturation") 8365 8366(conditional-media-dual-complex-i cmcpxis HI ext argjlo argjhi 8367 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8368 OP_75 OPE4_2 8369 "Conditional Media dual complex imaginary signed with saturation") 8370 8371(conditional-media-dual-complex-i cmcpxiu UHI zext argjlo argjhi 8372 (const DI #xffffffffff) (const DI 0) 8373 OP_75 OPE4_3 8374 "Conditional Media dual complex imaginary unsigned with saturation") 8375 8376(define-pmacro (media-quad-complex 8377 name mode conv rhs1 rhs2 max min op ope comment) 8378 (dni name 8379 (comment) 8380 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) 8381 (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") 8382 (+ pack ACC40Sk op FRintieven ope FRintjeven) 8383 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 8384 (if (register-unaligned ACC40Sk 2) 8385 (c-call VOID "@cpu@_media_acc_not_aligned") 8386 (if (orif (register-unaligned FRintieven 2) 8387 (register-unaligned FRintjeven 2)) 8388 (c-call VOID "@cpu@_media_register_not_aligned") 8389 (sequence ((mode argihi) (mode argilo) 8390 (mode argjhi) (mode argjlo)) 8391 (extract-hilo FRintieven 0 FRintjeven 0 8392 argihi argilo argjhi argjlo) 8393 (media-complex-semantics conv argihi rhs1 argilo rhs2 8394 ACC40Sk 8395 max min (msr-sie-acci)) 8396 (extract-hilo FRintieven 1 FRintjeven 1 8397 argihi argilo argjhi argjlo) 8398 (media-complex-semantics conv argihi rhs1 argilo rhs2 8399 (nextreg h-acc40S ACC40Sk 1) 8400 max min (msr-sie-acci-1)))))) 8401 ((fr400 (unit u-media-2-quad 8402 (in FRinti FRintieven) 8403 (in FRintj FRintjeven))) 8404 (fr500 (unit u-media-quad-complex 8405 (in FRinti FRintieven) 8406 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 8407 ) 8408) 8409 8410(define-pmacro (media-quad-complex-i 8411 name mode conv rhs1 rhs2 max min op ope comment) 8412 (dni name 8413 (comment) 8414 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2)) 8415 (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") 8416 (+ pack ACC40Sk op FRintieven ope FRintjeven) 8417 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 8418 (if (register-unaligned ACC40Sk 2) 8419 (c-call VOID "@cpu@_media_acc_not_aligned") 8420 (if (orif (register-unaligned FRintieven 2) 8421 (register-unaligned FRintjeven 2)) 8422 (c-call VOID "@cpu@_media_register_not_aligned") 8423 (sequence ((mode argihi) (mode argilo) 8424 (mode argjhi) (mode argjlo)) 8425 (extract-hilo FRintieven 0 FRintjeven 0 8426 argihi argilo argjhi argjlo) 8427 (media-complex-semantics-i conv argihi rhs1 argilo rhs2 8428 ACC40Sk 8429 max min (msr-sie-acci)) 8430 (extract-hilo FRintieven 1 FRintjeven 1 8431 argihi argilo argjhi argjlo) 8432 (media-complex-semantics-i conv argihi rhs1 argilo rhs2 8433 (nextreg h-acc40S ACC40Sk 1) 8434 max min (msr-sie-acci-1)))))) 8435 ((fr400 (unit u-media-2-quad 8436 (in FRinti FRintieven) 8437 (in FRintj FRintjeven))) 8438 (fr500 (unit u-media-quad-complex 8439 (in FRinti FRintieven) 8440 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 8441 ) 8442) 8443 8444(media-quad-complex mqcpxrs HI ext argjhi argjlo 8445 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8446 OP_7B OPE1_24 8447 "Media quad complex real signed with saturation") 8448 8449(media-quad-complex mqcpxru UHI zext argjhi argjlo 8450 (const DI #xffffffffff) (const DI 0) 8451 OP_7B OPE1_25 8452 "Media quad complex real unsigned with saturation") 8453 8454(media-quad-complex-i mqcpxis HI ext argjlo argjhi 8455 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8456 OP_7B OPE1_26 8457 "Media quad complex imaginary signed with saturation") 8458 8459(media-quad-complex-i mqcpxiu UHI zext argjlo argjhi 8460 (const DI #xffffffffff) (const DI 0) 8461 OP_7B OPE1_27 8462 "Media quad complex imaginary unsigned with saturation") 8463 8464(define-pmacro (media-pack src1 src2 targ offset) 8465 (sequence () 8466 (set (halfword hi targ offset) (halfword lo src1 offset)) 8467 (set (halfword lo targ offset) (halfword lo src2 offset))) 8468) 8469 8470(define-pmacro (media-expand-halfword-to-word-semantics cond) 8471 (if cond 8472 (sequence ((UHI tmp)) 8473 (if (and u6 1) 8474 (set tmp (halfword lo FRinti 0)) 8475 (set tmp (halfword hi FRinti 0))) 8476 (set (halfword hi FRintk 0) tmp) 8477 (set (halfword lo FRintk 0) tmp))) 8478) 8479 8480(dni mexpdhw 8481 "Media expand halfword to word" 8482 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) 8483 "mexpdhw$pack $FRinti,$u6,$FRintk" 8484 (+ pack FRintk OP_7B FRinti OPE1_32 u6) 8485 (media-expand-halfword-to-word-semantics 1) 8486 ((fr400 (unit u-media-3)) 8487 (fr500 (unit u-media)) (fr550 (unit u-media))) 8488) 8489 8490(dni cmexpdhw 8491 "Conditional media expand halfword to word" 8492 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1) CONDITIONAL) 8493 "cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond" 8494 (+ pack FRintk OP_76 FRinti CCi cond OPE4_2 u6) 8495 (media-expand-halfword-to-word-semantics (eq CCi (or cond 2))) 8496 ((fr400 (unit u-media-3)) 8497 (fr500 (unit u-media)) (fr550 (unit u-media))) 8498) 8499 8500(define-pmacro (media-expand-halfword-to-double-semantics cond) 8501 (if (register-unaligned FRintkeven 2) 8502 (c-call VOID "@cpu@_media_register_not_aligned") 8503 (if cond 8504 (sequence ((UHI tmp)) 8505 ; a hack to get FRintkeven referenced for profiling 8506 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 8507 (if (and u6 1) 8508 (set tmp (halfword lo FRinti 0)) 8509 (set tmp (halfword hi FRinti 0))) 8510 (set (halfword hi FRintkeven 0) tmp) 8511 (set (halfword lo FRintkeven 0) tmp) 8512 (set (halfword hi FRintkeven 1) tmp) 8513 (set (halfword lo FRintkeven 1) tmp)))) 8514) 8515 8516(dni mexpdhd 8517 "Media expand halfword to double" 8518 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) 8519 "mexpdhd$pack $FRinti,$u6,$FRintkeven" 8520 (+ pack FRintkeven OP_7B FRinti OPE1_33 u6) 8521 (media-expand-halfword-to-double-semantics 1) 8522 ((fr400 (unit u-media-dual-expand 8523 (out FRintk FRintkeven))) 8524 (fr500 (unit u-media-dual-expand 8525 (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand))) 8526) 8527 8528(dni cmexpdhd 8529 "Conditional media expand halfword to double" 8530 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2) CONDITIONAL) 8531 "cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond" 8532 (+ pack FRintkeven OP_76 FRinti CCi cond OPE4_3 u6) 8533 (media-expand-halfword-to-double-semantics (eq CCi (or cond 2))) 8534 ((fr400 (unit u-media-dual-expand 8535 (out FRintk FRintkeven))) 8536 (fr500 (unit u-media-dual-expand 8537 (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand))) 8538) 8539 8540(dni mpackh 8541 "Media halfword pack" 8542 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) 8543 "mpackh$pack $FRinti,$FRintj,$FRintk" 8544 (+ pack FRintk OP_7B FRinti OPE1_34 FRintj) 8545 (media-pack FRinti FRintj FRintk 0) 8546 ((fr400 (unit u-media-3)) 8547 (fr500 (unit u-media)) (fr550 (unit u-media))) 8548) 8549 8550(dni mdpackh 8551 "Media dual pack" 8552 ((UNIT FM01) (FR500-MAJOR M-5) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) 8553 "mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven" 8554 (+ pack FRintkeven OP_7B FRintieven OPE1_36 FRintjeven) 8555 (if (orif (register-unaligned FRintieven 2) 8556 (orif (register-unaligned FRintjeven 2) 8557 (register-unaligned FRintkeven 2))) 8558 (c-call VOID "@cpu@_media_register_not_aligned") 8559 (sequence () 8560 ; hack to get these referenced for profiling 8561 (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven)) 8562 (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven)) 8563 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 8564 (media-pack FRintieven FRintjeven FRintkeven 0) 8565 (media-pack FRintieven FRintjeven FRintkeven 1))) 8566 ((fr400 (unit u-media-3-quad 8567 (in FRinti FRintieven) 8568 (in FRintj FRintjeven) 8569 (out FRintk FRintkeven))) 8570 (fr500 (unit u-media-quad-arith 8571 (in FRinti FRintieven) 8572 (in FRintj FRintjeven) 8573 (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) 8574) 8575 8576(define-pmacro (media-unpack src soff targ toff) 8577 (sequence () 8578 (set (halfword hi targ toff) (halfword hi src soff)) 8579 (set (halfword lo targ toff) (halfword hi src soff)) 8580 (set (halfword hi targ (add toff 1)) (halfword lo src soff)) 8581 (set (halfword lo targ (add toff 1)) (halfword lo src soff))) 8582) 8583 8584(dni munpackh 8585 "Media halfword unpack" 8586 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) 8587 "munpackh$pack $FRinti,$FRintkeven" 8588 (+ pack FRintkeven OP_7B FRinti OPE1_35 (FRj-null)) 8589 (if (register-unaligned FRintkeven 2) 8590 (c-call VOID "@cpu@_media_register_not_aligned") 8591 (sequence () 8592 ; hack to get these referenced for profiling 8593 (set FRinti (c-raw-call SI "frv_ref_SI" FRinti)) 8594 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 8595 (media-unpack FRinti 0 FRintkeven 0))) 8596 ((fr400 (unit u-media-dual-expand 8597 (out FRintk FRintkeven))) 8598 (fr500 (unit u-media-dual-expand 8599 (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand))) 8600) 8601 8602(dni mdunpackh 8603 "Media dual unpack" 8604 ((UNIT FM01) (FR500-MAJOR M-7) (MACH simple,tomcat,frv)) 8605 "mdunpackh$pack $FRintieven,$FRintk" 8606 (+ pack FRintk OP_7B FRintieven OPE1_37 (FRj-null)) 8607 (if (orif (register-unaligned FRintieven 2) (register-unaligned FRintk 4)) 8608 (c-call VOID "@cpu@_media_register_not_aligned") 8609 (sequence () 8610 ; hack to get these referenced for profiling 8611 (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven)) 8612 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 8613 (media-unpack FRintieven 0 FRintk 0) 8614 (media-unpack FRintieven 1 FRintk 2))) 8615 ((fr500 (unit u-media-dual-unpack 8616 (in FRinti FRintieven)))) 8617) 8618 8619(define-pmacro (ubyte num arg offset) 8620 (reg (.sym h-fr_ num) (add (index-of arg) offset))) 8621 8622(define-pmacro (mbtoh-semantics cond) 8623 (if (register-unaligned FRintkeven 2) 8624 (c-call VOID "@cpu@_media_register_not_aligned") 8625 (if cond 8626 (sequence () 8627 (set (halfword hi FRintkeven 0) (ubyte 3 FRintj 0)) 8628 (set (halfword lo FRintkeven 0) (ubyte 2 FRintj 0)) 8629 (set (halfword hi FRintkeven 1) (ubyte 1 FRintj 0)) 8630 (set (halfword lo FRintkeven 1) (ubyte 0 FRintj 0))))) 8631) 8632 8633(dni mbtoh 8634 "Media convert byte to halfword" 8635 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) 8636 "mbtoh$pack $FRintj,$FRintkeven" 8637 (+ pack FRintkeven OP_7B (FRi-null) OPE1_38 FRintj) 8638 (sequence () 8639 ; hack to get these referenced for profiling 8640 (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) 8641 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 8642 (mbtoh-semantics 1)) 8643 ((fr400 (unit u-media-dual-expand 8644 (out FRintk FRintkeven))) 8645 (fr500 (unit u-media-dual-btoh 8646 (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand))) 8647) 8648 8649(dni cmbtoh 8650 "Conditional media convert byte to halfword" 8651 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2) CONDITIONAL) 8652 "cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond" 8653 (+ pack FRintkeven OP_77 (FRi-null) CCi cond OPE4_0 FRintj) 8654 (sequence () 8655 ; hack to get these referenced for profiling 8656 (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) 8657 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 8658 (mbtoh-semantics (eq CCi (or cond 2)))) 8659 ((fr400 (unit u-media-dual-expand 8660 (out FRintk FRintkeven))) 8661 (fr500 (unit u-media-dual-btoh 8662 (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand (in FRinti FRintj)))) 8663) 8664 8665(define-pmacro (mhtob-semantics cond) 8666 (if (register-unaligned FRintjeven 2) 8667 (c-call VOID "@cpu@_media_register_not_aligned") 8668 (if cond 8669 (sequence () 8670 (set (ubyte 3 FRintk 0) (halfword hi FRintjeven 0)) 8671 (set (ubyte 2 FRintk 0) (halfword lo FRintjeven 0)) 8672 (set (ubyte 1 FRintk 0) (halfword hi FRintjeven 1)) 8673 (set (ubyte 0 FRintk 0) (halfword lo FRintjeven 1))))) 8674) 8675 8676(dni mhtob 8677 "Media convert halfword to byte" 8678 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) 8679 "mhtob$pack $FRintjeven,$FRintk" 8680 (+ pack FRintk OP_7B (FRi-null) OPE1_39 FRintjeven) 8681 (sequence () 8682 ; hack to get these referenced for profiling 8683 (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven)) 8684 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 8685 (mhtob-semantics 1)) 8686 ((fr400 (unit u-media-dual-htob 8687 (in FRintj FRintjeven))) 8688 (fr500 (unit u-media-dual-htob 8689 (in FRintj FRintjeven))) (fr550 (unit u-media-3-dual (in FRinti FRintjeven)))) 8690) 8691 8692(dni cmhtob 8693 "Conditional media convert halfword to byte" 8694 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2) CONDITIONAL) 8695 "cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond" 8696 (+ pack FRintk OP_77 (FRi-null) CCi cond OPE4_1 FRintjeven) 8697 (sequence () 8698 ; hack to get these referenced for profiling 8699 (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven)) 8700 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 8701 (mhtob-semantics (eq CCi (or cond 2)))) 8702 ((fr400 (unit u-media-dual-htob 8703 (in FRintj FRintjeven))) 8704 (fr500 (unit u-media-dual-htob 8705 (in FRintj FRintjeven))) (fr550 (unit u-media-3-dual (in FRinti FRintjeven)))) 8706) 8707 8708(define-pmacro (mbtohe-semantics cond) 8709 (if (register-unaligned FRintk 4) 8710 (c-call VOID "@cpu@_media_register_not_aligned") 8711 (if cond 8712 (sequence () 8713 (set (halfword hi FRintk 0) (ubyte 3 FRintj 0)) 8714 (set (halfword lo FRintk 0) (ubyte 3 FRintj 0)) 8715 (set (halfword hi FRintk 1) (ubyte 2 FRintj 0)) 8716 (set (halfword lo FRintk 1) (ubyte 2 FRintj 0)) 8717 (set (halfword hi FRintk 2) (ubyte 1 FRintj 0)) 8718 (set (halfword lo FRintk 2) (ubyte 1 FRintj 0)) 8719 (set (halfword hi FRintk 3) (ubyte 0 FRintj 0)) 8720 (set (halfword lo FRintk 3) (ubyte 0 FRintj 0))))) 8721) 8722 8723(dni mbtohe 8724 "Media convert byte to halfword extended" 8725 ((UNIT FM01) (FR500-MAJOR M-7) (MACH simple,tomcat,frv)) 8726 "mbtohe$pack $FRintj,$FRintk" 8727 (+ pack FRintk OP_7B (FRi-null) OPE1_3A FRintj) 8728 (sequence () 8729 ; hack to get these referenced for profiling 8730 (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) 8731 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 8732 (mbtohe-semantics 1)) 8733 ((fr500 (unit u-media-dual-btohe))) 8734) 8735 8736(dni cmbtohe 8737 "Conditional media convert byte to halfword extended" 8738 ((UNIT FM01) (FR500-MAJOR M-7) CONDITIONAL (MACH simple,tomcat,frv)) 8739 "cmbtohe$pack $FRintj,$FRintk,$CCi,$cond" 8740 (+ pack FRintk OP_77 (FRi-null) CCi cond OPE4_2 FRintj) 8741 (sequence () 8742 ; hack to get these referenced for profiling 8743 (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) 8744 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 8745 (mbtohe-semantics (eq CCi (or cond 2)))) 8746 ((fr500 (unit u-media-dual-btohe))) 8747) 8748 8749; Media NOP 8750; A special case of mclracc 8751(dni mnop "Media nop" 8752 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-1) (FR400-MAJOR M-1)) 8753 "mnop$pack" 8754 (+ pack (f-ACC40Sk 63) OP_7B (f-A 1) (misc-null-10) OPE1_3B (FRj-null)) 8755 (nop) 8756 () 8757) 8758 8759; mclracc with #A==0 8760(dni mclracc-0 8761 "Media clear accumulator(s)" 8762 ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) 8763 "mclracc$pack $ACC40Sk,$A0" 8764 (+ pack ACC40Sk OP_7B (f-A 0) (misc-null-10) OPE1_3B (FRj-null)) 8765 (c-call VOID "@cpu@_clear_accumulators" (index-of ACC40Sk) 0) 8766 ((fr400 (unit u-media-4)) 8767 (fr500 (unit u-media)) (fr550 (unit u-media-3-mclracc))) 8768) 8769 8770; mclracc with #A==1 8771(dni mclracc-1 8772 "Media clear accumulator(s)" 8773 ((UNIT MCLRACC-1) (FR500-MAJOR M-6) (FR550-MAJOR M-3) (FR400-MAJOR M-2)) 8774 "mclracc$pack $ACC40Sk,$A1" 8775 (+ pack ACC40Sk OP_7B (f-A 1) (misc-null-10) OPE1_3B (FRj-null)) 8776 (c-call VOID "@cpu@_clear_accumulators" (index-of ACC40Sk) 1) 8777 ((fr400 (unit u-media-4)) 8778 (fr500 (unit u-media)) (fr550 (unit u-media-3-mclracc))) 8779) 8780 8781(dni mrdacc 8782 "Media read accumulator" 8783 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) 8784 "mrdacc$pack $ACC40Si,$FRintk" 8785 (+ pack FRintk OP_7B ACC40Si OPE1_3C (FRj-null)) 8786 (set FRintk ACC40Si) 8787 ((fr400 (unit u-media-4)) 8788 (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) 8789) 8790 8791(dni mrdaccg 8792 "Media read accumulator guard" 8793 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) 8794 "mrdaccg$pack $ACCGi,$FRintk" 8795 (+ pack FRintk OP_7B ACCGi OPE1_3E (FRj-null)) 8796 (set FRintk ACCGi) 8797 ((fr400 (unit u-media-4-accg)) 8798 (fr500 (unit u-media)) (fr550 (unit u-media-3-acc (in ACC40Si ACCGi)))) 8799) 8800 8801(dni mwtacc 8802 "Media write accumulator" 8803 ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) 8804 "mwtacc$pack $FRinti,$ACC40Sk" 8805 (+ pack ACC40Sk OP_7B FRinti OPE1_3D (FRj-null)) 8806 (set ACC40Sk (or (and ACC40Sk (const DI #xffffffff00000000)) 8807 FRinti)) 8808 ((fr400 (unit u-media-4)) 8809 (fr500 (unit u-media)) (fr550 (unit u-media-3-wtacc))) 8810) 8811 8812(dni mwtaccg 8813 "Media write accumulator guard" 8814 ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) (FR400-MAJOR M-1)) 8815 "mwtaccg$pack $FRinti,$ACCGk" 8816 (+ pack ACCGk OP_7B FRinti OPE1_3F (FRj-null)) 8817 (sequence () 8818 ; hack to get these referenced for profiling 8819 (c-raw-call VOID "frv_ref_SI" ACCGk) 8820 (set ACCGk FRinti)) 8821 ((fr400 (unit u-media-4-accg)) 8822 (fr500 (unit u-media)) (fr550 (unit u-media-3-wtacc (in ACC40Sk ACCGk)))) 8823) 8824 8825(define-pmacro (media-cop num op) 8826 (dni (.sym mcop num) 8827 "Media custom instruction" 8828 ((UNIT FM01) (FR500-MAJOR M-1) (MACH frv)) 8829 (.str "mcop" num "$pack $FRi,$FRj,$FRk") 8830 (+ pack FRk op FRi OPE1_00 FRj) 8831 (c-call VOID "@cpu@_media_cop" num) 8832 () 8833 ) 8834) 8835 8836(media-cop 1 OP_7C) 8837(media-cop 2 OP_7D) 8838 8839; nop 8840; A nop is defined to be a "ori gr0,0,gr0" 8841; This needn't be a macro-insn, but making it one greatly simplifies decode.c 8842; On the other hand spending a little time in the decoder is often worth it. 8843; 8844(dnmi nop "nop" 8845 ((UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1)) 8846 "nop$pack" 8847 (emit ori pack (GRi 0) (s12 0) (GRk 0)) 8848) 8849 8850; Floating point NOP 8851(dni fnop 8852 "Floating point nop" 8853 ((UNIT FMALL) (FR500-MAJOR F-8) (FR550-MAJOR F-1) (MACH simple,tomcat,fr500,fr550,frv)) 8854 "fnop$pack" 8855 (+ pack (rd-null) OP_79 (FRi-null) OPE1_0D (FRj-null)) 8856 (nop) 8857 () 8858) 8859 8860; A return instruction 8861(dnmi ret "return" 8862 (NO-DIS (UNIT B01) (FR500-MAJOR B-3) (FR400-MAJOR B-3)) 8863 "ret$pack" 8864 (emit bralr pack (hint_taken 2)) 8865) 8866 8867(dnmi cmp "compare" 8868 (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1)) 8869 "cmp$pack $GRi,$GRj,$ICCi_1" 8870 (emit subcc pack GRi GRj (GRk 0) ICCi_1) 8871) 8872 8873(dnmi cmpi "compare immediate" 8874 (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1)) 8875 "cmpi$pack $GRi,$s10,$ICCi_1" 8876 (emit subicc pack GRi s10 (GRk 0) ICCi_1) 8877) 8878 8879(dnmi ccmp "conditional compare" 8880 (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) 8881 "ccmp$pack $GRi,$GRj,$CCi,$cond" 8882 (emit csubcc pack GRi GRj (GRk 0) CCi cond) 8883) 8884 8885(dnmi mov "move" 8886 (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1)) 8887 "mov$pack $GRi,$GRk" 8888 (emit ori pack GRi (s12 0) GRk) 8889) 8890 8891(dnmi cmov "conditional move" 8892 (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL) 8893 "cmov$pack $GRi,$GRk,$CCi,$cond" 8894 (emit cor pack GRi (GRj 0) GRk CCi cond) 8895) 8896