1 /* i386.c -- Assemble code for the Intel 80386 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004 4 Free Software Foundation, Inc. 5 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS; see the file COPYING. If not, write to the Free 20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 21 02111-1307, USA. */ 22 23 /* Intel 80386 machine specific gas. 24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu). 25 x86_64 support by Jan Hubicka (jh@suse.cz) 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz) 27 Bugs & suggestions are completely welcome. This is free software. 28 Please help us make it better. */ 29 30 #include "as.h" 31 #include "safe-ctype.h" 32 #include "subsegs.h" 33 #include "dwarf2dbg.h" 34 #include "dw2gencfi.h" 35 #include "opcode/i386.h" 36 37 #ifndef REGISTER_WARNINGS 38 #define REGISTER_WARNINGS 1 39 #endif 40 41 #ifndef INFER_ADDR_PREFIX 42 #define INFER_ADDR_PREFIX 1 43 #endif 44 45 #ifndef SCALE1_WHEN_NO_INDEX 46 /* Specifying a scale factor besides 1 when there is no index is 47 futile. eg. `mov (%ebx,2),%al' does exactly the same as 48 `mov (%ebx),%al'. To slavishly follow what the programmer 49 specified, set SCALE1_WHEN_NO_INDEX to 0. */ 50 #define SCALE1_WHEN_NO_INDEX 1 51 #endif 52 53 #ifndef DEFAULT_ARCH 54 #define DEFAULT_ARCH "i386" 55 #endif 56 57 #ifndef INLINE 58 #if __GNUC__ >= 2 59 #define INLINE __inline__ 60 #else 61 #define INLINE 62 #endif 63 #endif 64 65 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int)); 66 static INLINE int fits_in_signed_byte PARAMS ((offsetT)); 67 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT)); 68 static INLINE int fits_in_unsigned_word PARAMS ((offsetT)); 69 static INLINE int fits_in_signed_word PARAMS ((offsetT)); 70 static INLINE int fits_in_unsigned_long PARAMS ((offsetT)); 71 static INLINE int fits_in_signed_long PARAMS ((offsetT)); 72 static int smallest_imm_type PARAMS ((offsetT)); 73 static offsetT offset_in_range PARAMS ((offsetT, int)); 74 static int add_prefix PARAMS ((unsigned int)); 75 static void set_code_flag PARAMS ((int)); 76 static void set_16bit_gcc_code_flag PARAMS ((int)); 77 static void set_intel_syntax PARAMS ((int)); 78 static void set_cpu_arch PARAMS ((int)); 79 static char *output_invalid PARAMS ((int c)); 80 static int i386_operand PARAMS ((char *operand_string)); 81 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); 82 static const reg_entry *parse_register PARAMS ((char *reg_string, 83 char **end_op)); 84 static char *parse_insn PARAMS ((char *, char *)); 85 static char *parse_operands PARAMS ((char *, const char *)); 86 static void swap_operands PARAMS ((void)); 87 static void optimize_imm PARAMS ((void)); 88 static void optimize_disp PARAMS ((void)); 89 static int match_template PARAMS ((void)); 90 static int check_string PARAMS ((void)); 91 static int process_suffix PARAMS ((void)); 92 static int check_byte_reg PARAMS ((void)); 93 static int check_long_reg PARAMS ((void)); 94 static int check_qword_reg PARAMS ((void)); 95 static int check_word_reg PARAMS ((void)); 96 static int finalize_imm PARAMS ((void)); 97 static int process_operands PARAMS ((void)); 98 static const seg_entry *build_modrm_byte PARAMS ((void)); 99 static void output_insn PARAMS ((void)); 100 static void output_branch PARAMS ((void)); 101 static void output_jump PARAMS ((void)); 102 static void output_interseg_jump PARAMS ((void)); 103 static void output_imm PARAMS ((fragS *insn_start_frag, 104 offsetT insn_start_off)); 105 static void output_disp PARAMS ((fragS *insn_start_frag, 106 offsetT insn_start_off)); 107 #ifndef I386COFF 108 static void s_bss PARAMS ((int)); 109 #endif 110 111 static const char *default_arch = DEFAULT_ARCH; 112 113 /* 'md_assemble ()' gathers together information and puts it into a 114 i386_insn. */ 115 116 union i386_op 117 { 118 expressionS *disps; 119 expressionS *imms; 120 const reg_entry *regs; 121 }; 122 123 struct _i386_insn 124 { 125 /* TM holds the template for the insn were currently assembling. */ 126 template tm; 127 128 /* SUFFIX holds the instruction mnemonic suffix if given. 129 (e.g. 'l' for 'movl') */ 130 char suffix; 131 132 /* OPERANDS gives the number of given operands. */ 133 unsigned int operands; 134 135 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number 136 of given register, displacement, memory operands and immediate 137 operands. */ 138 unsigned int reg_operands, disp_operands, mem_operands, imm_operands; 139 140 /* TYPES [i] is the type (see above #defines) which tells us how to 141 use OP[i] for the corresponding operand. */ 142 unsigned int types[MAX_OPERANDS]; 143 144 /* Displacement expression, immediate expression, or register for each 145 operand. */ 146 union i386_op op[MAX_OPERANDS]; 147 148 /* Flags for operands. */ 149 unsigned int flags[MAX_OPERANDS]; 150 #define Operand_PCrel 1 151 152 /* Relocation type for operand */ 153 enum bfd_reloc_code_real reloc[MAX_OPERANDS]; 154 155 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode 156 the base index byte below. */ 157 const reg_entry *base_reg; 158 const reg_entry *index_reg; 159 unsigned int log2_scale_factor; 160 161 /* SEG gives the seg_entries of this insn. They are zero unless 162 explicit segment overrides are given. */ 163 const seg_entry *seg[2]; 164 165 /* PREFIX holds all the given prefix opcodes (usually null). 166 PREFIXES is the number of prefix opcodes. */ 167 unsigned int prefixes; 168 unsigned char prefix[MAX_PREFIXES]; 169 170 /* RM and SIB are the modrm byte and the sib byte where the 171 addressing modes of this insn are encoded. */ 172 173 modrm_byte rm; 174 rex_byte rex; 175 sib_byte sib; 176 }; 177 178 typedef struct _i386_insn i386_insn; 179 180 /* List of chars besides those in app.c:symbol_chars that can start an 181 operand. Used to prevent the scrubber eating vital white-space. */ 182 #ifdef LEX_AT 183 const char extra_symbol_chars[] = "*%-(@["; 184 #else 185 const char extra_symbol_chars[] = "*%-(["; 186 #endif 187 188 #if (defined (TE_I386AIX) \ 189 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ 190 && !defined (TE_LINUX) \ 191 && !defined (TE_FreeBSD) \ 192 && !defined (TE_NetBSD) \ 193 && !defined (TE_OpenBSD))) 194 /* This array holds the chars that always start a comment. If the 195 pre-processor is disabled, these aren't very useful. */ 196 const char comment_chars[] = "#/"; 197 #define PREFIX_SEPARATOR '\\' 198 199 /* This array holds the chars that only start a comment at the beginning of 200 a line. If the line seems to have the form '# 123 filename' 201 .line and .file directives will appear in the pre-processed output. 202 Note that input_file.c hand checks for '#' at the beginning of the 203 first line of the input file. This is because the compiler outputs 204 #NO_APP at the beginning of its output. 205 Also note that comments started like this one will always work if 206 '/' isn't otherwise defined. */ 207 const char line_comment_chars[] = "#"; 208 209 #else 210 /* Putting '/' here makes it impossible to use the divide operator. 211 However, we need it for compatibility with SVR4 systems. */ 212 const char comment_chars[] = "#"; 213 #define PREFIX_SEPARATOR '/' 214 215 const char line_comment_chars[] = "/#"; 216 #endif 217 218 const char line_separator_chars[] = ";"; 219 220 /* Chars that can be used to separate mant from exp in floating point 221 nums. */ 222 const char EXP_CHARS[] = "eE"; 223 224 /* Chars that mean this number is a floating point constant 225 As in 0f12.456 226 or 0d1.2345e12. */ 227 const char FLT_CHARS[] = "fFdDxX"; 228 229 /* Tables for lexical analysis. */ 230 static char mnemonic_chars[256]; 231 static char register_chars[256]; 232 static char operand_chars[256]; 233 static char identifier_chars[256]; 234 static char digit_chars[256]; 235 236 /* Lexical macros. */ 237 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) 238 #define is_operand_char(x) (operand_chars[(unsigned char) x]) 239 #define is_register_char(x) (register_chars[(unsigned char) x]) 240 #define is_space_char(x) ((x) == ' ') 241 #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) 242 #define is_digit_char(x) (digit_chars[(unsigned char) x]) 243 244 /* All non-digit non-letter characters that may occur in an operand. */ 245 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; 246 247 /* md_assemble() always leaves the strings it's passed unaltered. To 248 effect this we maintain a stack of saved characters that we've smashed 249 with '\0's (indicating end of strings for various sub-fields of the 250 assembler instruction). */ 251 static char save_stack[32]; 252 static char *save_stack_p; 253 #define END_STRING_AND_SAVE(s) \ 254 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) 255 #define RESTORE_END_STRING(s) \ 256 do { *(s) = *--save_stack_p; } while (0) 257 258 /* The instruction we're assembling. */ 259 static i386_insn i; 260 261 /* Possible templates for current insn. */ 262 static const templates *current_templates; 263 264 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ 265 static expressionS disp_expressions[2], im_expressions[2]; 266 267 /* Current operand we are working on. */ 268 static int this_operand; 269 270 /* We support four different modes. FLAG_CODE variable is used to distinguish 271 these. */ 272 273 enum flag_code { 274 CODE_32BIT, 275 CODE_16BIT, 276 CODE_64BIT }; 277 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1) 278 279 static enum flag_code flag_code; 280 static int use_rela_relocations = 0; 281 282 /* The names used to print error messages. */ 283 static const char *flag_code_names[] = 284 { 285 "32", 286 "16", 287 "64" 288 }; 289 290 /* 1 for intel syntax, 291 0 if att syntax. */ 292 static int intel_syntax = 0; 293 294 /* 1 if register prefix % not required. */ 295 static int allow_naked_reg = 0; 296 297 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, 298 leave, push, and pop instructions so that gcc has the same stack 299 frame as in 32 bit mode. */ 300 static char stackop_size = '\0'; 301 302 /* Non-zero to optimize code alignment. */ 303 int optimize_align_code = 1; 304 305 /* Non-zero to quieten some warnings. */ 306 static int quiet_warnings = 0; 307 308 /* CPU name. */ 309 static const char *cpu_arch_name = NULL; 310 311 /* CPU feature flags. */ 312 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64; 313 314 /* If set, conditional jumps are not automatically promoted to handle 315 larger than a byte offset. */ 316 static unsigned int no_cond_jump_promotion = 0; 317 318 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ 319 symbolS *GOT_symbol; 320 321 /* The dwarf2 return column, adjusted for 32 or 64 bit. */ 322 unsigned int x86_dwarf2_return_column; 323 324 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 325 int x86_cie_data_alignment; 326 327 /* Interface to relax_segment. 328 There are 3 major relax states for 386 jump insns because the 329 different types of jumps add different sizes to frags when we're 330 figuring out what sort of jump to choose to reach a given label. */ 331 332 /* Types. */ 333 #define UNCOND_JUMP 0 334 #define COND_JUMP 1 335 #define COND_JUMP86 2 336 337 /* Sizes. */ 338 #define CODE16 1 339 #define SMALL 0 340 #define SMALL16 (SMALL | CODE16) 341 #define BIG 2 342 #define BIG16 (BIG | CODE16) 343 344 #ifndef INLINE 345 #ifdef __GNUC__ 346 #define INLINE __inline__ 347 #else 348 #define INLINE 349 #endif 350 #endif 351 352 #define ENCODE_RELAX_STATE(type, size) \ 353 ((relax_substateT) (((type) << 2) | (size))) 354 #define TYPE_FROM_RELAX_STATE(s) \ 355 ((s) >> 2) 356 #define DISP_SIZE_FROM_RELAX_STATE(s) \ 357 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) 358 359 /* This table is used by relax_frag to promote short jumps to long 360 ones where necessary. SMALL (short) jumps may be promoted to BIG 361 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We 362 don't allow a short jump in a 32 bit code segment to be promoted to 363 a 16 bit offset jump because it's slower (requires data size 364 prefix), and doesn't work, unless the destination is in the bottom 365 64k of the code segment (The top 16 bits of eip are zeroed). */ 366 367 const relax_typeS md_relax_table[] = 368 { 369 /* The fields are: 370 1) most positive reach of this state, 371 2) most negative reach of this state, 372 3) how many bytes this mode will have in the variable part of the frag 373 4) which index into the table to try if we can't fit into this one. */ 374 375 /* UNCOND_JUMP states. */ 376 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, 377 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, 378 /* dword jmp adds 4 bytes to frag: 379 0 extra opcode bytes, 4 displacement bytes. */ 380 {0, 0, 4, 0}, 381 /* word jmp adds 2 byte2 to frag: 382 0 extra opcode bytes, 2 displacement bytes. */ 383 {0, 0, 2, 0}, 384 385 /* COND_JUMP states. */ 386 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, 387 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, 388 /* dword conditionals adds 5 bytes to frag: 389 1 extra opcode byte, 4 displacement bytes. */ 390 {0, 0, 5, 0}, 391 /* word conditionals add 3 bytes to frag: 392 1 extra opcode byte, 2 displacement bytes. */ 393 {0, 0, 3, 0}, 394 395 /* COND_JUMP86 states. */ 396 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, 397 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, 398 /* dword conditionals adds 5 bytes to frag: 399 1 extra opcode byte, 4 displacement bytes. */ 400 {0, 0, 5, 0}, 401 /* word conditionals add 4 bytes to frag: 402 1 displacement byte and a 3 byte long branch insn. */ 403 {0, 0, 4, 0} 404 }; 405 406 static const arch_entry cpu_arch[] = { 407 {"i8086", Cpu086 }, 408 {"i186", Cpu086|Cpu186 }, 409 {"i286", Cpu086|Cpu186|Cpu286 }, 410 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, 411 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, 412 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, 413 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, 414 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, 415 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, 416 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 }, 417 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow }, 418 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow }, 419 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 }, 420 {NULL, 0 } 421 }; 422 423 const pseudo_typeS md_pseudo_table[] = 424 { 425 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) 426 {"align", s_align_bytes, 0}, 427 #else 428 {"align", s_align_ptwo, 0}, 429 #endif 430 {"arch", set_cpu_arch, 0}, 431 #ifndef I386COFF 432 {"bss", s_bss, 0}, 433 #endif 434 {"ffloat", float_cons, 'f'}, 435 {"dfloat", float_cons, 'd'}, 436 {"tfloat", float_cons, 'x'}, 437 {"value", cons, 2}, 438 {"noopt", s_ignore, 0}, 439 {"optim", s_ignore, 0}, 440 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, 441 {"code16", set_code_flag, CODE_16BIT}, 442 {"code32", set_code_flag, CODE_32BIT}, 443 {"code64", set_code_flag, CODE_64BIT}, 444 {"intel_syntax", set_intel_syntax, 1}, 445 {"att_syntax", set_intel_syntax, 0}, 446 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0}, 447 {"loc", dwarf2_directive_loc, 0}, 448 {0, 0, 0} 449 }; 450 451 /* For interface with expression (). */ 452 extern char *input_line_pointer; 453 454 /* Hash table for instruction mnemonic lookup. */ 455 static struct hash_control *op_hash; 456 457 /* Hash table for register lookup. */ 458 static struct hash_control *reg_hash; 459 460 void 461 i386_align_code (fragP, count) 462 fragS *fragP; 463 int count; 464 { 465 /* Various efficient no-op patterns for aligning code labels. 466 Note: Don't try to assemble the instructions in the comments. 467 0L and 0w are not legal. */ 468 static const char f32_1[] = 469 {0x90}; /* nop */ 470 static const char f32_2[] = 471 {0x89,0xf6}; /* movl %esi,%esi */ 472 static const char f32_3[] = 473 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ 474 static const char f32_4[] = 475 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 476 static const char f32_5[] = 477 {0x90, /* nop */ 478 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ 479 static const char f32_6[] = 480 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ 481 static const char f32_7[] = 482 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 483 static const char f32_8[] = 484 {0x90, /* nop */ 485 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ 486 static const char f32_9[] = 487 {0x89,0xf6, /* movl %esi,%esi */ 488 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 489 static const char f32_10[] = 490 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ 491 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 492 static const char f32_11[] = 493 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ 494 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 495 static const char f32_12[] = 496 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 497 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ 498 static const char f32_13[] = 499 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ 500 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 501 static const char f32_14[] = 502 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ 503 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ 504 static const char f32_15[] = 505 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ 506 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; 507 static const char f16_3[] = 508 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ 509 static const char f16_4[] = 510 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 511 static const char f16_5[] = 512 {0x90, /* nop */ 513 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ 514 static const char f16_6[] = 515 {0x89,0xf6, /* mov %si,%si */ 516 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 517 static const char f16_7[] = 518 {0x8d,0x74,0x00, /* lea 0(%si),%si */ 519 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 520 static const char f16_8[] = 521 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ 522 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ 523 static const char *const f32_patt[] = { 524 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, 525 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 526 }; 527 static const char *const f16_patt[] = { 528 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, 529 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 530 }; 531 532 if (count <= 0 || count > 15) 533 return; 534 535 /* The recommended way to pad 64bit code is to use NOPs preceded by 536 maximally four 0x66 prefixes. Balance the size of nops. */ 537 if (flag_code == CODE_64BIT) 538 { 539 int i; 540 int nnops = (count + 3) / 4; 541 int len = count / nnops; 542 int remains = count - nnops * len; 543 int pos = 0; 544 545 for (i = 0; i < remains; i++) 546 { 547 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len); 548 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90; 549 pos += len + 1; 550 } 551 for (; i < nnops; i++) 552 { 553 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1); 554 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90; 555 pos += len; 556 } 557 } 558 else 559 if (flag_code == CODE_16BIT) 560 { 561 memcpy (fragP->fr_literal + fragP->fr_fix, 562 f16_patt[count - 1], count); 563 if (count > 8) 564 /* Adjust jump offset. */ 565 fragP->fr_literal[fragP->fr_fix + 1] = count - 2; 566 } 567 else 568 memcpy (fragP->fr_literal + fragP->fr_fix, 569 f32_patt[count - 1], count); 570 fragP->fr_var = count; 571 } 572 573 static INLINE unsigned int 574 mode_from_disp_size (t) 575 unsigned int t; 576 { 577 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0; 578 } 579 580 static INLINE int 581 fits_in_signed_byte (num) 582 offsetT num; 583 { 584 return (num >= -128) && (num <= 127); 585 } 586 587 static INLINE int 588 fits_in_unsigned_byte (num) 589 offsetT num; 590 { 591 return (num & 0xff) == num; 592 } 593 594 static INLINE int 595 fits_in_unsigned_word (num) 596 offsetT num; 597 { 598 return (num & 0xffff) == num; 599 } 600 601 static INLINE int 602 fits_in_signed_word (num) 603 offsetT num; 604 { 605 return (-32768 <= num) && (num <= 32767); 606 } 607 static INLINE int 608 fits_in_signed_long (num) 609 offsetT num ATTRIBUTE_UNUSED; 610 { 611 #ifndef BFD64 612 return 1; 613 #else 614 return (!(((offsetT) -1 << 31) & num) 615 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); 616 #endif 617 } /* fits_in_signed_long() */ 618 static INLINE int 619 fits_in_unsigned_long (num) 620 offsetT num ATTRIBUTE_UNUSED; 621 { 622 #ifndef BFD64 623 return 1; 624 #else 625 return (num & (((offsetT) 2 << 31) - 1)) == num; 626 #endif 627 } /* fits_in_unsigned_long() */ 628 629 static int 630 smallest_imm_type (num) 631 offsetT num; 632 { 633 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)) 634 { 635 /* This code is disabled on the 486 because all the Imm1 forms 636 in the opcode table are slower on the i486. They're the 637 versions with the implicitly specified single-position 638 displacement, which has another syntax if you really want to 639 use that form. */ 640 if (num == 1) 641 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64; 642 } 643 return (fits_in_signed_byte (num) 644 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64) 645 : fits_in_unsigned_byte (num) 646 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64) 647 : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) 648 ? (Imm16 | Imm32 | Imm32S | Imm64) 649 : fits_in_signed_long (num) 650 ? (Imm32 | Imm32S | Imm64) 651 : fits_in_unsigned_long (num) 652 ? (Imm32 | Imm64) 653 : Imm64); 654 } 655 656 static offsetT 657 offset_in_range (val, size) 658 offsetT val; 659 int size; 660 { 661 addressT mask; 662 663 switch (size) 664 { 665 case 1: mask = ((addressT) 1 << 8) - 1; break; 666 case 2: mask = ((addressT) 1 << 16) - 1; break; 667 case 4: mask = ((addressT) 2 << 31) - 1; break; 668 #ifdef BFD64 669 case 8: mask = ((addressT) 2 << 63) - 1; break; 670 #endif 671 default: abort (); 672 } 673 674 /* If BFD64, sign extend val. */ 675 if (!use_rela_relocations) 676 if ((val & ~(((addressT) 2 << 31) - 1)) == 0) 677 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); 678 679 if ((val & ~mask) != 0 && (val & ~mask) != ~mask) 680 { 681 char buf1[40], buf2[40]; 682 683 sprint_value (buf1, val); 684 sprint_value (buf2, val & mask); 685 as_warn (_("%s shortened to %s"), buf1, buf2); 686 } 687 return val & mask; 688 } 689 690 /* Returns 0 if attempting to add a prefix where one from the same 691 class already exists, 1 if non rep/repne added, 2 if rep/repne 692 added. */ 693 static int 694 add_prefix (prefix) 695 unsigned int prefix; 696 { 697 int ret = 1; 698 int q; 699 700 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 701 && flag_code == CODE_64BIT) 702 q = REX_PREFIX; 703 else 704 switch (prefix) 705 { 706 default: 707 abort (); 708 709 case CS_PREFIX_OPCODE: 710 case DS_PREFIX_OPCODE: 711 case ES_PREFIX_OPCODE: 712 case FS_PREFIX_OPCODE: 713 case GS_PREFIX_OPCODE: 714 case SS_PREFIX_OPCODE: 715 q = SEG_PREFIX; 716 break; 717 718 case REPNE_PREFIX_OPCODE: 719 case REPE_PREFIX_OPCODE: 720 ret = 2; 721 /* fall thru */ 722 case LOCK_PREFIX_OPCODE: 723 q = LOCKREP_PREFIX; 724 break; 725 726 case FWAIT_OPCODE: 727 q = WAIT_PREFIX; 728 break; 729 730 case ADDR_PREFIX_OPCODE: 731 q = ADDR_PREFIX; 732 break; 733 734 case DATA_PREFIX_OPCODE: 735 q = DATA_PREFIX; 736 break; 737 } 738 739 if (i.prefix[q] != 0) 740 { 741 as_bad (_("same type of prefix used twice")); 742 return 0; 743 } 744 745 i.prefixes += 1; 746 i.prefix[q] = prefix; 747 return ret; 748 } 749 750 static void 751 set_code_flag (value) 752 int value; 753 { 754 flag_code = value; 755 cpu_arch_flags &= ~(Cpu64 | CpuNo64); 756 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); 757 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer)) 758 { 759 as_bad (_("64bit mode not supported on this CPU.")); 760 } 761 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386)) 762 { 763 as_bad (_("32bit mode not supported on this CPU.")); 764 } 765 stackop_size = '\0'; 766 } 767 768 static void 769 set_16bit_gcc_code_flag (new_code_flag) 770 int new_code_flag; 771 { 772 flag_code = new_code_flag; 773 cpu_arch_flags &= ~(Cpu64 | CpuNo64); 774 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); 775 stackop_size = 'l'; 776 } 777 778 static void 779 set_intel_syntax (syntax_flag) 780 int syntax_flag; 781 { 782 /* Find out if register prefixing is specified. */ 783 int ask_naked_reg = 0; 784 785 SKIP_WHITESPACE (); 786 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 787 { 788 char *string = input_line_pointer; 789 int e = get_symbol_end (); 790 791 if (strcmp (string, "prefix") == 0) 792 ask_naked_reg = 1; 793 else if (strcmp (string, "noprefix") == 0) 794 ask_naked_reg = -1; 795 else 796 as_bad (_("bad argument to syntax directive.")); 797 *input_line_pointer = e; 798 } 799 demand_empty_rest_of_line (); 800 801 intel_syntax = syntax_flag; 802 803 if (ask_naked_reg == 0) 804 allow_naked_reg = (intel_syntax 805 && (bfd_get_symbol_leading_char (stdoutput) != '\0')); 806 else 807 allow_naked_reg = (ask_naked_reg < 0); 808 } 809 810 static void 811 set_cpu_arch (dummy) 812 int dummy ATTRIBUTE_UNUSED; 813 { 814 SKIP_WHITESPACE (); 815 816 if (!is_end_of_line[(unsigned char) *input_line_pointer]) 817 { 818 char *string = input_line_pointer; 819 int e = get_symbol_end (); 820 int i; 821 822 for (i = 0; cpu_arch[i].name; i++) 823 { 824 if (strcmp (string, cpu_arch[i].name) == 0) 825 { 826 cpu_arch_name = cpu_arch[i].name; 827 cpu_arch_flags = (cpu_arch[i].flags 828 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64)); 829 break; 830 } 831 } 832 if (!cpu_arch[i].name) 833 as_bad (_("no such architecture: `%s'"), string); 834 835 *input_line_pointer = e; 836 } 837 else 838 as_bad (_("missing cpu architecture")); 839 840 no_cond_jump_promotion = 0; 841 if (*input_line_pointer == ',' 842 && !is_end_of_line[(unsigned char) input_line_pointer[1]]) 843 { 844 char *string = ++input_line_pointer; 845 int e = get_symbol_end (); 846 847 if (strcmp (string, "nojumps") == 0) 848 no_cond_jump_promotion = 1; 849 else if (strcmp (string, "jumps") == 0) 850 ; 851 else 852 as_bad (_("no such architecture modifier: `%s'"), string); 853 854 *input_line_pointer = e; 855 } 856 857 demand_empty_rest_of_line (); 858 } 859 860 unsigned long 861 i386_mach () 862 { 863 if (!strcmp (default_arch, "x86_64")) 864 return bfd_mach_x86_64; 865 else if (!strcmp (default_arch, "i386")) 866 return bfd_mach_i386_i386; 867 else 868 as_fatal (_("Unknown architecture")); 869 } 870 871 void 872 md_begin () 873 { 874 const char *hash_err; 875 876 /* Initialize op_hash hash table. */ 877 op_hash = hash_new (); 878 879 { 880 const template *optab; 881 templates *core_optab; 882 883 /* Setup for loop. */ 884 optab = i386_optab; 885 core_optab = (templates *) xmalloc (sizeof (templates)); 886 core_optab->start = optab; 887 888 while (1) 889 { 890 ++optab; 891 if (optab->name == NULL 892 || strcmp (optab->name, (optab - 1)->name) != 0) 893 { 894 /* different name --> ship out current template list; 895 add to hash table; & begin anew. */ 896 core_optab->end = optab; 897 hash_err = hash_insert (op_hash, 898 (optab - 1)->name, 899 (PTR) core_optab); 900 if (hash_err) 901 { 902 as_fatal (_("Internal Error: Can't hash %s: %s"), 903 (optab - 1)->name, 904 hash_err); 905 } 906 if (optab->name == NULL) 907 break; 908 core_optab = (templates *) xmalloc (sizeof (templates)); 909 core_optab->start = optab; 910 } 911 } 912 } 913 914 /* Initialize reg_hash hash table. */ 915 reg_hash = hash_new (); 916 { 917 const reg_entry *regtab; 918 919 for (regtab = i386_regtab; 920 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); 921 regtab++) 922 { 923 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); 924 if (hash_err) 925 as_fatal (_("Internal Error: Can't hash %s: %s"), 926 regtab->reg_name, 927 hash_err); 928 } 929 } 930 931 /* Fill in lexical tables: mnemonic_chars, operand_chars. */ 932 { 933 int c; 934 char *p; 935 936 for (c = 0; c < 256; c++) 937 { 938 if (ISDIGIT (c)) 939 { 940 digit_chars[c] = c; 941 mnemonic_chars[c] = c; 942 register_chars[c] = c; 943 operand_chars[c] = c; 944 } 945 else if (ISLOWER (c)) 946 { 947 mnemonic_chars[c] = c; 948 register_chars[c] = c; 949 operand_chars[c] = c; 950 } 951 else if (ISUPPER (c)) 952 { 953 mnemonic_chars[c] = TOLOWER (c); 954 register_chars[c] = mnemonic_chars[c]; 955 operand_chars[c] = c; 956 } 957 958 if (ISALPHA (c) || ISDIGIT (c)) 959 identifier_chars[c] = c; 960 else if (c >= 128) 961 { 962 identifier_chars[c] = c; 963 operand_chars[c] = c; 964 } 965 } 966 967 #ifdef LEX_AT 968 identifier_chars['@'] = '@'; 969 #endif 970 digit_chars['-'] = '-'; 971 mnemonic_chars['-'] = '-'; 972 identifier_chars['_'] = '_'; 973 identifier_chars['.'] = '.'; 974 975 for (p = operand_special_chars; *p != '\0'; p++) 976 operand_chars[(unsigned char) *p] = *p; 977 } 978 979 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 980 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 981 { 982 record_alignment (text_section, 2); 983 record_alignment (data_section, 2); 984 record_alignment (bss_section, 2); 985 } 986 #endif 987 988 if (flag_code == CODE_64BIT) 989 { 990 x86_dwarf2_return_column = 16; 991 x86_cie_data_alignment = -8; 992 } 993 else 994 { 995 x86_dwarf2_return_column = 8; 996 x86_cie_data_alignment = -4; 997 } 998 } 999 1000 void 1001 i386_print_statistics (file) 1002 FILE *file; 1003 { 1004 hash_print_statistics (file, "i386 opcode", op_hash); 1005 hash_print_statistics (file, "i386 register", reg_hash); 1006 } 1007 1008 #ifdef DEBUG386 1009 1010 /* Debugging routines for md_assemble. */ 1011 static void pi PARAMS ((char *, i386_insn *)); 1012 static void pte PARAMS ((template *)); 1013 static void pt PARAMS ((unsigned int)); 1014 static void pe PARAMS ((expressionS *)); 1015 static void ps PARAMS ((symbolS *)); 1016 1017 static void 1018 pi (line, x) 1019 char *line; 1020 i386_insn *x; 1021 { 1022 unsigned int i; 1023 1024 fprintf (stdout, "%s: template ", line); 1025 pte (&x->tm); 1026 fprintf (stdout, " address: base %s index %s scale %x\n", 1027 x->base_reg ? x->base_reg->reg_name : "none", 1028 x->index_reg ? x->index_reg->reg_name : "none", 1029 x->log2_scale_factor); 1030 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", 1031 x->rm.mode, x->rm.reg, x->rm.regmem); 1032 fprintf (stdout, " sib: base %x index %x scale %x\n", 1033 x->sib.base, x->sib.index, x->sib.scale); 1034 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", 1035 (x->rex & REX_MODE64) != 0, 1036 (x->rex & REX_EXTX) != 0, 1037 (x->rex & REX_EXTY) != 0, 1038 (x->rex & REX_EXTZ) != 0); 1039 for (i = 0; i < x->operands; i++) 1040 { 1041 fprintf (stdout, " #%d: ", i + 1); 1042 pt (x->types[i]); 1043 fprintf (stdout, "\n"); 1044 if (x->types[i] 1045 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) 1046 fprintf (stdout, "%s\n", x->op[i].regs->reg_name); 1047 if (x->types[i] & Imm) 1048 pe (x->op[i].imms); 1049 if (x->types[i] & Disp) 1050 pe (x->op[i].disps); 1051 } 1052 } 1053 1054 static void 1055 pte (t) 1056 template *t; 1057 { 1058 unsigned int i; 1059 fprintf (stdout, " %d operands ", t->operands); 1060 fprintf (stdout, "opcode %x ", t->base_opcode); 1061 if (t->extension_opcode != None) 1062 fprintf (stdout, "ext %x ", t->extension_opcode); 1063 if (t->opcode_modifier & D) 1064 fprintf (stdout, "D"); 1065 if (t->opcode_modifier & W) 1066 fprintf (stdout, "W"); 1067 fprintf (stdout, "\n"); 1068 for (i = 0; i < t->operands; i++) 1069 { 1070 fprintf (stdout, " #%d type ", i + 1); 1071 pt (t->operand_types[i]); 1072 fprintf (stdout, "\n"); 1073 } 1074 } 1075 1076 static void 1077 pe (e) 1078 expressionS *e; 1079 { 1080 fprintf (stdout, " operation %d\n", e->X_op); 1081 fprintf (stdout, " add_number %ld (%lx)\n", 1082 (long) e->X_add_number, (long) e->X_add_number); 1083 if (e->X_add_symbol) 1084 { 1085 fprintf (stdout, " add_symbol "); 1086 ps (e->X_add_symbol); 1087 fprintf (stdout, "\n"); 1088 } 1089 if (e->X_op_symbol) 1090 { 1091 fprintf (stdout, " op_symbol "); 1092 ps (e->X_op_symbol); 1093 fprintf (stdout, "\n"); 1094 } 1095 } 1096 1097 static void 1098 ps (s) 1099 symbolS *s; 1100 { 1101 fprintf (stdout, "%s type %s%s", 1102 S_GET_NAME (s), 1103 S_IS_EXTERNAL (s) ? "EXTERNAL " : "", 1104 segment_name (S_GET_SEGMENT (s))); 1105 } 1106 1107 struct type_name 1108 { 1109 unsigned int mask; 1110 char *tname; 1111 } 1112 1113 static const type_names[] = 1114 { 1115 { Reg8, "r8" }, 1116 { Reg16, "r16" }, 1117 { Reg32, "r32" }, 1118 { Reg64, "r64" }, 1119 { Imm8, "i8" }, 1120 { Imm8S, "i8s" }, 1121 { Imm16, "i16" }, 1122 { Imm32, "i32" }, 1123 { Imm32S, "i32s" }, 1124 { Imm64, "i64" }, 1125 { Imm1, "i1" }, 1126 { BaseIndex, "BaseIndex" }, 1127 { Disp8, "d8" }, 1128 { Disp16, "d16" }, 1129 { Disp32, "d32" }, 1130 { Disp32S, "d32s" }, 1131 { Disp64, "d64" }, 1132 { InOutPortReg, "InOutPortReg" }, 1133 { ShiftCount, "ShiftCount" }, 1134 { Control, "control reg" }, 1135 { Test, "test reg" }, 1136 { Debug, "debug reg" }, 1137 { FloatReg, "FReg" }, 1138 { FloatAcc, "FAcc" }, 1139 { SReg2, "SReg2" }, 1140 { SReg3, "SReg3" }, 1141 { Acc, "Acc" }, 1142 { JumpAbsolute, "Jump Absolute" }, 1143 { RegMMX, "rMMX" }, 1144 { RegXMM, "rXMM" }, 1145 { EsSeg, "es" }, 1146 { 0, "" } 1147 }; 1148 1149 static void 1150 pt (t) 1151 unsigned int t; 1152 { 1153 const struct type_name *ty; 1154 1155 for (ty = type_names; ty->mask; ty++) 1156 if (t & ty->mask) 1157 fprintf (stdout, "%s, ", ty->tname); 1158 fflush (stdout); 1159 } 1160 1161 #endif /* DEBUG386 */ 1162 1163 static bfd_reloc_code_real_type reloc 1164 PARAMS ((int, int, int, bfd_reloc_code_real_type)); 1165 1166 static bfd_reloc_code_real_type 1167 reloc (size, pcrel, sign, other) 1168 int size; 1169 int pcrel; 1170 int sign; 1171 bfd_reloc_code_real_type other; 1172 { 1173 if (other != NO_RELOC) 1174 return other; 1175 1176 if (pcrel) 1177 { 1178 if (!sign) 1179 as_bad (_("There are no unsigned pc-relative relocations")); 1180 switch (size) 1181 { 1182 case 1: return BFD_RELOC_8_PCREL; 1183 case 2: return BFD_RELOC_16_PCREL; 1184 case 4: return BFD_RELOC_32_PCREL; 1185 } 1186 as_bad (_("can not do %d byte pc-relative relocation"), size); 1187 } 1188 else 1189 { 1190 if (sign) 1191 switch (size) 1192 { 1193 case 4: return BFD_RELOC_X86_64_32S; 1194 } 1195 else 1196 switch (size) 1197 { 1198 case 1: return BFD_RELOC_8; 1199 case 2: return BFD_RELOC_16; 1200 case 4: return BFD_RELOC_32; 1201 case 8: return BFD_RELOC_64; 1202 } 1203 as_bad (_("can not do %s %d byte relocation"), 1204 sign ? "signed" : "unsigned", size); 1205 } 1206 1207 abort (); 1208 return BFD_RELOC_NONE; 1209 } 1210 1211 /* Here we decide which fixups can be adjusted to make them relative to 1212 the beginning of the section instead of the symbol. Basically we need 1213 to make sure that the dynamic relocations are done correctly, so in 1214 some cases we force the original symbol to be used. */ 1215 1216 int 1217 tc_i386_fix_adjustable (fixP) 1218 fixS *fixP ATTRIBUTE_UNUSED; 1219 { 1220 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 1221 if (OUTPUT_FLAVOR != bfd_target_elf_flavour) 1222 return 1; 1223 1224 /* Don't adjust pc-relative references to merge sections in 64-bit 1225 mode. */ 1226 if (use_rela_relocations 1227 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 1228 && fixP->fx_pcrel) 1229 return 0; 1230 1231 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations 1232 and changed later by validate_fix. */ 1233 if (GOT_symbol && fixP->fx_subsy == GOT_symbol 1234 && fixP->fx_r_type == BFD_RELOC_32_PCREL) 1235 return 0; 1236 1237 /* adjust_reloc_syms doesn't know about the GOT. */ 1238 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF 1239 || fixP->fx_r_type == BFD_RELOC_386_PLT32 1240 || fixP->fx_r_type == BFD_RELOC_386_GOT32 1241 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD 1242 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM 1243 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 1244 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 1245 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE 1246 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE 1247 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 1248 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE 1249 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 1250 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 1251 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL 1252 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD 1253 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD 1254 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 1255 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF 1256 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 1257 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 1258 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 1259 return 0; 1260 #endif 1261 return 1; 1262 } 1263 1264 static int intel_float_operand PARAMS ((const char *mnemonic)); 1265 1266 static int 1267 intel_float_operand (mnemonic) 1268 const char *mnemonic; 1269 { 1270 if (mnemonic[0] == 'f' && mnemonic[1] == 'i') 1271 return 2; 1272 1273 if (mnemonic[0] == 'f') 1274 return 1; 1275 1276 return 0; 1277 } 1278 1279 /* This is the guts of the machine-dependent assembler. LINE points to a 1280 machine dependent instruction. This function is supposed to emit 1281 the frags/bytes it assembles to. */ 1282 1283 void 1284 md_assemble (line) 1285 char *line; 1286 { 1287 int j; 1288 char mnemonic[MAX_MNEM_SIZE]; 1289 1290 /* Initialize globals. */ 1291 memset (&i, '\0', sizeof (i)); 1292 for (j = 0; j < MAX_OPERANDS; j++) 1293 i.reloc[j] = NO_RELOC; 1294 memset (disp_expressions, '\0', sizeof (disp_expressions)); 1295 memset (im_expressions, '\0', sizeof (im_expressions)); 1296 save_stack_p = save_stack; 1297 1298 /* First parse an instruction mnemonic & call i386_operand for the operands. 1299 We assume that the scrubber has arranged it so that line[0] is the valid 1300 start of a (possibly prefixed) mnemonic. */ 1301 1302 line = parse_insn (line, mnemonic); 1303 if (line == NULL) 1304 return; 1305 1306 line = parse_operands (line, mnemonic); 1307 if (line == NULL) 1308 return; 1309 1310 /* Now we've parsed the mnemonic into a set of templates, and have the 1311 operands at hand. */ 1312 1313 /* All intel opcodes have reversed operands except for "bound" and 1314 "enter". We also don't reverse intersegment "jmp" and "call" 1315 instructions with 2 immediate operands so that the immediate segment 1316 precedes the offset, as it does when in AT&T mode. "enter" and the 1317 intersegment "jmp" and "call" instructions are the only ones that 1318 have two immediate operands. */ 1319 if (intel_syntax && i.operands > 1 1320 && (strcmp (mnemonic, "bound") != 0) 1321 && (strcmp (mnemonic, "invlpga") != 0) 1322 && !((i.types[0] & Imm) && (i.types[1] & Imm))) 1323 swap_operands (); 1324 1325 if (i.imm_operands) 1326 optimize_imm (); 1327 1328 if (i.disp_operands) 1329 optimize_disp (); 1330 1331 /* Next, we find a template that matches the given insn, 1332 making sure the overlap of the given operands types is consistent 1333 with the template operand types. */ 1334 1335 if (!match_template ()) 1336 return; 1337 1338 if (intel_syntax) 1339 { 1340 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ 1341 if (SYSV386_COMPAT 1342 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) 1343 i.tm.base_opcode ^= FloatR; 1344 1345 /* Zap movzx and movsx suffix. The suffix may have been set from 1346 "word ptr" or "byte ptr" on the source operand, but we'll use 1347 the suffix later to choose the destination register. */ 1348 if ((i.tm.base_opcode & ~9) == 0x0fb6) 1349 i.suffix = 0; 1350 } 1351 1352 if (i.tm.opcode_modifier & FWait) 1353 if (!add_prefix (FWAIT_OPCODE)) 1354 return; 1355 1356 /* Check string instruction segment overrides. */ 1357 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) 1358 { 1359 if (!check_string ()) 1360 return; 1361 } 1362 1363 if (!process_suffix ()) 1364 return; 1365 1366 /* Make still unresolved immediate matches conform to size of immediate 1367 given in i.suffix. */ 1368 if (!finalize_imm ()) 1369 return; 1370 1371 if (i.types[0] & Imm1) 1372 i.imm_operands = 0; /* kludge for shift insns. */ 1373 if (i.types[0] & ImplicitRegister) 1374 i.reg_operands--; 1375 if (i.types[1] & ImplicitRegister) 1376 i.reg_operands--; 1377 if (i.types[2] & ImplicitRegister) 1378 i.reg_operands--; 1379 1380 if (i.tm.opcode_modifier & ImmExt) 1381 { 1382 expressionS *exp; 1383 1384 if ((i.tm.cpu_flags & (CpuPNI|CpuXSAVE|CpuSMAP)) && i.operands > 0) 1385 { 1386 /* These Intel Prescott New Instructions have the fixed 1387 operands with an opcode suffix which is coded in the same 1388 place as an 8-bit immediate field would be. Here we check 1389 those operands and remove them afterwards. */ 1390 unsigned int x; 1391 1392 for (x = 0; x < i.operands; x++) 1393 if (i.op[x].regs->reg_num != x) 1394 as_bad (_("can't use register '%%%s' as operand %d in '%s'."), 1395 i.op[x].regs->reg_name, x + 1, i.tm.name); 1396 i.operands = 0; 1397 } 1398 1399 /* These AMD 3DNow! and Intel Katmai New Instructions have an 1400 opcode suffix which is coded in the same place as an 8-bit 1401 immediate field would be. Here we fake an 8-bit immediate 1402 operand from the opcode suffix stored in tm.extension_opcode. */ 1403 1404 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); 1405 1406 exp = &im_expressions[i.imm_operands++]; 1407 i.op[i.operands].imms = exp; 1408 i.types[i.operands++] = Imm8; 1409 exp->X_op = O_constant; 1410 exp->X_add_number = i.tm.extension_opcode; 1411 i.tm.extension_opcode = None; 1412 } 1413 1414 /* For insns with operands there are more diddles to do to the opcode. */ 1415 if (i.operands) 1416 { 1417 if (!process_operands ()) 1418 return; 1419 } 1420 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) 1421 { 1422 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ 1423 as_warn (_("translating to `%sp'"), i.tm.name); 1424 } 1425 1426 /* Handle conversion of 'int $3' --> special int3 insn. */ 1427 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) 1428 { 1429 i.tm.base_opcode = INT3_OPCODE; 1430 i.imm_operands = 0; 1431 } 1432 1433 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) 1434 && i.op[0].disps->X_op == O_constant) 1435 { 1436 /* Convert "jmp constant" (and "call constant") to a jump (call) to 1437 the absolute address given by the constant. Since ix86 jumps and 1438 calls are pc relative, we need to generate a reloc. */ 1439 i.op[0].disps->X_add_symbol = &abs_symbol; 1440 i.op[0].disps->X_op = O_symbol; 1441 } 1442 1443 if ((i.tm.opcode_modifier & Rex64) != 0) 1444 i.rex |= REX_MODE64; 1445 1446 /* For 8 bit registers we need an empty rex prefix. Also if the 1447 instruction already has a prefix, we need to convert old 1448 registers to new ones. */ 1449 1450 if (((i.types[0] & Reg8) != 0 1451 && (i.op[0].regs->reg_flags & RegRex64) != 0) 1452 || ((i.types[1] & Reg8) != 0 1453 && (i.op[1].regs->reg_flags & RegRex64) != 0) 1454 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0) 1455 && i.rex != 0)) 1456 { 1457 int x; 1458 1459 i.rex |= REX_OPCODE; 1460 for (x = 0; x < 2; x++) 1461 { 1462 /* Look for 8 bit operand that uses old registers. */ 1463 if ((i.types[x] & Reg8) != 0 1464 && (i.op[x].regs->reg_flags & RegRex64) == 0) 1465 { 1466 /* In case it is "hi" register, give up. */ 1467 if (i.op[x].regs->reg_num > 3) 1468 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"), 1469 i.op[x].regs->reg_name); 1470 1471 /* Otherwise it is equivalent to the extended register. 1472 Since the encoding doesn't change this is merely 1473 cosmetic cleanup for debug output. */ 1474 1475 i.op[x].regs = i.op[x].regs + 8; 1476 } 1477 } 1478 } 1479 1480 if (i.rex != 0) 1481 add_prefix (REX_OPCODE | i.rex); 1482 1483 /* We are ready to output the insn. */ 1484 output_insn (); 1485 } 1486 1487 static char * 1488 parse_insn (line, mnemonic) 1489 char *line; 1490 char *mnemonic; 1491 { 1492 char *l = line; 1493 char *token_start = l; 1494 char *mnem_p; 1495 1496 /* Non-zero if we found a prefix only acceptable with string insns. */ 1497 const char *expecting_string_instruction = NULL; 1498 1499 while (1) 1500 { 1501 mnem_p = mnemonic; 1502 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) 1503 { 1504 mnem_p++; 1505 if (mnem_p >= mnemonic + MAX_MNEM_SIZE) 1506 { 1507 as_bad (_("no such instruction: `%s'"), token_start); 1508 return NULL; 1509 } 1510 l++; 1511 } 1512 if (!is_space_char (*l) 1513 && *l != END_OF_INSN 1514 && *l != PREFIX_SEPARATOR 1515 && *l != ',') 1516 { 1517 as_bad (_("invalid character %s in mnemonic"), 1518 output_invalid (*l)); 1519 return NULL; 1520 } 1521 if (token_start == l) 1522 { 1523 if (*l == PREFIX_SEPARATOR) 1524 as_bad (_("expecting prefix; got nothing")); 1525 else 1526 as_bad (_("expecting mnemonic; got nothing")); 1527 return NULL; 1528 } 1529 1530 /* Look up instruction (or prefix) via hash table. */ 1531 current_templates = hash_find (op_hash, mnemonic); 1532 1533 if (*l != END_OF_INSN 1534 && (!is_space_char (*l) || l[1] != END_OF_INSN) 1535 && current_templates 1536 && (current_templates->start->opcode_modifier & IsPrefix)) 1537 { 1538 /* If we are in 16-bit mode, do not allow addr16 or data16. 1539 Similarly, in 32-bit mode, do not allow addr32 or data32. */ 1540 if ((current_templates->start->opcode_modifier & (Size16 | Size32)) 1541 && flag_code != CODE_64BIT 1542 && (((current_templates->start->opcode_modifier & Size32) != 0) 1543 ^ (flag_code == CODE_16BIT))) 1544 { 1545 as_bad (_("redundant %s prefix"), 1546 current_templates->start->name); 1547 return NULL; 1548 } 1549 /* Add prefix, checking for repeated prefixes. */ 1550 switch (add_prefix (current_templates->start->base_opcode)) 1551 { 1552 case 0: 1553 return NULL; 1554 case 2: 1555 expecting_string_instruction = current_templates->start->name; 1556 break; 1557 } 1558 /* Skip past PREFIX_SEPARATOR and reset token_start. */ 1559 token_start = ++l; 1560 } 1561 else 1562 break; 1563 } 1564 1565 if (!current_templates) 1566 { 1567 /* See if we can get a match by trimming off a suffix. */ 1568 switch (mnem_p[-1]) 1569 { 1570 case WORD_MNEM_SUFFIX: 1571 case BYTE_MNEM_SUFFIX: 1572 case QWORD_MNEM_SUFFIX: 1573 i.suffix = mnem_p[-1]; 1574 mnem_p[-1] = '\0'; 1575 current_templates = hash_find (op_hash, mnemonic); 1576 break; 1577 case SHORT_MNEM_SUFFIX: 1578 case LONG_MNEM_SUFFIX: 1579 if (!intel_syntax) 1580 { 1581 i.suffix = mnem_p[-1]; 1582 mnem_p[-1] = '\0'; 1583 current_templates = hash_find (op_hash, mnemonic); 1584 } 1585 break; 1586 1587 /* Intel Syntax. */ 1588 case 'd': 1589 if (intel_syntax) 1590 { 1591 if (intel_float_operand (mnemonic)) 1592 i.suffix = SHORT_MNEM_SUFFIX; 1593 else 1594 i.suffix = LONG_MNEM_SUFFIX; 1595 mnem_p[-1] = '\0'; 1596 current_templates = hash_find (op_hash, mnemonic); 1597 } 1598 break; 1599 } 1600 if (!current_templates) 1601 { 1602 as_bad (_("no such instruction: `%s'"), token_start); 1603 return NULL; 1604 } 1605 } 1606 1607 if (current_templates->start->opcode_modifier & (Jump | JumpByte)) 1608 { 1609 /* Check for a branch hint. We allow ",pt" and ",pn" for 1610 predict taken and predict not taken respectively. 1611 I'm not sure that branch hints actually do anything on loop 1612 and jcxz insns (JumpByte) for current Pentium4 chips. They 1613 may work in the future and it doesn't hurt to accept them 1614 now. */ 1615 if (l[0] == ',' && l[1] == 'p') 1616 { 1617 if (l[2] == 't') 1618 { 1619 if (!add_prefix (DS_PREFIX_OPCODE)) 1620 return NULL; 1621 l += 3; 1622 } 1623 else if (l[2] == 'n') 1624 { 1625 if (!add_prefix (CS_PREFIX_OPCODE)) 1626 return NULL; 1627 l += 3; 1628 } 1629 } 1630 } 1631 /* Any other comma loses. */ 1632 if (*l == ',') 1633 { 1634 as_bad (_("invalid character %s in mnemonic"), 1635 output_invalid (*l)); 1636 return NULL; 1637 } 1638 1639 /* Check if instruction is supported on specified architecture. */ 1640 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64)) 1641 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))) 1642 { 1643 as_warn (_("`%s' is not supported on `%s'"), 1644 current_templates->start->name, cpu_arch_name); 1645 } 1646 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT)) 1647 { 1648 as_warn (_("use .code16 to ensure correct addressing mode")); 1649 } 1650 1651 /* Check for rep/repne without a string instruction. */ 1652 if (expecting_string_instruction 1653 && !(current_templates->start->opcode_modifier & IsString)) 1654 { 1655 as_bad (_("expecting string instruction after `%s'"), 1656 expecting_string_instruction); 1657 return NULL; 1658 } 1659 1660 return l; 1661 } 1662 1663 static char * 1664 parse_operands (l, mnemonic) 1665 char *l; 1666 const char *mnemonic; 1667 { 1668 char *token_start; 1669 1670 /* 1 if operand is pending after ','. */ 1671 unsigned int expecting_operand = 0; 1672 1673 /* Non-zero if operand parens not balanced. */ 1674 unsigned int paren_not_balanced; 1675 1676 while (*l != END_OF_INSN) 1677 { 1678 /* Skip optional white space before operand. */ 1679 if (is_space_char (*l)) 1680 ++l; 1681 if (!is_operand_char (*l) && *l != END_OF_INSN) 1682 { 1683 as_bad (_("invalid character %s before operand %d"), 1684 output_invalid (*l), 1685 i.operands + 1); 1686 return NULL; 1687 } 1688 token_start = l; /* after white space */ 1689 paren_not_balanced = 0; 1690 while (paren_not_balanced || *l != ',') 1691 { 1692 if (*l == END_OF_INSN) 1693 { 1694 if (paren_not_balanced) 1695 { 1696 if (!intel_syntax) 1697 as_bad (_("unbalanced parenthesis in operand %d."), 1698 i.operands + 1); 1699 else 1700 as_bad (_("unbalanced brackets in operand %d."), 1701 i.operands + 1); 1702 return NULL; 1703 } 1704 else 1705 break; /* we are done */ 1706 } 1707 else if (!is_operand_char (*l) && !is_space_char (*l)) 1708 { 1709 as_bad (_("invalid character %s in operand %d"), 1710 output_invalid (*l), 1711 i.operands + 1); 1712 return NULL; 1713 } 1714 if (!intel_syntax) 1715 { 1716 if (*l == '(') 1717 ++paren_not_balanced; 1718 if (*l == ')') 1719 --paren_not_balanced; 1720 } 1721 else 1722 { 1723 if (*l == '[') 1724 ++paren_not_balanced; 1725 if (*l == ']') 1726 --paren_not_balanced; 1727 } 1728 l++; 1729 } 1730 if (l != token_start) 1731 { /* Yes, we've read in another operand. */ 1732 unsigned int operand_ok; 1733 this_operand = i.operands++; 1734 if (i.operands > MAX_OPERANDS) 1735 { 1736 as_bad (_("spurious operands; (%d operands/instruction max)"), 1737 MAX_OPERANDS); 1738 return NULL; 1739 } 1740 /* Now parse operand adding info to 'i' as we go along. */ 1741 END_STRING_AND_SAVE (l); 1742 1743 if (intel_syntax) 1744 operand_ok = 1745 i386_intel_operand (token_start, 1746 intel_float_operand (mnemonic)); 1747 else 1748 operand_ok = i386_operand (token_start); 1749 1750 RESTORE_END_STRING (l); 1751 if (!operand_ok) 1752 return NULL; 1753 } 1754 else 1755 { 1756 if (expecting_operand) 1757 { 1758 expecting_operand_after_comma: 1759 as_bad (_("expecting operand after ','; got nothing")); 1760 return NULL; 1761 } 1762 if (*l == ',') 1763 { 1764 as_bad (_("expecting operand before ','; got nothing")); 1765 return NULL; 1766 } 1767 } 1768 1769 /* Now *l must be either ',' or END_OF_INSN. */ 1770 if (*l == ',') 1771 { 1772 if (*++l == END_OF_INSN) 1773 { 1774 /* Just skip it, if it's \n complain. */ 1775 goto expecting_operand_after_comma; 1776 } 1777 expecting_operand = 1; 1778 } 1779 } 1780 return l; 1781 } 1782 1783 static void 1784 swap_operands () 1785 { 1786 union i386_op temp_op; 1787 unsigned int temp_type; 1788 enum bfd_reloc_code_real temp_reloc; 1789 int xchg1 = 0; 1790 int xchg2 = 0; 1791 1792 if (i.operands == 2) 1793 { 1794 xchg1 = 0; 1795 xchg2 = 1; 1796 } 1797 else if (i.operands == 3) 1798 { 1799 xchg1 = 0; 1800 xchg2 = 2; 1801 } 1802 temp_type = i.types[xchg2]; 1803 i.types[xchg2] = i.types[xchg1]; 1804 i.types[xchg1] = temp_type; 1805 temp_op = i.op[xchg2]; 1806 i.op[xchg2] = i.op[xchg1]; 1807 i.op[xchg1] = temp_op; 1808 temp_reloc = i.reloc[xchg2]; 1809 i.reloc[xchg2] = i.reloc[xchg1]; 1810 i.reloc[xchg1] = temp_reloc; 1811 1812 if (i.mem_operands == 2) 1813 { 1814 const seg_entry *temp_seg; 1815 temp_seg = i.seg[0]; 1816 i.seg[0] = i.seg[1]; 1817 i.seg[1] = temp_seg; 1818 } 1819 } 1820 1821 /* Try to ensure constant immediates are represented in the smallest 1822 opcode possible. */ 1823 static void 1824 optimize_imm () 1825 { 1826 char guess_suffix = 0; 1827 int op; 1828 1829 if (i.suffix) 1830 guess_suffix = i.suffix; 1831 else if (i.reg_operands) 1832 { 1833 /* Figure out a suffix from the last register operand specified. 1834 We can't do this properly yet, ie. excluding InOutPortReg, 1835 but the following works for instructions with immediates. 1836 In any case, we can't set i.suffix yet. */ 1837 for (op = i.operands; --op >= 0;) 1838 if (i.types[op] & Reg) 1839 { 1840 if (i.types[op] & Reg8) 1841 guess_suffix = BYTE_MNEM_SUFFIX; 1842 else if (i.types[op] & Reg16) 1843 guess_suffix = WORD_MNEM_SUFFIX; 1844 else if (i.types[op] & Reg32) 1845 guess_suffix = LONG_MNEM_SUFFIX; 1846 else if (i.types[op] & Reg64) 1847 guess_suffix = QWORD_MNEM_SUFFIX; 1848 break; 1849 } 1850 } 1851 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) 1852 guess_suffix = WORD_MNEM_SUFFIX; 1853 1854 for (op = i.operands; --op >= 0;) 1855 if (i.types[op] & Imm) 1856 { 1857 switch (i.op[op].imms->X_op) 1858 { 1859 case O_constant: 1860 /* If a suffix is given, this operand may be shortened. */ 1861 switch (guess_suffix) 1862 { 1863 case LONG_MNEM_SUFFIX: 1864 i.types[op] |= Imm32 | Imm64; 1865 break; 1866 case WORD_MNEM_SUFFIX: 1867 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64; 1868 break; 1869 case BYTE_MNEM_SUFFIX: 1870 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64; 1871 break; 1872 } 1873 1874 /* If this operand is at most 16 bits, convert it 1875 to a signed 16 bit number before trying to see 1876 whether it will fit in an even smaller size. 1877 This allows a 16-bit operand such as $0xffe0 to 1878 be recognised as within Imm8S range. */ 1879 if ((i.types[op] & Imm16) 1880 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) 1881 { 1882 i.op[op].imms->X_add_number = 1883 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); 1884 } 1885 if ((i.types[op] & Imm32) 1886 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) 1887 == 0)) 1888 { 1889 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number 1890 ^ ((offsetT) 1 << 31)) 1891 - ((offsetT) 1 << 31)); 1892 } 1893 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number); 1894 1895 /* We must avoid matching of Imm32 templates when 64bit 1896 only immediate is available. */ 1897 if (guess_suffix == QWORD_MNEM_SUFFIX) 1898 i.types[op] &= ~Imm32; 1899 break; 1900 1901 case O_absent: 1902 case O_register: 1903 abort (); 1904 1905 /* Symbols and expressions. */ 1906 default: 1907 /* Convert symbolic operand to proper sizes for matching. */ 1908 switch (guess_suffix) 1909 { 1910 case QWORD_MNEM_SUFFIX: 1911 i.types[op] = Imm64 | Imm32S; 1912 break; 1913 case LONG_MNEM_SUFFIX: 1914 i.types[op] = Imm32; 1915 break; 1916 case WORD_MNEM_SUFFIX: 1917 i.types[op] = Imm16; 1918 break; 1919 case BYTE_MNEM_SUFFIX: 1920 i.types[op] = Imm8 | Imm8S; 1921 break; 1922 } 1923 break; 1924 } 1925 } 1926 } 1927 1928 /* Try to use the smallest displacement type too. */ 1929 static void 1930 optimize_disp () 1931 { 1932 int op; 1933 1934 for (op = i.operands; --op >= 0;) 1935 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant) 1936 { 1937 offsetT disp = i.op[op].disps->X_add_number; 1938 1939 if (i.types[op] & Disp16) 1940 { 1941 /* We know this operand is at most 16 bits, so 1942 convert to a signed 16 bit number before trying 1943 to see whether it will fit in an even smaller 1944 size. */ 1945 1946 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); 1947 } 1948 else if (i.types[op] & Disp32) 1949 { 1950 /* We know this operand is at most 32 bits, so convert to a 1951 signed 32 bit number before trying to see whether it will 1952 fit in an even smaller size. */ 1953 disp &= (((offsetT) 2 << 31) - 1); 1954 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); 1955 } 1956 if (flag_code == CODE_64BIT) 1957 { 1958 if (fits_in_signed_long (disp)) 1959 i.types[op] |= Disp32S; 1960 if (fits_in_unsigned_long (disp)) 1961 i.types[op] |= Disp32; 1962 } 1963 if ((i.types[op] & (Disp32 | Disp32S | Disp16)) 1964 && fits_in_signed_byte (disp)) 1965 i.types[op] |= Disp8; 1966 } 1967 } 1968 1969 static int 1970 match_template () 1971 { 1972 /* Points to template once we've found it. */ 1973 const template *t; 1974 unsigned int overlap0, overlap1, overlap2; 1975 unsigned int found_reverse_match; 1976 int suffix_check; 1977 1978 #define MATCH(overlap, given, template) \ 1979 ((overlap & ~JumpAbsolute) \ 1980 && (((given) & (BaseIndex | JumpAbsolute)) \ 1981 == ((overlap) & (BaseIndex | JumpAbsolute)))) 1982 1983 /* If given types r0 and r1 are registers they must be of the same type 1984 unless the expected operand type register overlap is null. 1985 Note that Acc in a template matches every size of reg. */ 1986 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ 1987 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \ 1988 || ((g0) & Reg) == ((g1) & Reg) \ 1989 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) 1990 1991 overlap0 = 0; 1992 overlap1 = 0; 1993 overlap2 = 0; 1994 found_reverse_match = 0; 1995 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX 1996 ? No_bSuf 1997 : (i.suffix == WORD_MNEM_SUFFIX 1998 ? No_wSuf 1999 : (i.suffix == SHORT_MNEM_SUFFIX 2000 ? No_sSuf 2001 : (i.suffix == LONG_MNEM_SUFFIX 2002 ? No_lSuf 2003 : (i.suffix == QWORD_MNEM_SUFFIX 2004 ? No_qSuf 2005 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX 2006 ? No_xSuf : 0)))))); 2007 2008 t = current_templates->start; 2009 if (i.suffix == QWORD_MNEM_SUFFIX 2010 && flag_code != CODE_64BIT 2011 && (!intel_syntax 2012 || (!(t->opcode_modifier & IgnoreSize) 2013 && ! intel_float_operand (t->name))) 2014 && (!(t->operand_types[0] & (RegMMX | RegXMM)) 2015 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM))) 2016 && (t->base_opcode != 0x0fc7 2017 || t->extension_opcode != 1 /* cmpxchg8b */)) 2018 t = current_templates->end; 2019 for (; t < current_templates->end; t++) 2020 { 2021 /* Must have right number of operands. */ 2022 if (i.operands != t->operands) 2023 continue; 2024 2025 /* Check the suffix, except for some instructions in intel mode. */ 2026 if ((t->opcode_modifier & suffix_check) 2027 && !(intel_syntax 2028 && (t->opcode_modifier & IgnoreSize)) 2029 && !(intel_syntax 2030 && t->base_opcode == 0xd9 2031 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ 2032 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ 2033 continue; 2034 2035 /* Do not verify operands when there are none. */ 2036 else if (!t->operands) 2037 { 2038 if (t->cpu_flags & ~cpu_arch_flags) 2039 continue; 2040 /* We've found a match; break out of loop. */ 2041 break; 2042 } 2043 2044 overlap0 = i.types[0] & t->operand_types[0]; 2045 switch (t->operands) 2046 { 2047 case 1: 2048 if (!MATCH (overlap0, i.types[0], t->operand_types[0])) 2049 continue; 2050 break; 2051 case 2: 2052 case 3: 2053 overlap1 = i.types[1] & t->operand_types[1]; 2054 if (!MATCH (overlap0, i.types[0], t->operand_types[0]) 2055 || !MATCH (overlap1, i.types[1], t->operand_types[1]) 2056 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], 2057 t->operand_types[0], 2058 overlap1, i.types[1], 2059 t->operand_types[1])) 2060 { 2061 /* Check if other direction is valid ... */ 2062 if ((t->opcode_modifier & (D | FloatD)) == 0) 2063 continue; 2064 2065 /* Try reversing direction of operands. */ 2066 overlap0 = i.types[0] & t->operand_types[1]; 2067 overlap1 = i.types[1] & t->operand_types[0]; 2068 if (!MATCH (overlap0, i.types[0], t->operand_types[1]) 2069 || !MATCH (overlap1, i.types[1], t->operand_types[0]) 2070 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], 2071 t->operand_types[1], 2072 overlap1, i.types[1], 2073 t->operand_types[0])) 2074 { 2075 /* Does not match either direction. */ 2076 continue; 2077 } 2078 /* found_reverse_match holds which of D or FloatDR 2079 we've found. */ 2080 found_reverse_match = t->opcode_modifier & (D | FloatDR); 2081 } 2082 /* Found a forward 2 operand match here. */ 2083 else if (t->operands == 3) 2084 { 2085 /* Here we make use of the fact that there are no 2086 reverse match 3 operand instructions, and all 3 2087 operand instructions only need to be checked for 2088 register consistency between operands 2 and 3. */ 2089 overlap2 = i.types[2] & t->operand_types[2]; 2090 if (!MATCH (overlap2, i.types[2], t->operand_types[2]) 2091 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], 2092 t->operand_types[1], 2093 overlap2, i.types[2], 2094 t->operand_types[2])) 2095 2096 continue; 2097 } 2098 /* Found either forward/reverse 2 or 3 operand match here: 2099 slip through to break. */ 2100 } 2101 if (t->cpu_flags & ~cpu_arch_flags) 2102 { 2103 found_reverse_match = 0; 2104 continue; 2105 } 2106 /* We've found a match; break out of loop. */ 2107 break; 2108 } 2109 2110 if (t == current_templates->end) 2111 { 2112 /* We found no match. */ 2113 as_bad (_("suffix or operands invalid for `%s'"), 2114 current_templates->start->name); 2115 return 0; 2116 } 2117 2118 if (!quiet_warnings) 2119 { 2120 if (!intel_syntax 2121 && ((i.types[0] & JumpAbsolute) 2122 != (t->operand_types[0] & JumpAbsolute))) 2123 { 2124 as_warn (_("indirect %s without `*'"), t->name); 2125 } 2126 2127 if ((t->opcode_modifier & (IsPrefix | IgnoreSize)) 2128 == (IsPrefix | IgnoreSize)) 2129 { 2130 /* Warn them that a data or address size prefix doesn't 2131 affect assembly of the next line of code. */ 2132 as_warn (_("stand-alone `%s' prefix"), t->name); 2133 } 2134 } 2135 2136 /* Copy the template we found. */ 2137 i.tm = *t; 2138 if (found_reverse_match) 2139 { 2140 /* If we found a reverse match we must alter the opcode 2141 direction bit. found_reverse_match holds bits to change 2142 (different for int & float insns). */ 2143 2144 i.tm.base_opcode ^= found_reverse_match; 2145 2146 i.tm.operand_types[0] = t->operand_types[1]; 2147 i.tm.operand_types[1] = t->operand_types[0]; 2148 } 2149 2150 return 1; 2151 } 2152 2153 static int 2154 check_string () 2155 { 2156 int mem_op = (i.types[0] & AnyMem) ? 0 : 1; 2157 if ((i.tm.operand_types[mem_op] & EsSeg) != 0) 2158 { 2159 if (i.seg[0] != NULL && i.seg[0] != &es) 2160 { 2161 as_bad (_("`%s' operand %d must use `%%es' segment"), 2162 i.tm.name, 2163 mem_op + 1); 2164 return 0; 2165 } 2166 /* There's only ever one segment override allowed per instruction. 2167 This instruction possibly has a legal segment override on the 2168 second operand, so copy the segment to where non-string 2169 instructions store it, allowing common code. */ 2170 i.seg[0] = i.seg[1]; 2171 } 2172 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) 2173 { 2174 if (i.seg[1] != NULL && i.seg[1] != &es) 2175 { 2176 as_bad (_("`%s' operand %d must use `%%es' segment"), 2177 i.tm.name, 2178 mem_op + 2); 2179 return 0; 2180 } 2181 } 2182 return 1; 2183 } 2184 2185 static int 2186 process_suffix (void) 2187 { 2188 /* If matched instruction specifies an explicit instruction mnemonic 2189 suffix, use it. */ 2190 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64)) 2191 { 2192 if (i.tm.opcode_modifier & Size16) 2193 i.suffix = WORD_MNEM_SUFFIX; 2194 else if (i.tm.opcode_modifier & Size64) 2195 i.suffix = QWORD_MNEM_SUFFIX; 2196 else 2197 i.suffix = LONG_MNEM_SUFFIX; 2198 } 2199 else if (i.reg_operands) 2200 { 2201 /* If there's no instruction mnemonic suffix we try to invent one 2202 based on register operands. */ 2203 if (!i.suffix) 2204 { 2205 /* We take i.suffix from the last register operand specified, 2206 Destination register type is more significant than source 2207 register type. */ 2208 int op; 2209 2210 for (op = i.operands; --op >= 0;) 2211 if ((i.types[op] & Reg) 2212 && !(i.tm.operand_types[op] & InOutPortReg)) 2213 { 2214 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : 2215 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : 2216 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : 2217 LONG_MNEM_SUFFIX); 2218 break; 2219 } 2220 } 2221 else if (i.suffix == BYTE_MNEM_SUFFIX) 2222 { 2223 if (!check_byte_reg ()) 2224 return 0; 2225 } 2226 else if (i.suffix == LONG_MNEM_SUFFIX) 2227 { 2228 if (!check_long_reg ()) 2229 return 0; 2230 } 2231 else if (i.suffix == QWORD_MNEM_SUFFIX) 2232 { 2233 if (!check_qword_reg ()) 2234 return 0; 2235 } 2236 else if (i.suffix == WORD_MNEM_SUFFIX) 2237 { 2238 if (!check_word_reg ()) 2239 return 0; 2240 } 2241 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) 2242 /* Do nothing if the instruction is going to ignore the prefix. */ 2243 ; 2244 else 2245 abort (); 2246 } 2247 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) 2248 { 2249 i.suffix = stackop_size; 2250 if (i.suffix == QWORD_MNEM_SUFFIX 2251 && (i.tm.opcode_modifier & No_qSuf)) 2252 i.suffix = LONG_MNEM_SUFFIX; 2253 } 2254 2255 /* Change the opcode based on the operand size given by i.suffix; 2256 We need not change things for byte insns. */ 2257 if (!i.suffix && (i.tm.opcode_modifier & W)) 2258 { 2259 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); 2260 return 0; 2261 } 2262 2263 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) 2264 { 2265 /* It's not a byte, select word/dword operation. */ 2266 if (i.tm.opcode_modifier & W) 2267 { 2268 if (i.tm.opcode_modifier & ShortForm) 2269 i.tm.base_opcode |= 8; 2270 else 2271 i.tm.base_opcode |= 1; 2272 } 2273 2274 /* Now select between word & dword operations via the operand 2275 size prefix, except for instructions that will ignore this 2276 prefix anyway. */ 2277 if (i.suffix != QWORD_MNEM_SUFFIX 2278 && !(i.tm.opcode_modifier & IgnoreSize) 2279 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) 2280 || (flag_code == CODE_64BIT 2281 && (i.tm.opcode_modifier & JumpByte)))) 2282 { 2283 unsigned int prefix = DATA_PREFIX_OPCODE; 2284 2285 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ 2286 prefix = ADDR_PREFIX_OPCODE; 2287 2288 if (!add_prefix (prefix)) 2289 return 0; 2290 } 2291 2292 /* Set mode64 for an operand. */ 2293 if (i.suffix == QWORD_MNEM_SUFFIX 2294 && flag_code == CODE_64BIT 2295 && (i.tm.opcode_modifier & NoRex64) == 0) 2296 i.rex |= REX_MODE64; 2297 2298 /* Size floating point instruction. */ 2299 if (i.suffix == LONG_MNEM_SUFFIX) 2300 if (i.tm.opcode_modifier & FloatMF) 2301 i.tm.base_opcode ^= 4; 2302 } 2303 2304 return 1; 2305 } 2306 2307 static int 2308 check_byte_reg (void) 2309 { 2310 int op; 2311 2312 for (op = i.operands; --op >= 0;) 2313 { 2314 /* If this is an eight bit register, it's OK. If it's the 16 or 2315 32 bit version of an eight bit register, we will just use the 2316 low portion, and that's OK too. */ 2317 if (i.types[op] & Reg8) 2318 continue; 2319 2320 /* movzx and movsx should not generate this warning. */ 2321 if (intel_syntax 2322 && (i.tm.base_opcode == 0xfb7 2323 || i.tm.base_opcode == 0xfb6 2324 || i.tm.base_opcode == 0x63 2325 || i.tm.base_opcode == 0xfbe 2326 || i.tm.base_opcode == 0xfbf)) 2327 continue; 2328 2329 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 2330 #if 0 2331 /* Check that the template allows eight bit regs. This 2332 kills insns such as `orb $1,%edx', which maybe should be 2333 allowed. */ 2334 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg)) 2335 #endif 2336 ) 2337 { 2338 /* Prohibit these changes in the 64bit mode, since the 2339 lowering is more complicated. */ 2340 if (flag_code == CODE_64BIT 2341 && (i.tm.operand_types[op] & InOutPortReg) == 0) 2342 { 2343 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2344 i.op[op].regs->reg_name, 2345 i.suffix); 2346 return 0; 2347 } 2348 #if REGISTER_WARNINGS 2349 if (!quiet_warnings 2350 && (i.tm.operand_types[op] & InOutPortReg) == 0) 2351 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), 2352 (i.op[op].regs + (i.types[op] & Reg16 2353 ? REGNAM_AL - REGNAM_AX 2354 : REGNAM_AL - REGNAM_EAX))->reg_name, 2355 i.op[op].regs->reg_name, 2356 i.suffix); 2357 #endif 2358 continue; 2359 } 2360 /* Any other register is bad. */ 2361 if (i.types[op] & (Reg | RegMMX | RegXMM 2362 | SReg2 | SReg3 2363 | Control | Debug | Test 2364 | FloatReg | FloatAcc)) 2365 { 2366 as_bad (_("`%%%s' not allowed with `%s%c'"), 2367 i.op[op].regs->reg_name, 2368 i.tm.name, 2369 i.suffix); 2370 return 0; 2371 } 2372 } 2373 return 1; 2374 } 2375 2376 static int 2377 check_long_reg () 2378 { 2379 int op; 2380 2381 for (op = i.operands; --op >= 0;) 2382 /* Reject eight bit registers, except where the template requires 2383 them. (eg. movzb) */ 2384 if ((i.types[op] & Reg8) != 0 2385 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) 2386 { 2387 as_bad (_("`%%%s' not allowed with `%s%c'"), 2388 i.op[op].regs->reg_name, 2389 i.tm.name, 2390 i.suffix); 2391 return 0; 2392 } 2393 /* Warn if the e prefix on a general reg is missing. */ 2394 else if ((!quiet_warnings || flag_code == CODE_64BIT) 2395 && (i.types[op] & Reg16) != 0 2396 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) 2397 { 2398 /* Prohibit these changes in the 64bit mode, since the 2399 lowering is more complicated. */ 2400 if (flag_code == CODE_64BIT) 2401 { 2402 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2403 i.op[op].regs->reg_name, 2404 i.suffix); 2405 return 0; 2406 } 2407 #if REGISTER_WARNINGS 2408 else 2409 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), 2410 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, 2411 i.op[op].regs->reg_name, 2412 i.suffix); 2413 #endif 2414 } 2415 /* Warn if the r prefix on a general reg is missing. */ 2416 else if ((i.types[op] & Reg64) != 0 2417 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) 2418 { 2419 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2420 i.op[op].regs->reg_name, 2421 i.suffix); 2422 return 0; 2423 } 2424 return 1; 2425 } 2426 2427 static int 2428 check_qword_reg () 2429 { 2430 int op; 2431 2432 for (op = i.operands; --op >= 0; ) 2433 /* Reject eight bit registers, except where the template requires 2434 them. (eg. movzb) */ 2435 if ((i.types[op] & Reg8) != 0 2436 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) 2437 { 2438 as_bad (_("`%%%s' not allowed with `%s%c'"), 2439 i.op[op].regs->reg_name, 2440 i.tm.name, 2441 i.suffix); 2442 return 0; 2443 } 2444 /* Warn if the e prefix on a general reg is missing. */ 2445 else if (((i.types[op] & Reg16) != 0 2446 || (i.types[op] & Reg32) != 0) 2447 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) 2448 { 2449 /* Prohibit these changes in the 64bit mode, since the 2450 lowering is more complicated. */ 2451 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2452 i.op[op].regs->reg_name, 2453 i.suffix); 2454 return 0; 2455 } 2456 return 1; 2457 } 2458 2459 static int 2460 check_word_reg () 2461 { 2462 int op; 2463 for (op = i.operands; --op >= 0;) 2464 /* Reject eight bit registers, except where the template requires 2465 them. (eg. movzb) */ 2466 if ((i.types[op] & Reg8) != 0 2467 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) 2468 { 2469 as_bad (_("`%%%s' not allowed with `%s%c'"), 2470 i.op[op].regs->reg_name, 2471 i.tm.name, 2472 i.suffix); 2473 return 0; 2474 } 2475 /* Warn if the e prefix on a general reg is present. */ 2476 else if ((!quiet_warnings || flag_code == CODE_64BIT) 2477 && (i.types[op] & Reg32) != 0 2478 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0) 2479 { 2480 /* Prohibit these changes in the 64bit mode, since the 2481 lowering is more complicated. */ 2482 if (flag_code == CODE_64BIT) 2483 { 2484 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), 2485 i.op[op].regs->reg_name, 2486 i.suffix); 2487 return 0; 2488 } 2489 else 2490 #if REGISTER_WARNINGS 2491 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), 2492 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, 2493 i.op[op].regs->reg_name, 2494 i.suffix); 2495 #endif 2496 } 2497 return 1; 2498 } 2499 2500 static int 2501 finalize_imm () 2502 { 2503 unsigned int overlap0, overlap1, overlap2; 2504 2505 overlap0 = i.types[0] & i.tm.operand_types[0]; 2506 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64)) 2507 && overlap0 != Imm8 && overlap0 != Imm8S 2508 && overlap0 != Imm16 && overlap0 != Imm32S 2509 && overlap0 != Imm32 && overlap0 != Imm64) 2510 { 2511 if (i.suffix) 2512 { 2513 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX 2514 ? Imm8 | Imm8S 2515 : (i.suffix == WORD_MNEM_SUFFIX 2516 ? Imm16 2517 : (i.suffix == QWORD_MNEM_SUFFIX 2518 ? Imm64 | Imm32S 2519 : Imm32))); 2520 } 2521 else if (overlap0 == (Imm16 | Imm32S | Imm32) 2522 || overlap0 == (Imm16 | Imm32) 2523 || overlap0 == (Imm16 | Imm32S)) 2524 { 2525 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) 2526 ? Imm16 : Imm32S); 2527 } 2528 if (overlap0 != Imm8 && overlap0 != Imm8S 2529 && overlap0 != Imm16 && overlap0 != Imm32S 2530 && overlap0 != Imm32 && overlap0 != Imm64) 2531 { 2532 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); 2533 return 0; 2534 } 2535 } 2536 i.types[0] = overlap0; 2537 2538 overlap1 = i.types[1] & i.tm.operand_types[1]; 2539 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32)) 2540 && overlap1 != Imm8 && overlap1 != Imm8S 2541 && overlap1 != Imm16 && overlap1 != Imm32S 2542 && overlap1 != Imm32 && overlap1 != Imm64) 2543 { 2544 if (i.suffix) 2545 { 2546 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX 2547 ? Imm8 | Imm8S 2548 : (i.suffix == WORD_MNEM_SUFFIX 2549 ? Imm16 2550 : (i.suffix == QWORD_MNEM_SUFFIX 2551 ? Imm64 | Imm32S 2552 : Imm32))); 2553 } 2554 else if (overlap1 == (Imm16 | Imm32 | Imm32S) 2555 || overlap1 == (Imm16 | Imm32) 2556 || overlap1 == (Imm16 | Imm32S)) 2557 { 2558 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) 2559 ? Imm16 : Imm32S); 2560 } 2561 if (overlap1 != Imm8 && overlap1 != Imm8S 2562 && overlap1 != Imm16 && overlap1 != Imm32S 2563 && overlap1 != Imm32 && overlap1 != Imm64) 2564 { 2565 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix); 2566 return 0; 2567 } 2568 } 2569 i.types[1] = overlap1; 2570 2571 overlap2 = i.types[2] & i.tm.operand_types[2]; 2572 assert ((overlap2 & Imm) == 0); 2573 i.types[2] = overlap2; 2574 2575 return 1; 2576 } 2577 2578 static int 2579 process_operands () 2580 { 2581 /* Default segment register this instruction will use for memory 2582 accesses. 0 means unknown. This is only for optimizing out 2583 unnecessary segment overrides. */ 2584 const seg_entry *default_seg = 0; 2585 2586 /* The imul $imm, %reg instruction is converted into 2587 imul $imm, %reg, %reg, and the clr %reg instruction 2588 is converted into xor %reg, %reg. */ 2589 if (i.tm.opcode_modifier & regKludge) 2590 { 2591 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; 2592 /* Pretend we saw the extra register operand. */ 2593 assert (i.op[first_reg_op + 1].regs == 0); 2594 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; 2595 i.types[first_reg_op + 1] = i.types[first_reg_op]; 2596 i.reg_operands = 2; 2597 } 2598 2599 if (i.tm.opcode_modifier & ShortForm) 2600 { 2601 /* The register or float register operand is in operand 0 or 1. */ 2602 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; 2603 /* Register goes in low 3 bits of opcode. */ 2604 i.tm.base_opcode |= i.op[op].regs->reg_num; 2605 if ((i.op[op].regs->reg_flags & RegRex) != 0) 2606 i.rex |= REX_EXTZ; 2607 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) 2608 { 2609 /* Warn about some common errors, but press on regardless. 2610 The first case can be generated by gcc (<= 2.8.1). */ 2611 if (i.operands == 2) 2612 { 2613 /* Reversed arguments on faddp, fsubp, etc. */ 2614 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, 2615 i.op[1].regs->reg_name, 2616 i.op[0].regs->reg_name); 2617 } 2618 else 2619 { 2620 /* Extraneous `l' suffix on fp insn. */ 2621 as_warn (_("translating to `%s %%%s'"), i.tm.name, 2622 i.op[0].regs->reg_name); 2623 } 2624 } 2625 } 2626 else if (i.tm.opcode_modifier & Modrm) 2627 { 2628 /* The opcode is completed (modulo i.tm.extension_opcode which 2629 must be put into the modrm byte). Now, we make the modrm and 2630 index base bytes based on all the info we've collected. */ 2631 2632 default_seg = build_modrm_byte (); 2633 } 2634 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) 2635 { 2636 if (i.tm.base_opcode == POP_SEG_SHORT 2637 && i.op[0].regs->reg_num == 1) 2638 { 2639 as_bad (_("you can't `pop %%cs'")); 2640 return 0; 2641 } 2642 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); 2643 if ((i.op[0].regs->reg_flags & RegRex) != 0) 2644 i.rex |= REX_EXTZ; 2645 } 2646 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32) 2647 { 2648 default_seg = &ds; 2649 } 2650 else if ((i.tm.opcode_modifier & IsString) != 0) 2651 { 2652 /* For the string instructions that allow a segment override 2653 on one of their operands, the default segment is ds. */ 2654 default_seg = &ds; 2655 } 2656 2657 if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings) 2658 as_warn (_("segment override on `lea' is ineffectual")); 2659 2660 /* If a segment was explicitly specified, and the specified segment 2661 is not the default, use an opcode prefix to select it. If we 2662 never figured out what the default segment is, then default_seg 2663 will be zero at this point, and the specified segment prefix will 2664 always be used. */ 2665 if ((i.seg[0]) && (i.seg[0] != default_seg)) 2666 { 2667 if (!add_prefix (i.seg[0]->seg_prefix)) 2668 return 0; 2669 } 2670 return 1; 2671 } 2672 2673 static const seg_entry * 2674 build_modrm_byte () 2675 { 2676 const seg_entry *default_seg = 0; 2677 2678 /* i.reg_operands MUST be the number of real register operands; 2679 implicit registers do not count. */ 2680 if (i.reg_operands == 2) 2681 { 2682 unsigned int source, dest; 2683 source = ((i.types[0] 2684 & (Reg | RegMMX | RegXMM 2685 | SReg2 | SReg3 2686 | Control | Debug | Test)) 2687 ? 0 : 1); 2688 dest = source + 1; 2689 2690 i.rm.mode = 3; 2691 /* One of the register operands will be encoded in the i.tm.reg 2692 field, the other in the combined i.tm.mode and i.tm.regmem 2693 fields. If no form of this instruction supports a memory 2694 destination operand, then we assume the source operand may 2695 sometimes be a memory operand and so we need to store the 2696 destination in the i.rm.reg field. */ 2697 if ((i.tm.operand_types[dest] & AnyMem) == 0) 2698 { 2699 i.rm.reg = i.op[dest].regs->reg_num; 2700 i.rm.regmem = i.op[source].regs->reg_num; 2701 if ((i.op[dest].regs->reg_flags & RegRex) != 0) 2702 i.rex |= REX_EXTX; 2703 if ((i.op[source].regs->reg_flags & RegRex) != 0) 2704 i.rex |= REX_EXTZ; 2705 } 2706 else 2707 { 2708 i.rm.reg = i.op[source].regs->reg_num; 2709 i.rm.regmem = i.op[dest].regs->reg_num; 2710 if ((i.op[dest].regs->reg_flags & RegRex) != 0) 2711 i.rex |= REX_EXTZ; 2712 if ((i.op[source].regs->reg_flags & RegRex) != 0) 2713 i.rex |= REX_EXTX; 2714 } 2715 } 2716 else 2717 { /* If it's not 2 reg operands... */ 2718 if (i.mem_operands) 2719 { 2720 unsigned int fake_zero_displacement = 0; 2721 unsigned int op = ((i.types[0] & AnyMem) 2722 ? 0 2723 : (i.types[1] & AnyMem) ? 1 : 2); 2724 2725 default_seg = &ds; 2726 2727 if (i.base_reg == 0) 2728 { 2729 i.rm.mode = 0; 2730 if (!i.disp_operands) 2731 fake_zero_displacement = 1; 2732 if (i.index_reg == 0) 2733 { 2734 /* Operand is just <disp> */ 2735 if (flag_code == CODE_64BIT) 2736 { 2737 /* 64bit mode overwrites the 32bit absolute 2738 addressing by RIP relative addressing and 2739 absolute addressing is encoded by one of the 2740 redundant SIB forms. */ 2741 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 2742 i.sib.base = NO_BASE_REGISTER; 2743 i.sib.index = NO_INDEX_REGISTER; 2744 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32); 2745 } 2746 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) 2747 { 2748 i.rm.regmem = NO_BASE_REGISTER_16; 2749 i.types[op] = Disp16; 2750 } 2751 else 2752 { 2753 i.rm.regmem = NO_BASE_REGISTER; 2754 i.types[op] = Disp32; 2755 } 2756 } 2757 else /* !i.base_reg && i.index_reg */ 2758 { 2759 i.sib.index = i.index_reg->reg_num; 2760 i.sib.base = NO_BASE_REGISTER; 2761 i.sib.scale = i.log2_scale_factor; 2762 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 2763 i.types[op] &= ~Disp; 2764 if (flag_code != CODE_64BIT) 2765 i.types[op] |= Disp32; /* Must be 32 bit */ 2766 else 2767 i.types[op] |= Disp32S; 2768 if ((i.index_reg->reg_flags & RegRex) != 0) 2769 i.rex |= REX_EXTY; 2770 } 2771 } 2772 /* RIP addressing for 64bit mode. */ 2773 else if (i.base_reg->reg_type == BaseIndex) 2774 { 2775 i.rm.regmem = NO_BASE_REGISTER; 2776 i.types[op] &= ~ Disp; 2777 i.types[op] |= Disp32S; 2778 i.flags[op] = Operand_PCrel; 2779 if (! i.disp_operands) 2780 fake_zero_displacement = 1; 2781 } 2782 else if (i.base_reg->reg_type & Reg16) 2783 { 2784 switch (i.base_reg->reg_num) 2785 { 2786 case 3: /* (%bx) */ 2787 if (i.index_reg == 0) 2788 i.rm.regmem = 7; 2789 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ 2790 i.rm.regmem = i.index_reg->reg_num - 6; 2791 break; 2792 case 5: /* (%bp) */ 2793 default_seg = &ss; 2794 if (i.index_reg == 0) 2795 { 2796 i.rm.regmem = 6; 2797 if ((i.types[op] & Disp) == 0) 2798 { 2799 /* fake (%bp) into 0(%bp) */ 2800 i.types[op] |= Disp8; 2801 fake_zero_displacement = 1; 2802 } 2803 } 2804 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ 2805 i.rm.regmem = i.index_reg->reg_num - 6 + 2; 2806 break; 2807 default: /* (%si) -> 4 or (%di) -> 5 */ 2808 i.rm.regmem = i.base_reg->reg_num - 6 + 4; 2809 } 2810 i.rm.mode = mode_from_disp_size (i.types[op]); 2811 } 2812 else /* i.base_reg and 32/64 bit mode */ 2813 { 2814 if (flag_code == CODE_64BIT 2815 && (i.types[op] & Disp)) 2816 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32); 2817 2818 i.rm.regmem = i.base_reg->reg_num; 2819 if ((i.base_reg->reg_flags & RegRex) != 0) 2820 i.rex |= REX_EXTZ; 2821 i.sib.base = i.base_reg->reg_num; 2822 /* x86-64 ignores REX prefix bit here to avoid decoder 2823 complications. */ 2824 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) 2825 { 2826 default_seg = &ss; 2827 if (i.disp_operands == 0) 2828 { 2829 fake_zero_displacement = 1; 2830 i.types[op] |= Disp8; 2831 } 2832 } 2833 else if (i.base_reg->reg_num == ESP_REG_NUM) 2834 { 2835 default_seg = &ss; 2836 } 2837 i.sib.scale = i.log2_scale_factor; 2838 if (i.index_reg == 0) 2839 { 2840 /* <disp>(%esp) becomes two byte modrm with no index 2841 register. We've already stored the code for esp 2842 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. 2843 Any base register besides %esp will not use the 2844 extra modrm byte. */ 2845 i.sib.index = NO_INDEX_REGISTER; 2846 #if !SCALE1_WHEN_NO_INDEX 2847 /* Another case where we force the second modrm byte. */ 2848 if (i.log2_scale_factor) 2849 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 2850 #endif 2851 } 2852 else 2853 { 2854 i.sib.index = i.index_reg->reg_num; 2855 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; 2856 if ((i.index_reg->reg_flags & RegRex) != 0) 2857 i.rex |= REX_EXTY; 2858 } 2859 i.rm.mode = mode_from_disp_size (i.types[op]); 2860 } 2861 2862 if (fake_zero_displacement) 2863 { 2864 /* Fakes a zero displacement assuming that i.types[op] 2865 holds the correct displacement size. */ 2866 expressionS *exp; 2867 2868 assert (i.op[op].disps == 0); 2869 exp = &disp_expressions[i.disp_operands++]; 2870 i.op[op].disps = exp; 2871 exp->X_op = O_constant; 2872 exp->X_add_number = 0; 2873 exp->X_add_symbol = (symbolS *) 0; 2874 exp->X_op_symbol = (symbolS *) 0; 2875 } 2876 } 2877 2878 /* Fill in i.rm.reg or i.rm.regmem field with register operand 2879 (if any) based on i.tm.extension_opcode. Again, we must be 2880 careful to make sure that segment/control/debug/test/MMX 2881 registers are coded into the i.rm.reg field. */ 2882 if (i.reg_operands) 2883 { 2884 unsigned int op = 2885 ((i.types[0] 2886 & (Reg | RegMMX | RegXMM 2887 | SReg2 | SReg3 2888 | Control | Debug | Test)) 2889 ? 0 2890 : ((i.types[1] 2891 & (Reg | RegMMX | RegXMM 2892 | SReg2 | SReg3 2893 | Control | Debug | Test)) 2894 ? 1 2895 : 2)); 2896 /* If there is an extension opcode to put here, the register 2897 number must be put into the regmem field. */ 2898 if (i.tm.extension_opcode != None) 2899 { 2900 i.rm.regmem = i.op[op].regs->reg_num; 2901 if ((i.op[op].regs->reg_flags & RegRex) != 0) 2902 i.rex |= REX_EXTZ; 2903 } 2904 else 2905 { 2906 i.rm.reg = i.op[op].regs->reg_num; 2907 if ((i.op[op].regs->reg_flags & RegRex) != 0) 2908 i.rex |= REX_EXTX; 2909 } 2910 2911 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we 2912 must set it to 3 to indicate this is a register operand 2913 in the regmem field. */ 2914 if (!i.mem_operands) 2915 i.rm.mode = 3; 2916 } 2917 2918 /* Fill in i.rm.reg field with extension opcode (if any). */ 2919 if (i.tm.extension_opcode != None) 2920 i.rm.reg = i.tm.extension_opcode; 2921 } 2922 return default_seg; 2923 } 2924 2925 static void 2926 output_branch () 2927 { 2928 char *p; 2929 int code16; 2930 int prefix; 2931 relax_substateT subtype; 2932 symbolS *sym; 2933 offsetT off; 2934 2935 code16 = 0; 2936 if (flag_code == CODE_16BIT) 2937 code16 = CODE16; 2938 2939 prefix = 0; 2940 if (i.prefix[DATA_PREFIX] != 0) 2941 { 2942 prefix = 1; 2943 i.prefixes -= 1; 2944 code16 ^= CODE16; 2945 } 2946 /* Pentium4 branch hints. */ 2947 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ 2948 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) 2949 { 2950 prefix++; 2951 i.prefixes--; 2952 } 2953 if (i.prefix[REX_PREFIX] != 0) 2954 { 2955 prefix++; 2956 i.prefixes--; 2957 } 2958 2959 if (i.prefixes != 0 && !intel_syntax) 2960 as_warn (_("skipping prefixes on this instruction")); 2961 2962 /* It's always a symbol; End frag & setup for relax. 2963 Make sure there is enough room in this frag for the largest 2964 instruction we may generate in md_convert_frag. This is 2 2965 bytes for the opcode and room for the prefix and largest 2966 displacement. */ 2967 frag_grow (prefix + 2 + 4); 2968 /* Prefix and 1 opcode byte go in fr_fix. */ 2969 p = frag_more (prefix + 1); 2970 if (i.prefix[DATA_PREFIX] != 0) 2971 *p++ = DATA_PREFIX_OPCODE; 2972 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE 2973 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) 2974 *p++ = i.prefix[SEG_PREFIX]; 2975 if (i.prefix[REX_PREFIX] != 0) 2976 *p++ = i.prefix[REX_PREFIX]; 2977 *p = i.tm.base_opcode; 2978 2979 if ((unsigned char) *p == JUMP_PC_RELATIVE) 2980 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); 2981 else if ((cpu_arch_flags & Cpu386) != 0) 2982 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); 2983 else 2984 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); 2985 subtype |= code16; 2986 2987 sym = i.op[0].disps->X_add_symbol; 2988 off = i.op[0].disps->X_add_number; 2989 2990 if (i.op[0].disps->X_op != O_constant 2991 && i.op[0].disps->X_op != O_symbol) 2992 { 2993 /* Handle complex expressions. */ 2994 sym = make_expr_symbol (i.op[0].disps); 2995 off = 0; 2996 } 2997 2998 /* 1 possible extra opcode + 4 byte displacement go in var part. 2999 Pass reloc in fr_var. */ 3000 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); 3001 } 3002 3003 static void 3004 output_jump () 3005 { 3006 char *p; 3007 int size; 3008 fixS *fixP; 3009 3010 if (i.tm.opcode_modifier & JumpByte) 3011 { 3012 /* This is a loop or jecxz type instruction. */ 3013 size = 1; 3014 if (i.prefix[ADDR_PREFIX] != 0) 3015 { 3016 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); 3017 i.prefixes -= 1; 3018 } 3019 /* Pentium4 branch hints. */ 3020 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ 3021 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) 3022 { 3023 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); 3024 i.prefixes--; 3025 } 3026 } 3027 else 3028 { 3029 int code16; 3030 3031 code16 = 0; 3032 if (flag_code == CODE_16BIT) 3033 code16 = CODE16; 3034 3035 if (i.prefix[DATA_PREFIX] != 0) 3036 { 3037 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); 3038 i.prefixes -= 1; 3039 code16 ^= CODE16; 3040 } 3041 3042 size = 4; 3043 if (code16) 3044 size = 2; 3045 } 3046 3047 if (i.prefix[REX_PREFIX] != 0) 3048 { 3049 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); 3050 i.prefixes -= 1; 3051 } 3052 3053 if (i.prefixes != 0 && !intel_syntax) 3054 as_warn (_("skipping prefixes on this instruction")); 3055 3056 p = frag_more (1 + size); 3057 *p++ = i.tm.base_opcode; 3058 3059 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, 3060 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); 3061 3062 /* All jumps handled here are signed, but don't use a signed limit 3063 check for 32 and 16 bit jumps as we want to allow wrap around at 3064 4G and 64k respectively. */ 3065 if (size == 1) 3066 fixP->fx_signed = 1; 3067 } 3068 3069 static void 3070 output_interseg_jump () 3071 { 3072 char *p; 3073 int size; 3074 int prefix; 3075 int code16; 3076 3077 code16 = 0; 3078 if (flag_code == CODE_16BIT) 3079 code16 = CODE16; 3080 3081 prefix = 0; 3082 if (i.prefix[DATA_PREFIX] != 0) 3083 { 3084 prefix = 1; 3085 i.prefixes -= 1; 3086 code16 ^= CODE16; 3087 } 3088 if (i.prefix[REX_PREFIX] != 0) 3089 { 3090 prefix++; 3091 i.prefixes -= 1; 3092 } 3093 3094 size = 4; 3095 if (code16) 3096 size = 2; 3097 3098 if (i.prefixes != 0 && !intel_syntax) 3099 as_warn (_("skipping prefixes on this instruction")); 3100 3101 /* 1 opcode; 2 segment; offset */ 3102 p = frag_more (prefix + 1 + 2 + size); 3103 3104 if (i.prefix[DATA_PREFIX] != 0) 3105 *p++ = DATA_PREFIX_OPCODE; 3106 3107 if (i.prefix[REX_PREFIX] != 0) 3108 *p++ = i.prefix[REX_PREFIX]; 3109 3110 *p++ = i.tm.base_opcode; 3111 if (i.op[1].imms->X_op == O_constant) 3112 { 3113 offsetT n = i.op[1].imms->X_add_number; 3114 3115 if (size == 2 3116 && !fits_in_unsigned_word (n) 3117 && !fits_in_signed_word (n)) 3118 { 3119 as_bad (_("16-bit jump out of range")); 3120 return; 3121 } 3122 md_number_to_chars (p, n, size); 3123 } 3124 else 3125 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 3126 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); 3127 if (i.op[0].imms->X_op != O_constant) 3128 as_bad (_("can't handle non absolute segment in `%s'"), 3129 i.tm.name); 3130 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); 3131 } 3132 3133 static void 3134 output_insn () 3135 { 3136 fragS *insn_start_frag; 3137 offsetT insn_start_off; 3138 3139 /* Tie dwarf2 debug info to the address at the start of the insn. 3140 We can't do this after the insn has been output as the current 3141 frag may have been closed off. eg. by frag_var. */ 3142 dwarf2_emit_insn (0); 3143 3144 insn_start_frag = frag_now; 3145 insn_start_off = frag_now_fix (); 3146 3147 /* Output jumps. */ 3148 if (i.tm.opcode_modifier & Jump) 3149 output_branch (); 3150 else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) 3151 output_jump (); 3152 else if (i.tm.opcode_modifier & JumpInterSegment) 3153 output_interseg_jump (); 3154 else 3155 { 3156 /* Output normal instructions here. */ 3157 char *p; 3158 unsigned char *q; 3159 unsigned int prefix; 3160 3161 /* All opcodes on i386 have either 1 or 2 bytes, PadLock instructions 3162 have 3 bytes. We may use one more higher byte to specify a prefix 3163 the instruction requires. */ 3164 if (((i.tm.cpu_flags & (CpuPadLock|CpuSSSE3|CpuAES|CpuPCLMUL)) != 0) 3165 && (i.tm.base_opcode & 0xff000000) != 0) 3166 { 3167 unsigned int prefix; 3168 prefix = (i.tm.base_opcode >> 24) & 0xff; 3169 3170 if (prefix != REPE_PREFIX_OPCODE 3171 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE) 3172 add_prefix (prefix); 3173 } 3174 else if (i.tm.base_opcode == 0x660f3880 || i.tm.base_opcode == 0x660f3881) { 3175 /* invept and invvpid are 3 byte instructions with a 3176 mandatory prefix. */ 3177 if (i.tm.base_opcode & 0xff000000) 3178 { 3179 prefix = (i.tm.base_opcode >> 24) & 0xff; 3180 add_prefix (prefix); 3181 } 3182 } 3183 else 3184 if ((i.tm.cpu_flags & CpuPadLock) == 0 3185 && (i.tm.base_opcode & 0xff0000) != 0) 3186 add_prefix ((i.tm.base_opcode >> 16) & 0xff); 3187 3188 /* The prefix bytes. */ 3189 for (q = i.prefix; 3190 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); 3191 q++) 3192 { 3193 if (*q) 3194 { 3195 p = frag_more (1); 3196 md_number_to_chars (p, (valueT) *q, 1); 3197 } 3198 } 3199 3200 /* Now the opcode; be careful about word order here! */ 3201 if (fits_in_unsigned_byte (i.tm.base_opcode)) 3202 { 3203 FRAG_APPEND_1_CHAR (i.tm.base_opcode); 3204 } 3205 else 3206 { 3207 if ((i.tm.cpu_flags & (CpuPadLock|CpuSSSE3|CpuAES|CpuPCLMUL)) != 0) 3208 { 3209 p = frag_more (3); 3210 *p++ = (i.tm.base_opcode >> 16) & 0xff; 3211 } 3212 else if (i.tm.base_opcode == 0x660f3880 || 3213 i.tm.base_opcode == 0x660f3881) 3214 { 3215 p = frag_more (3); 3216 *p++ = (i.tm.base_opcode >> 16) & 0xff; 3217 } 3218 else 3219 p = frag_more (2); 3220 3221 /* Put out high byte first: can't use md_number_to_chars! */ 3222 *p++ = (i.tm.base_opcode >> 8) & 0xff; 3223 *p = i.tm.base_opcode & 0xff; 3224 } 3225 3226 /* Now the modrm byte and sib byte (if present). */ 3227 if (i.tm.opcode_modifier & Modrm) 3228 { 3229 p = frag_more (1); 3230 md_number_to_chars (p, 3231 (valueT) (i.rm.regmem << 0 3232 | i.rm.reg << 3 3233 | i.rm.mode << 6), 3234 1); 3235 /* If i.rm.regmem == ESP (4) 3236 && i.rm.mode != (Register mode) 3237 && not 16 bit 3238 ==> need second modrm byte. */ 3239 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING 3240 && i.rm.mode != 3 3241 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) 3242 { 3243 p = frag_more (1); 3244 md_number_to_chars (p, 3245 (valueT) (i.sib.base << 0 3246 | i.sib.index << 3 3247 | i.sib.scale << 6), 3248 1); 3249 } 3250 } 3251 3252 if (i.disp_operands) 3253 output_disp (insn_start_frag, insn_start_off); 3254 3255 if (i.imm_operands) 3256 output_imm (insn_start_frag, insn_start_off); 3257 } 3258 3259 #ifdef DEBUG386 3260 if (flag_debug) 3261 { 3262 pi (line, &i); 3263 } 3264 #endif /* DEBUG386 */ 3265 } 3266 3267 static void 3268 output_disp (insn_start_frag, insn_start_off) 3269 fragS *insn_start_frag; 3270 offsetT insn_start_off; 3271 { 3272 char *p; 3273 unsigned int n; 3274 3275 for (n = 0; n < i.operands; n++) 3276 { 3277 if (i.types[n] & Disp) 3278 { 3279 if (i.op[n].disps->X_op == O_constant) 3280 { 3281 int size; 3282 offsetT val; 3283 3284 size = 4; 3285 if (i.types[n] & (Disp8 | Disp16 | Disp64)) 3286 { 3287 size = 2; 3288 if (i.types[n] & Disp8) 3289 size = 1; 3290 if (i.types[n] & Disp64) 3291 size = 8; 3292 } 3293 val = offset_in_range (i.op[n].disps->X_add_number, 3294 size); 3295 p = frag_more (size); 3296 md_number_to_chars (p, val, size); 3297 } 3298 else 3299 { 3300 enum bfd_reloc_code_real reloc_type; 3301 int size = 4; 3302 int sign = 0; 3303 int pcrel = (i.flags[n] & Operand_PCrel) != 0; 3304 3305 /* The PC relative address is computed relative 3306 to the instruction boundary, so in case immediate 3307 fields follows, we need to adjust the value. */ 3308 if (pcrel && i.imm_operands) 3309 { 3310 int imm_size = 4; 3311 unsigned int n1; 3312 3313 for (n1 = 0; n1 < i.operands; n1++) 3314 if (i.types[n1] & Imm) 3315 { 3316 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64)) 3317 { 3318 imm_size = 2; 3319 if (i.types[n1] & (Imm8 | Imm8S)) 3320 imm_size = 1; 3321 if (i.types[n1] & Imm64) 3322 imm_size = 8; 3323 } 3324 break; 3325 } 3326 /* We should find the immediate. */ 3327 if (n1 == i.operands) 3328 abort (); 3329 i.op[n].disps->X_add_number -= imm_size; 3330 } 3331 3332 if (i.types[n] & Disp32S) 3333 sign = 1; 3334 3335 if (i.types[n] & (Disp16 | Disp64)) 3336 { 3337 size = 2; 3338 if (i.types[n] & Disp64) 3339 size = 8; 3340 } 3341 3342 p = frag_more (size); 3343 reloc_type = reloc (size, pcrel, sign, i.reloc[n]); 3344 if (reloc_type == BFD_RELOC_32 3345 && GOT_symbol 3346 && GOT_symbol == i.op[n].disps->X_add_symbol 3347 && (i.op[n].disps->X_op == O_symbol 3348 || (i.op[n].disps->X_op == O_add 3349 && ((symbol_get_value_expression 3350 (i.op[n].disps->X_op_symbol)->X_op) 3351 == O_subtract)))) 3352 { 3353 offsetT add; 3354 3355 if (insn_start_frag == frag_now) 3356 add = (p - frag_now->fr_literal) - insn_start_off; 3357 else 3358 { 3359 fragS *fr; 3360 3361 add = insn_start_frag->fr_fix - insn_start_off; 3362 for (fr = insn_start_frag->fr_next; 3363 fr && fr != frag_now; fr = fr->fr_next) 3364 add += fr->fr_fix; 3365 add += p - frag_now->fr_literal; 3366 } 3367 3368 /* We don't support dynamic linking on x86-64 yet. */ 3369 if (flag_code == CODE_64BIT) 3370 abort (); 3371 reloc_type = BFD_RELOC_386_GOTPC; 3372 i.op[n].disps->X_add_number += add; 3373 } 3374 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 3375 i.op[n].disps, pcrel, reloc_type); 3376 } 3377 } 3378 } 3379 } 3380 3381 static void 3382 output_imm (insn_start_frag, insn_start_off) 3383 fragS *insn_start_frag; 3384 offsetT insn_start_off; 3385 { 3386 char *p; 3387 unsigned int n; 3388 3389 for (n = 0; n < i.operands; n++) 3390 { 3391 if (i.types[n] & Imm) 3392 { 3393 if (i.op[n].imms->X_op == O_constant) 3394 { 3395 int size; 3396 offsetT val; 3397 3398 size = 4; 3399 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) 3400 { 3401 size = 2; 3402 if (i.types[n] & (Imm8 | Imm8S)) 3403 size = 1; 3404 else if (i.types[n] & Imm64) 3405 size = 8; 3406 } 3407 val = offset_in_range (i.op[n].imms->X_add_number, 3408 size); 3409 p = frag_more (size); 3410 md_number_to_chars (p, val, size); 3411 } 3412 else 3413 { 3414 /* Not absolute_section. 3415 Need a 32-bit fixup (don't support 8bit 3416 non-absolute imms). Try to support other 3417 sizes ... */ 3418 enum bfd_reloc_code_real reloc_type; 3419 int size = 4; 3420 int sign = 0; 3421 3422 if ((i.types[n] & (Imm32S)) 3423 && i.suffix == QWORD_MNEM_SUFFIX) 3424 sign = 1; 3425 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) 3426 { 3427 size = 2; 3428 if (i.types[n] & (Imm8 | Imm8S)) 3429 size = 1; 3430 if (i.types[n] & Imm64) 3431 size = 8; 3432 } 3433 3434 p = frag_more (size); 3435 reloc_type = reloc (size, 0, sign, i.reloc[n]); 3436 3437 /* This is tough to explain. We end up with this one if we 3438 * have operands that look like 3439 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to 3440 * obtain the absolute address of the GOT, and it is strongly 3441 * preferable from a performance point of view to avoid using 3442 * a runtime relocation for this. The actual sequence of 3443 * instructions often look something like: 3444 * 3445 * call .L66 3446 * .L66: 3447 * popl %ebx 3448 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx 3449 * 3450 * The call and pop essentially return the absolute address 3451 * of the label .L66 and store it in %ebx. The linker itself 3452 * will ultimately change the first operand of the addl so 3453 * that %ebx points to the GOT, but to keep things simple, the 3454 * .o file must have this operand set so that it generates not 3455 * the absolute address of .L66, but the absolute address of 3456 * itself. This allows the linker itself simply treat a GOTPC 3457 * relocation as asking for a pcrel offset to the GOT to be 3458 * added in, and the addend of the relocation is stored in the 3459 * operand field for the instruction itself. 3460 * 3461 * Our job here is to fix the operand so that it would add 3462 * the correct offset so that %ebx would point to itself. The 3463 * thing that is tricky is that .-.L66 will point to the 3464 * beginning of the instruction, so we need to further modify 3465 * the operand so that it will point to itself. There are 3466 * other cases where you have something like: 3467 * 3468 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] 3469 * 3470 * and here no correction would be required. Internally in 3471 * the assembler we treat operands of this form as not being 3472 * pcrel since the '.' is explicitly mentioned, and I wonder 3473 * whether it would simplify matters to do it this way. Who 3474 * knows. In earlier versions of the PIC patches, the 3475 * pcrel_adjust field was used to store the correction, but 3476 * since the expression is not pcrel, I felt it would be 3477 * confusing to do it this way. */ 3478 3479 if (reloc_type == BFD_RELOC_32 3480 && GOT_symbol 3481 && GOT_symbol == i.op[n].imms->X_add_symbol 3482 && (i.op[n].imms->X_op == O_symbol 3483 || (i.op[n].imms->X_op == O_add 3484 && ((symbol_get_value_expression 3485 (i.op[n].imms->X_op_symbol)->X_op) 3486 == O_subtract)))) 3487 { 3488 offsetT add; 3489 3490 if (insn_start_frag == frag_now) 3491 add = (p - frag_now->fr_literal) - insn_start_off; 3492 else 3493 { 3494 fragS *fr; 3495 3496 add = insn_start_frag->fr_fix - insn_start_off; 3497 for (fr = insn_start_frag->fr_next; 3498 fr && fr != frag_now; fr = fr->fr_next) 3499 add += fr->fr_fix; 3500 add += p - frag_now->fr_literal; 3501 } 3502 3503 /* We don't support dynamic linking on x86-64 yet. */ 3504 if (flag_code == CODE_64BIT) 3505 abort (); 3506 reloc_type = BFD_RELOC_386_GOTPC; 3507 i.op[n].imms->X_add_number += add; 3508 } 3509 fix_new_exp (frag_now, p - frag_now->fr_literal, size, 3510 i.op[n].imms, 0, reloc_type); 3511 } 3512 } 3513 } 3514 } 3515 3516 #ifndef LEX_AT 3517 static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *)); 3518 3519 /* Parse operands of the form 3520 <symbol>@GOTOFF+<nnn> 3521 and similar .plt or .got references. 3522 3523 If we find one, set up the correct relocation in RELOC and copy the 3524 input string, minus the `@GOTOFF' into a malloc'd buffer for 3525 parsing by the calling routine. Return this buffer, and if ADJUST 3526 is non-null set it to the length of the string we removed from the 3527 input line. Otherwise return NULL. */ 3528 static char * 3529 lex_got (reloc, adjust) 3530 enum bfd_reloc_code_real *reloc; 3531 int *adjust; 3532 { 3533 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" }; 3534 static const struct { 3535 const char *str; 3536 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE]; 3537 } gotrel[] = { 3538 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } }, 3539 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } }, 3540 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } }, 3541 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } }, 3542 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } }, 3543 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } }, 3544 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } }, 3545 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } }, 3546 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } }, 3547 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } }, 3548 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } }, 3549 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } }, 3550 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } } 3551 }; 3552 char *cp; 3553 unsigned int j; 3554 3555 for (cp = input_line_pointer; *cp != '@'; cp++) 3556 if (is_end_of_line[(unsigned char) *cp]) 3557 return NULL; 3558 3559 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++) 3560 { 3561 int len; 3562 3563 len = strlen (gotrel[j].str); 3564 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) 3565 { 3566 if (gotrel[j].rel[(unsigned int) flag_code] != 0) 3567 { 3568 int first, second; 3569 char *tmpbuf, *past_reloc; 3570 3571 *reloc = gotrel[j].rel[(unsigned int) flag_code]; 3572 if (adjust) 3573 *adjust = len; 3574 3575 if (GOT_symbol == NULL) 3576 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); 3577 3578 /* Replace the relocation token with ' ', so that 3579 errors like foo@GOTOFF1 will be detected. */ 3580 3581 /* The length of the first part of our input line. */ 3582 first = cp - input_line_pointer; 3583 3584 /* The second part goes from after the reloc token until 3585 (and including) an end_of_line char. Don't use strlen 3586 here as the end_of_line char may not be a NUL. */ 3587 past_reloc = cp + 1 + len; 3588 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; ) 3589 ; 3590 second = cp - past_reloc; 3591 3592 /* Allocate and copy string. The trailing NUL shouldn't 3593 be necessary, but be safe. */ 3594 tmpbuf = xmalloc (first + second + 2); 3595 memcpy (tmpbuf, input_line_pointer, first); 3596 tmpbuf[first] = ' '; 3597 memcpy (tmpbuf + first + 1, past_reloc, second); 3598 tmpbuf[first + second + 1] = '\0'; 3599 return tmpbuf; 3600 } 3601 3602 as_bad (_("@%s reloc is not supported in %s bit mode"), 3603 gotrel[j].str, mode_name[(unsigned int) flag_code]); 3604 return NULL; 3605 } 3606 } 3607 3608 /* Might be a symbol version string. Don't as_bad here. */ 3609 return NULL; 3610 } 3611 3612 /* x86_cons_fix_new is called via the expression parsing code when a 3613 reloc is needed. We use this hook to get the correct .got reloc. */ 3614 static enum bfd_reloc_code_real got_reloc = NO_RELOC; 3615 3616 void 3617 x86_cons_fix_new (frag, off, len, exp) 3618 fragS *frag; 3619 unsigned int off; 3620 unsigned int len; 3621 expressionS *exp; 3622 { 3623 enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc); 3624 got_reloc = NO_RELOC; 3625 fix_new_exp (frag, off, len, exp, 0, r); 3626 } 3627 3628 void 3629 x86_cons (exp, size) 3630 expressionS *exp; 3631 int size; 3632 { 3633 if (size == 4) 3634 { 3635 /* Handle @GOTOFF and the like in an expression. */ 3636 char *save; 3637 char *gotfree_input_line; 3638 int adjust; 3639 3640 save = input_line_pointer; 3641 gotfree_input_line = lex_got (&got_reloc, &adjust); 3642 if (gotfree_input_line) 3643 input_line_pointer = gotfree_input_line; 3644 3645 expression (exp); 3646 3647 if (gotfree_input_line) 3648 { 3649 /* expression () has merrily parsed up to the end of line, 3650 or a comma - in the wrong buffer. Transfer how far 3651 input_line_pointer has moved to the right buffer. */ 3652 input_line_pointer = (save 3653 + (input_line_pointer - gotfree_input_line) 3654 + adjust); 3655 free (gotfree_input_line); 3656 } 3657 } 3658 else 3659 expression (exp); 3660 } 3661 #endif 3662 3663 static int i386_immediate PARAMS ((char *)); 3664 3665 static int 3666 i386_immediate (imm_start) 3667 char *imm_start; 3668 { 3669 char *save_input_line_pointer; 3670 #ifndef LEX_AT 3671 char *gotfree_input_line; 3672 #endif 3673 segT exp_seg = 0; 3674 expressionS *exp; 3675 3676 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) 3677 { 3678 as_bad (_("only 1 or 2 immediate operands are allowed")); 3679 return 0; 3680 } 3681 3682 exp = &im_expressions[i.imm_operands++]; 3683 i.op[this_operand].imms = exp; 3684 3685 if (is_space_char (*imm_start)) 3686 ++imm_start; 3687 3688 save_input_line_pointer = input_line_pointer; 3689 input_line_pointer = imm_start; 3690 3691 #ifndef LEX_AT 3692 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); 3693 if (gotfree_input_line) 3694 input_line_pointer = gotfree_input_line; 3695 #endif 3696 3697 exp_seg = expression (exp); 3698 3699 SKIP_WHITESPACE (); 3700 if (*input_line_pointer) 3701 as_bad (_("junk `%s' after expression"), input_line_pointer); 3702 3703 input_line_pointer = save_input_line_pointer; 3704 #ifndef LEX_AT 3705 if (gotfree_input_line) 3706 free (gotfree_input_line); 3707 #endif 3708 3709 if (exp->X_op == O_absent || exp->X_op == O_big) 3710 { 3711 /* Missing or bad expr becomes absolute 0. */ 3712 as_bad (_("missing or invalid immediate expression `%s' taken as 0"), 3713 imm_start); 3714 exp->X_op = O_constant; 3715 exp->X_add_number = 0; 3716 exp->X_add_symbol = (symbolS *) 0; 3717 exp->X_op_symbol = (symbolS *) 0; 3718 } 3719 else if (exp->X_op == O_constant) 3720 { 3721 /* Size it properly later. */ 3722 i.types[this_operand] |= Imm64; 3723 /* If BFD64, sign extend val. */ 3724 if (!use_rela_relocations) 3725 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) 3726 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); 3727 } 3728 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 3729 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour 3730 && exp_seg != absolute_section 3731 && exp_seg != text_section 3732 && exp_seg != data_section 3733 && exp_seg != bss_section 3734 && exp_seg != undefined_section 3735 && !bfd_is_com_section (exp_seg)) 3736 { 3737 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 3738 return 0; 3739 } 3740 #endif 3741 else 3742 { 3743 /* This is an address. The size of the address will be 3744 determined later, depending on destination register, 3745 suffix, or the default for the section. */ 3746 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64; 3747 } 3748 3749 return 1; 3750 } 3751 3752 static char *i386_scale PARAMS ((char *)); 3753 3754 static char * 3755 i386_scale (scale) 3756 char *scale; 3757 { 3758 offsetT val; 3759 char *save = input_line_pointer; 3760 3761 input_line_pointer = scale; 3762 val = get_absolute_expression (); 3763 3764 switch (val) 3765 { 3766 case 0: 3767 case 1: 3768 i.log2_scale_factor = 0; 3769 break; 3770 case 2: 3771 i.log2_scale_factor = 1; 3772 break; 3773 case 4: 3774 i.log2_scale_factor = 2; 3775 break; 3776 case 8: 3777 i.log2_scale_factor = 3; 3778 break; 3779 default: 3780 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), 3781 scale); 3782 input_line_pointer = save; 3783 return NULL; 3784 } 3785 if (i.log2_scale_factor != 0 && i.index_reg == 0) 3786 { 3787 as_warn (_("scale factor of %d without an index register"), 3788 1 << i.log2_scale_factor); 3789 #if SCALE1_WHEN_NO_INDEX 3790 i.log2_scale_factor = 0; 3791 #endif 3792 } 3793 scale = input_line_pointer; 3794 input_line_pointer = save; 3795 return scale; 3796 } 3797 3798 static int i386_displacement PARAMS ((char *, char *)); 3799 3800 static int 3801 i386_displacement (disp_start, disp_end) 3802 char *disp_start; 3803 char *disp_end; 3804 { 3805 expressionS *exp; 3806 segT exp_seg = 0; 3807 char *save_input_line_pointer; 3808 #ifndef LEX_AT 3809 char *gotfree_input_line; 3810 #endif 3811 int bigdisp = Disp32; 3812 3813 if (flag_code == CODE_64BIT) 3814 { 3815 if (i.prefix[ADDR_PREFIX] == 0) 3816 bigdisp = Disp64; 3817 } 3818 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) 3819 bigdisp = Disp16; 3820 i.types[this_operand] |= bigdisp; 3821 3822 exp = &disp_expressions[i.disp_operands]; 3823 i.op[this_operand].disps = exp; 3824 i.disp_operands++; 3825 save_input_line_pointer = input_line_pointer; 3826 input_line_pointer = disp_start; 3827 END_STRING_AND_SAVE (disp_end); 3828 3829 #ifndef GCC_ASM_O_HACK 3830 #define GCC_ASM_O_HACK 0 3831 #endif 3832 #if GCC_ASM_O_HACK 3833 END_STRING_AND_SAVE (disp_end + 1); 3834 if ((i.types[this_operand] & BaseIndex) != 0 3835 && displacement_string_end[-1] == '+') 3836 { 3837 /* This hack is to avoid a warning when using the "o" 3838 constraint within gcc asm statements. 3839 For instance: 3840 3841 #define _set_tssldt_desc(n,addr,limit,type) \ 3842 __asm__ __volatile__ ( \ 3843 "movw %w2,%0\n\t" \ 3844 "movw %w1,2+%0\n\t" \ 3845 "rorl $16,%1\n\t" \ 3846 "movb %b1,4+%0\n\t" \ 3847 "movb %4,5+%0\n\t" \ 3848 "movb $0,6+%0\n\t" \ 3849 "movb %h1,7+%0\n\t" \ 3850 "rorl $16,%1" \ 3851 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) 3852 3853 This works great except that the output assembler ends 3854 up looking a bit weird if it turns out that there is 3855 no offset. You end up producing code that looks like: 3856 3857 #APP 3858 movw $235,(%eax) 3859 movw %dx,2+(%eax) 3860 rorl $16,%edx 3861 movb %dl,4+(%eax) 3862 movb $137,5+(%eax) 3863 movb $0,6+(%eax) 3864 movb %dh,7+(%eax) 3865 rorl $16,%edx 3866 #NO_APP 3867 3868 So here we provide the missing zero. */ 3869 3870 *displacement_string_end = '0'; 3871 } 3872 #endif 3873 #ifndef LEX_AT 3874 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); 3875 if (gotfree_input_line) 3876 input_line_pointer = gotfree_input_line; 3877 #endif 3878 3879 exp_seg = expression (exp); 3880 3881 SKIP_WHITESPACE (); 3882 if (*input_line_pointer) 3883 as_bad (_("junk `%s' after expression"), input_line_pointer); 3884 #if GCC_ASM_O_HACK 3885 RESTORE_END_STRING (disp_end + 1); 3886 #endif 3887 RESTORE_END_STRING (disp_end); 3888 input_line_pointer = save_input_line_pointer; 3889 #ifndef LEX_AT 3890 if (gotfree_input_line) 3891 free (gotfree_input_line); 3892 #endif 3893 3894 /* We do this to make sure that the section symbol is in 3895 the symbol table. We will ultimately change the relocation 3896 to be relative to the beginning of the section. */ 3897 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF 3898 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) 3899 { 3900 if (exp->X_op != O_symbol) 3901 { 3902 as_bad (_("bad expression used with @%s"), 3903 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL 3904 ? "GOTPCREL" 3905 : "GOTOFF")); 3906 return 0; 3907 } 3908 3909 if (S_IS_LOCAL (exp->X_add_symbol) 3910 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) 3911 section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); 3912 exp->X_op = O_subtract; 3913 exp->X_op_symbol = GOT_symbol; 3914 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) 3915 i.reloc[this_operand] = BFD_RELOC_32_PCREL; 3916 else 3917 i.reloc[this_operand] = BFD_RELOC_32; 3918 } 3919 3920 if (exp->X_op == O_absent || exp->X_op == O_big) 3921 { 3922 /* Missing or bad expr becomes absolute 0. */ 3923 as_bad (_("missing or invalid displacement expression `%s' taken as 0"), 3924 disp_start); 3925 exp->X_op = O_constant; 3926 exp->X_add_number = 0; 3927 exp->X_add_symbol = (symbolS *) 0; 3928 exp->X_op_symbol = (symbolS *) 0; 3929 } 3930 3931 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 3932 if (exp->X_op != O_constant 3933 && OUTPUT_FLAVOR == bfd_target_aout_flavour 3934 && exp_seg != absolute_section 3935 && exp_seg != text_section 3936 && exp_seg != data_section 3937 && exp_seg != bss_section 3938 && exp_seg != undefined_section 3939 && !bfd_is_com_section (exp_seg)) 3940 { 3941 as_bad (_("unimplemented segment %s in operand"), exp_seg->name); 3942 return 0; 3943 } 3944 #endif 3945 else if (flag_code == CODE_64BIT) 3946 i.types[this_operand] |= Disp32S | Disp32; 3947 return 1; 3948 } 3949 3950 static int i386_index_check PARAMS ((const char *)); 3951 3952 /* Make sure the memory operand we've been dealt is valid. 3953 Return 1 on success, 0 on a failure. */ 3954 3955 static int 3956 i386_index_check (operand_string) 3957 const char *operand_string; 3958 { 3959 int ok; 3960 #if INFER_ADDR_PREFIX 3961 int fudged = 0; 3962 3963 tryprefix: 3964 #endif 3965 ok = 1; 3966 if (flag_code == CODE_64BIT) 3967 { 3968 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32); 3969 3970 if ((i.base_reg 3971 && ((i.base_reg->reg_type & RegXX) == 0) 3972 && (i.base_reg->reg_type != BaseIndex 3973 || i.index_reg)) 3974 || (i.index_reg 3975 && ((i.index_reg->reg_type & (RegXX | BaseIndex)) 3976 != (RegXX | BaseIndex)))) 3977 ok = 0; 3978 } 3979 else 3980 { 3981 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) 3982 { 3983 /* 16bit checks. */ 3984 if ((i.base_reg 3985 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex)) 3986 != (Reg16 | BaseIndex))) 3987 || (i.index_reg 3988 && (((i.index_reg->reg_type & (Reg16 | BaseIndex)) 3989 != (Reg16 | BaseIndex)) 3990 || !(i.base_reg 3991 && i.base_reg->reg_num < 6 3992 && i.index_reg->reg_num >= 6 3993 && i.log2_scale_factor == 0)))) 3994 ok = 0; 3995 } 3996 else 3997 { 3998 /* 32bit checks. */ 3999 if ((i.base_reg 4000 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) 4001 || (i.index_reg 4002 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex)) 4003 != (Reg32 | BaseIndex)))) 4004 ok = 0; 4005 } 4006 } 4007 if (!ok) 4008 { 4009 #if INFER_ADDR_PREFIX 4010 if (i.prefix[ADDR_PREFIX] == 0) 4011 { 4012 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; 4013 i.prefixes += 1; 4014 /* Change the size of any displacement too. At most one of 4015 Disp16 or Disp32 is set. 4016 FIXME. There doesn't seem to be any real need for separate 4017 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. 4018 Removing them would probably clean up the code quite a lot. */ 4019 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32))) 4020 i.types[this_operand] ^= (Disp16 | Disp32); 4021 fudged = 1; 4022 goto tryprefix; 4023 } 4024 if (fudged) 4025 as_bad (_("`%s' is not a valid base/index expression"), 4026 operand_string); 4027 else 4028 #endif 4029 as_bad (_("`%s' is not a valid %s bit base/index expression"), 4030 operand_string, 4031 flag_code_names[flag_code]); 4032 } 4033 return ok; 4034 } 4035 4036 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero 4037 on error. */ 4038 4039 static int 4040 i386_operand (operand_string) 4041 char *operand_string; 4042 { 4043 const reg_entry *r; 4044 char *end_op; 4045 char *op_string = operand_string; 4046 4047 if (is_space_char (*op_string)) 4048 ++op_string; 4049 4050 /* We check for an absolute prefix (differentiating, 4051 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ 4052 if (*op_string == ABSOLUTE_PREFIX) 4053 { 4054 ++op_string; 4055 if (is_space_char (*op_string)) 4056 ++op_string; 4057 i.types[this_operand] |= JumpAbsolute; 4058 } 4059 4060 /* Check if operand is a register. */ 4061 if ((*op_string == REGISTER_PREFIX || allow_naked_reg) 4062 && (r = parse_register (op_string, &end_op)) != NULL) 4063 { 4064 /* Check for a segment override by searching for ':' after a 4065 segment register. */ 4066 op_string = end_op; 4067 if (is_space_char (*op_string)) 4068 ++op_string; 4069 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) 4070 { 4071 switch (r->reg_num) 4072 { 4073 case 0: 4074 i.seg[i.mem_operands] = &es; 4075 break; 4076 case 1: 4077 i.seg[i.mem_operands] = &cs; 4078 break; 4079 case 2: 4080 i.seg[i.mem_operands] = &ss; 4081 break; 4082 case 3: 4083 i.seg[i.mem_operands] = &ds; 4084 break; 4085 case 4: 4086 i.seg[i.mem_operands] = &fs; 4087 break; 4088 case 5: 4089 i.seg[i.mem_operands] = &gs; 4090 break; 4091 } 4092 4093 /* Skip the ':' and whitespace. */ 4094 ++op_string; 4095 if (is_space_char (*op_string)) 4096 ++op_string; 4097 4098 if (!is_digit_char (*op_string) 4099 && !is_identifier_char (*op_string) 4100 && *op_string != '(' 4101 && *op_string != ABSOLUTE_PREFIX) 4102 { 4103 as_bad (_("bad memory operand `%s'"), op_string); 4104 return 0; 4105 } 4106 /* Handle case of %es:*foo. */ 4107 if (*op_string == ABSOLUTE_PREFIX) 4108 { 4109 ++op_string; 4110 if (is_space_char (*op_string)) 4111 ++op_string; 4112 i.types[this_operand] |= JumpAbsolute; 4113 } 4114 goto do_memory_reference; 4115 } 4116 if (*op_string) 4117 { 4118 as_bad (_("junk `%s' after register"), op_string); 4119 return 0; 4120 } 4121 i.types[this_operand] |= r->reg_type & ~BaseIndex; 4122 i.op[this_operand].regs = r; 4123 i.reg_operands++; 4124 } 4125 else if (*op_string == REGISTER_PREFIX) 4126 { 4127 as_bad (_("bad register name `%s'"), op_string); 4128 return 0; 4129 } 4130 else if (*op_string == IMMEDIATE_PREFIX) 4131 { 4132 ++op_string; 4133 if (i.types[this_operand] & JumpAbsolute) 4134 { 4135 as_bad (_("immediate operand illegal with absolute jump")); 4136 return 0; 4137 } 4138 if (!i386_immediate (op_string)) 4139 return 0; 4140 } 4141 else if (is_digit_char (*op_string) 4142 || is_identifier_char (*op_string) 4143 || *op_string == '(') 4144 { 4145 /* This is a memory reference of some sort. */ 4146 char *base_string; 4147 4148 /* Start and end of displacement string expression (if found). */ 4149 char *displacement_string_start; 4150 char *displacement_string_end; 4151 4152 do_memory_reference: 4153 if ((i.mem_operands == 1 4154 && (current_templates->start->opcode_modifier & IsString) == 0) 4155 || i.mem_operands == 2) 4156 { 4157 as_bad (_("too many memory references for `%s'"), 4158 current_templates->start->name); 4159 return 0; 4160 } 4161 4162 /* Check for base index form. We detect the base index form by 4163 looking for an ')' at the end of the operand, searching 4164 for the '(' matching it, and finding a REGISTER_PREFIX or ',' 4165 after the '('. */ 4166 base_string = op_string + strlen (op_string); 4167 4168 --base_string; 4169 if (is_space_char (*base_string)) 4170 --base_string; 4171 4172 /* If we only have a displacement, set-up for it to be parsed later. */ 4173 displacement_string_start = op_string; 4174 displacement_string_end = base_string + 1; 4175 4176 if (*base_string == ')') 4177 { 4178 char *temp_string; 4179 unsigned int parens_balanced = 1; 4180 /* We've already checked that the number of left & right ()'s are 4181 equal, so this loop will not be infinite. */ 4182 do 4183 { 4184 base_string--; 4185 if (*base_string == ')') 4186 parens_balanced++; 4187 if (*base_string == '(') 4188 parens_balanced--; 4189 } 4190 while (parens_balanced); 4191 4192 temp_string = base_string; 4193 4194 /* Skip past '(' and whitespace. */ 4195 ++base_string; 4196 if (is_space_char (*base_string)) 4197 ++base_string; 4198 4199 if (*base_string == ',' 4200 || ((*base_string == REGISTER_PREFIX || allow_naked_reg) 4201 && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) 4202 { 4203 displacement_string_end = temp_string; 4204 4205 i.types[this_operand] |= BaseIndex; 4206 4207 if (i.base_reg) 4208 { 4209 base_string = end_op; 4210 if (is_space_char (*base_string)) 4211 ++base_string; 4212 } 4213 4214 /* There may be an index reg or scale factor here. */ 4215 if (*base_string == ',') 4216 { 4217 ++base_string; 4218 if (is_space_char (*base_string)) 4219 ++base_string; 4220 4221 if ((*base_string == REGISTER_PREFIX || allow_naked_reg) 4222 && (i.index_reg = parse_register (base_string, &end_op)) != NULL) 4223 { 4224 base_string = end_op; 4225 if (is_space_char (*base_string)) 4226 ++base_string; 4227 if (*base_string == ',') 4228 { 4229 ++base_string; 4230 if (is_space_char (*base_string)) 4231 ++base_string; 4232 } 4233 else if (*base_string != ')') 4234 { 4235 as_bad (_("expecting `,' or `)' after index register in `%s'"), 4236 operand_string); 4237 return 0; 4238 } 4239 } 4240 else if (*base_string == REGISTER_PREFIX) 4241 { 4242 as_bad (_("bad register name `%s'"), base_string); 4243 return 0; 4244 } 4245 4246 /* Check for scale factor. */ 4247 if (*base_string != ')') 4248 { 4249 char *end_scale = i386_scale (base_string); 4250 4251 if (!end_scale) 4252 return 0; 4253 4254 base_string = end_scale; 4255 if (is_space_char (*base_string)) 4256 ++base_string; 4257 if (*base_string != ')') 4258 { 4259 as_bad (_("expecting `)' after scale factor in `%s'"), 4260 operand_string); 4261 return 0; 4262 } 4263 } 4264 else if (!i.index_reg) 4265 { 4266 as_bad (_("expecting index register or scale factor after `,'; got '%c'"), 4267 *base_string); 4268 return 0; 4269 } 4270 } 4271 else if (*base_string != ')') 4272 { 4273 as_bad (_("expecting `,' or `)' after base register in `%s'"), 4274 operand_string); 4275 return 0; 4276 } 4277 } 4278 else if (*base_string == REGISTER_PREFIX) 4279 { 4280 as_bad (_("bad register name `%s'"), base_string); 4281 return 0; 4282 } 4283 } 4284 4285 /* If there's an expression beginning the operand, parse it, 4286 assuming displacement_string_start and 4287 displacement_string_end are meaningful. */ 4288 if (displacement_string_start != displacement_string_end) 4289 { 4290 if (!i386_displacement (displacement_string_start, 4291 displacement_string_end)) 4292 return 0; 4293 } 4294 4295 /* Special case for (%dx) while doing input/output op. */ 4296 if (i.base_reg 4297 && i.base_reg->reg_type == (Reg16 | InOutPortReg) 4298 && i.index_reg == 0 4299 && i.log2_scale_factor == 0 4300 && i.seg[i.mem_operands] == 0 4301 && (i.types[this_operand] & Disp) == 0) 4302 { 4303 i.types[this_operand] = InOutPortReg; 4304 return 1; 4305 } 4306 4307 if (i386_index_check (operand_string) == 0) 4308 return 0; 4309 i.mem_operands++; 4310 } 4311 else 4312 { 4313 /* It's not a memory operand; argh! */ 4314 as_bad (_("invalid char %s beginning operand %d `%s'"), 4315 output_invalid (*op_string), 4316 this_operand + 1, 4317 op_string); 4318 return 0; 4319 } 4320 return 1; /* Normal return. */ 4321 } 4322 4323 /* md_estimate_size_before_relax() 4324 4325 Called just before relax() for rs_machine_dependent frags. The x86 4326 assembler uses these frags to handle variable size jump 4327 instructions. 4328 4329 Any symbol that is now undefined will not become defined. 4330 Return the correct fr_subtype in the frag. 4331 Return the initial "guess for variable size of frag" to caller. 4332 The guess is actually the growth beyond the fixed part. Whatever 4333 we do to grow the fixed or variable part contributes to our 4334 returned value. */ 4335 4336 int 4337 md_estimate_size_before_relax (fragP, segment) 4338 fragS *fragP; 4339 segT segment; 4340 { 4341 /* We've already got fragP->fr_subtype right; all we have to do is 4342 check for un-relaxable symbols. On an ELF system, we can't relax 4343 an externally visible symbol, because it may be overridden by a 4344 shared library. */ 4345 if (S_GET_SEGMENT (fragP->fr_symbol) != segment 4346 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 4347 || (OUTPUT_FLAVOR == bfd_target_elf_flavour 4348 && (S_IS_EXTERNAL (fragP->fr_symbol) 4349 || S_IS_WEAK (fragP->fr_symbol))) 4350 #endif 4351 ) 4352 { 4353 /* Symbol is undefined in this segment, or we need to keep a 4354 reloc so that weak symbols can be overridden. */ 4355 int size = (fragP->fr_subtype & CODE16) ? 2 : 4; 4356 enum bfd_reloc_code_real reloc_type; 4357 unsigned char *opcode; 4358 int old_fr_fix; 4359 4360 if (fragP->fr_var != NO_RELOC) 4361 reloc_type = fragP->fr_var; 4362 else if (size == 2) 4363 reloc_type = BFD_RELOC_16_PCREL; 4364 else 4365 reloc_type = BFD_RELOC_32_PCREL; 4366 4367 old_fr_fix = fragP->fr_fix; 4368 opcode = (unsigned char *) fragP->fr_opcode; 4369 4370 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) 4371 { 4372 case UNCOND_JUMP: 4373 /* Make jmp (0xeb) a (d)word displacement jump. */ 4374 opcode[0] = 0xe9; 4375 fragP->fr_fix += size; 4376 fix_new (fragP, old_fr_fix, size, 4377 fragP->fr_symbol, 4378 fragP->fr_offset, 1, 4379 reloc_type); 4380 break; 4381 4382 case COND_JUMP86: 4383 if (size == 2 4384 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) 4385 { 4386 /* Negate the condition, and branch past an 4387 unconditional jump. */ 4388 opcode[0] ^= 1; 4389 opcode[1] = 3; 4390 /* Insert an unconditional jump. */ 4391 opcode[2] = 0xe9; 4392 /* We added two extra opcode bytes, and have a two byte 4393 offset. */ 4394 fragP->fr_fix += 2 + 2; 4395 fix_new (fragP, old_fr_fix + 2, 2, 4396 fragP->fr_symbol, 4397 fragP->fr_offset, 1, 4398 reloc_type); 4399 break; 4400 } 4401 /* Fall through. */ 4402 4403 case COND_JUMP: 4404 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) 4405 { 4406 fixS *fixP; 4407 4408 fragP->fr_fix += 1; 4409 fixP = fix_new (fragP, old_fr_fix, 1, 4410 fragP->fr_symbol, 4411 fragP->fr_offset, 1, 4412 BFD_RELOC_8_PCREL); 4413 fixP->fx_signed = 1; 4414 break; 4415 } 4416 4417 /* This changes the byte-displacement jump 0x7N 4418 to the (d)word-displacement jump 0x0f,0x8N. */ 4419 opcode[1] = opcode[0] + 0x10; 4420 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 4421 /* We've added an opcode byte. */ 4422 fragP->fr_fix += 1 + size; 4423 fix_new (fragP, old_fr_fix + 1, size, 4424 fragP->fr_symbol, 4425 fragP->fr_offset, 1, 4426 reloc_type); 4427 break; 4428 4429 default: 4430 BAD_CASE (fragP->fr_subtype); 4431 break; 4432 } 4433 frag_wane (fragP); 4434 return fragP->fr_fix - old_fr_fix; 4435 } 4436 4437 /* Guess size depending on current relax state. Initially the relax 4438 state will correspond to a short jump and we return 1, because 4439 the variable part of the frag (the branch offset) is one byte 4440 long. However, we can relax a section more than once and in that 4441 case we must either set fr_subtype back to the unrelaxed state, 4442 or return the value for the appropriate branch. */ 4443 return md_relax_table[fragP->fr_subtype].rlx_length; 4444 } 4445 4446 /* Called after relax() is finished. 4447 4448 In: Address of frag. 4449 fr_type == rs_machine_dependent. 4450 fr_subtype is what the address relaxed to. 4451 4452 Out: Any fixSs and constants are set up. 4453 Caller will turn frag into a ".space 0". */ 4454 4455 void 4456 md_convert_frag (abfd, sec, fragP) 4457 bfd *abfd ATTRIBUTE_UNUSED; 4458 segT sec ATTRIBUTE_UNUSED; 4459 fragS *fragP; 4460 { 4461 unsigned char *opcode; 4462 unsigned char *where_to_put_displacement = NULL; 4463 offsetT target_address; 4464 offsetT opcode_address; 4465 unsigned int extension = 0; 4466 offsetT displacement_from_opcode_start; 4467 4468 opcode = (unsigned char *) fragP->fr_opcode; 4469 4470 /* Address we want to reach in file space. */ 4471 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; 4472 4473 /* Address opcode resides at in file space. */ 4474 opcode_address = fragP->fr_address + fragP->fr_fix; 4475 4476 /* Displacement from opcode start to fill into instruction. */ 4477 displacement_from_opcode_start = target_address - opcode_address; 4478 4479 if ((fragP->fr_subtype & BIG) == 0) 4480 { 4481 /* Don't have to change opcode. */ 4482 extension = 1; /* 1 opcode + 1 displacement */ 4483 where_to_put_displacement = &opcode[1]; 4484 } 4485 else 4486 { 4487 if (no_cond_jump_promotion 4488 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) 4489 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required")); 4490 4491 switch (fragP->fr_subtype) 4492 { 4493 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): 4494 extension = 4; /* 1 opcode + 4 displacement */ 4495 opcode[0] = 0xe9; 4496 where_to_put_displacement = &opcode[1]; 4497 break; 4498 4499 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): 4500 extension = 2; /* 1 opcode + 2 displacement */ 4501 opcode[0] = 0xe9; 4502 where_to_put_displacement = &opcode[1]; 4503 break; 4504 4505 case ENCODE_RELAX_STATE (COND_JUMP, BIG): 4506 case ENCODE_RELAX_STATE (COND_JUMP86, BIG): 4507 extension = 5; /* 2 opcode + 4 displacement */ 4508 opcode[1] = opcode[0] + 0x10; 4509 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 4510 where_to_put_displacement = &opcode[2]; 4511 break; 4512 4513 case ENCODE_RELAX_STATE (COND_JUMP, BIG16): 4514 extension = 3; /* 2 opcode + 2 displacement */ 4515 opcode[1] = opcode[0] + 0x10; 4516 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; 4517 where_to_put_displacement = &opcode[2]; 4518 break; 4519 4520 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): 4521 extension = 4; 4522 opcode[0] ^= 1; 4523 opcode[1] = 3; 4524 opcode[2] = 0xe9; 4525 where_to_put_displacement = &opcode[3]; 4526 break; 4527 4528 default: 4529 BAD_CASE (fragP->fr_subtype); 4530 break; 4531 } 4532 } 4533 4534 /* Now put displacement after opcode. */ 4535 md_number_to_chars ((char *) where_to_put_displacement, 4536 (valueT) (displacement_from_opcode_start - extension), 4537 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); 4538 fragP->fr_fix += extension; 4539 } 4540 4541 /* Size of byte displacement jmp. */ 4542 int md_short_jump_size = 2; 4543 4544 /* Size of dword displacement jmp. */ 4545 int md_long_jump_size = 5; 4546 4547 /* Size of relocation record. */ 4548 const int md_reloc_size = 8; 4549 4550 void 4551 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) 4552 char *ptr; 4553 addressT from_addr, to_addr; 4554 fragS *frag ATTRIBUTE_UNUSED; 4555 symbolS *to_symbol ATTRIBUTE_UNUSED; 4556 { 4557 offsetT offset; 4558 4559 offset = to_addr - (from_addr + 2); 4560 /* Opcode for byte-disp jump. */ 4561 md_number_to_chars (ptr, (valueT) 0xeb, 1); 4562 md_number_to_chars (ptr + 1, (valueT) offset, 1); 4563 } 4564 4565 void 4566 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) 4567 char *ptr; 4568 addressT from_addr, to_addr; 4569 fragS *frag ATTRIBUTE_UNUSED; 4570 symbolS *to_symbol ATTRIBUTE_UNUSED; 4571 { 4572 offsetT offset; 4573 4574 offset = to_addr - (from_addr + 5); 4575 md_number_to_chars (ptr, (valueT) 0xe9, 1); 4576 md_number_to_chars (ptr + 1, (valueT) offset, 4); 4577 } 4578 4579 /* Apply a fixup (fixS) to segment data, once it has been determined 4580 by our caller that we have all the info we need to fix it up. 4581 4582 On the 386, immediates, displacements, and data pointers are all in 4583 the same (little-endian) format, so we don't need to care about which 4584 we are handling. */ 4585 4586 void 4587 md_apply_fix3 (fixP, valP, seg) 4588 /* The fix we're to put in. */ 4589 fixS *fixP; 4590 /* Pointer to the value of the bits. */ 4591 valueT *valP; 4592 /* Segment fix is from. */ 4593 segT seg ATTRIBUTE_UNUSED; 4594 { 4595 char *p = fixP->fx_where + fixP->fx_frag->fr_literal; 4596 valueT value = *valP; 4597 4598 #if !defined (TE_Mach) 4599 if (fixP->fx_pcrel) 4600 { 4601 switch (fixP->fx_r_type) 4602 { 4603 default: 4604 break; 4605 4606 case BFD_RELOC_32: 4607 fixP->fx_r_type = BFD_RELOC_32_PCREL; 4608 break; 4609 case BFD_RELOC_16: 4610 fixP->fx_r_type = BFD_RELOC_16_PCREL; 4611 break; 4612 case BFD_RELOC_8: 4613 fixP->fx_r_type = BFD_RELOC_8_PCREL; 4614 break; 4615 } 4616 } 4617 4618 if (fixP->fx_addsy != NULL 4619 && (fixP->fx_r_type == BFD_RELOC_32_PCREL 4620 || fixP->fx_r_type == BFD_RELOC_16_PCREL 4621 || fixP->fx_r_type == BFD_RELOC_8_PCREL) 4622 && !use_rela_relocations) 4623 { 4624 /* This is a hack. There should be a better way to handle this. 4625 This covers for the fact that bfd_install_relocation will 4626 subtract the current location (for partial_inplace, PC relative 4627 relocations); see more below. */ 4628 #ifndef OBJ_AOUT 4629 if (OUTPUT_FLAVOR == bfd_target_elf_flavour 4630 #ifdef TE_PE 4631 || OUTPUT_FLAVOR == bfd_target_coff_flavour 4632 #endif 4633 ) 4634 value += fixP->fx_where + fixP->fx_frag->fr_address; 4635 #endif 4636 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 4637 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 4638 { 4639 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); 4640 4641 if ((sym_seg == seg 4642 || (symbol_section_p (fixP->fx_addsy) 4643 && sym_seg != absolute_section)) 4644 && !generic_force_reloc (fixP)) 4645 { 4646 /* Yes, we add the values in twice. This is because 4647 bfd_install_relocation subtracts them out again. I think 4648 bfd_install_relocation is broken, but I don't dare change 4649 it. FIXME. */ 4650 value += fixP->fx_where + fixP->fx_frag->fr_address; 4651 } 4652 } 4653 #endif 4654 #if defined (OBJ_COFF) && defined (TE_PE) 4655 /* For some reason, the PE format does not store a section 4656 address offset for a PC relative symbol. */ 4657 if (S_GET_SEGMENT (fixP->fx_addsy) != seg) 4658 value += md_pcrel_from (fixP); 4659 #endif 4660 } 4661 4662 /* Fix a few things - the dynamic linker expects certain values here, 4663 and we must not disappoint it. */ 4664 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 4665 if (OUTPUT_FLAVOR == bfd_target_elf_flavour 4666 && fixP->fx_addsy) 4667 switch (fixP->fx_r_type) 4668 { 4669 case BFD_RELOC_386_PLT32: 4670 case BFD_RELOC_X86_64_PLT32: 4671 /* Make the jump instruction point to the address of the operand. At 4672 runtime we merely add the offset to the actual PLT entry. */ 4673 value = -4; 4674 break; 4675 4676 case BFD_RELOC_386_TLS_GD: 4677 case BFD_RELOC_386_TLS_LDM: 4678 case BFD_RELOC_386_TLS_IE_32: 4679 case BFD_RELOC_386_TLS_IE: 4680 case BFD_RELOC_386_TLS_GOTIE: 4681 case BFD_RELOC_X86_64_TLSGD: 4682 case BFD_RELOC_X86_64_TLSLD: 4683 case BFD_RELOC_X86_64_GOTTPOFF: 4684 value = 0; /* Fully resolved at runtime. No addend. */ 4685 /* Fallthrough */ 4686 case BFD_RELOC_386_TLS_LE: 4687 case BFD_RELOC_386_TLS_LDO_32: 4688 case BFD_RELOC_386_TLS_LE_32: 4689 case BFD_RELOC_X86_64_DTPOFF32: 4690 case BFD_RELOC_X86_64_TPOFF32: 4691 S_SET_THREAD_LOCAL (fixP->fx_addsy); 4692 break; 4693 4694 case BFD_RELOC_386_GOT32: 4695 case BFD_RELOC_X86_64_GOT32: 4696 value = 0; /* Fully resolved at runtime. No addend. */ 4697 break; 4698 4699 case BFD_RELOC_VTABLE_INHERIT: 4700 case BFD_RELOC_VTABLE_ENTRY: 4701 fixP->fx_done = 0; 4702 return; 4703 4704 default: 4705 break; 4706 } 4707 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ 4708 *valP = value; 4709 #endif /* !defined (TE_Mach) */ 4710 4711 /* Are we finished with this relocation now? */ 4712 if (fixP->fx_addsy == NULL) 4713 fixP->fx_done = 1; 4714 else if (use_rela_relocations) 4715 { 4716 fixP->fx_no_overflow = 1; 4717 /* Remember value for tc_gen_reloc. */ 4718 fixP->fx_addnumber = value; 4719 value = 0; 4720 } 4721 4722 md_number_to_chars (p, value, fixP->fx_size); 4723 } 4724 4725 #define MAX_LITTLENUMS 6 4726 4727 /* Turn the string pointed to by litP into a floating point constant 4728 of type TYPE, and emit the appropriate bytes. The number of 4729 LITTLENUMS emitted is stored in *SIZEP. An error message is 4730 returned, or NULL on OK. */ 4731 4732 char * 4733 md_atof (type, litP, sizeP) 4734 int type; 4735 char *litP; 4736 int *sizeP; 4737 { 4738 int prec; 4739 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 4740 LITTLENUM_TYPE *wordP; 4741 char *t; 4742 4743 switch (type) 4744 { 4745 case 'f': 4746 case 'F': 4747 prec = 2; 4748 break; 4749 4750 case 'd': 4751 case 'D': 4752 prec = 4; 4753 break; 4754 4755 case 'x': 4756 case 'X': 4757 prec = 5; 4758 break; 4759 4760 default: 4761 *sizeP = 0; 4762 return _("Bad call to md_atof ()"); 4763 } 4764 t = atof_ieee (input_line_pointer, type, words); 4765 if (t) 4766 input_line_pointer = t; 4767 4768 *sizeP = prec * sizeof (LITTLENUM_TYPE); 4769 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with 4770 the bigendian 386. */ 4771 for (wordP = words + prec - 1; prec--;) 4772 { 4773 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); 4774 litP += sizeof (LITTLENUM_TYPE); 4775 } 4776 return 0; 4777 } 4778 4779 char output_invalid_buf[8]; 4780 4781 static char * 4782 output_invalid (c) 4783 int c; 4784 { 4785 if (ISPRINT (c)) 4786 sprintf (output_invalid_buf, "'%c'", c); 4787 else 4788 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); 4789 return output_invalid_buf; 4790 } 4791 4792 /* REG_STRING starts *before* REGISTER_PREFIX. */ 4793 4794 static const reg_entry * 4795 parse_register (reg_string, end_op) 4796 char *reg_string; 4797 char **end_op; 4798 { 4799 char *s = reg_string; 4800 char *p; 4801 char reg_name_given[MAX_REG_NAME_SIZE + 1]; 4802 const reg_entry *r; 4803 4804 /* Skip possible REGISTER_PREFIX and possible whitespace. */ 4805 if (*s == REGISTER_PREFIX) 4806 ++s; 4807 4808 if (is_space_char (*s)) 4809 ++s; 4810 4811 p = reg_name_given; 4812 while ((*p++ = register_chars[(unsigned char) *s]) != '\0') 4813 { 4814 if (p >= reg_name_given + MAX_REG_NAME_SIZE) 4815 return (const reg_entry *) NULL; 4816 s++; 4817 } 4818 4819 /* For naked regs, make sure that we are not dealing with an identifier. 4820 This prevents confusing an identifier like `eax_var' with register 4821 `eax'. */ 4822 if (allow_naked_reg && identifier_chars[(unsigned char) *s]) 4823 return (const reg_entry *) NULL; 4824 4825 *end_op = s; 4826 4827 r = (const reg_entry *) hash_find (reg_hash, reg_name_given); 4828 4829 /* Handle floating point regs, allowing spaces in the (i) part. */ 4830 if (r == i386_regtab /* %st is first entry of table */) 4831 { 4832 if (is_space_char (*s)) 4833 ++s; 4834 if (*s == '(') 4835 { 4836 ++s; 4837 if (is_space_char (*s)) 4838 ++s; 4839 if (*s >= '0' && *s <= '7') 4840 { 4841 r = &i386_float_regtab[*s - '0']; 4842 ++s; 4843 if (is_space_char (*s)) 4844 ++s; 4845 if (*s == ')') 4846 { 4847 *end_op = s + 1; 4848 return r; 4849 } 4850 } 4851 /* We have "%st(" then garbage. */ 4852 return (const reg_entry *) NULL; 4853 } 4854 } 4855 4856 if (r != NULL 4857 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0 4858 && flag_code != CODE_64BIT) 4859 return (const reg_entry *) NULL; 4860 4861 return r; 4862 } 4863 4864 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 4865 const char *md_shortopts = "kVQ:sqn"; 4866 #else 4867 const char *md_shortopts = "qn"; 4868 #endif 4869 4870 struct option md_longopts[] = { 4871 #define OPTION_32 (OPTION_MD_BASE + 0) 4872 {"32", no_argument, NULL, OPTION_32}, 4873 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 4874 #define OPTION_64 (OPTION_MD_BASE + 1) 4875 {"64", no_argument, NULL, OPTION_64}, 4876 #endif 4877 {NULL, no_argument, NULL, 0} 4878 }; 4879 size_t md_longopts_size = sizeof (md_longopts); 4880 4881 int 4882 md_parse_option (c, arg) 4883 int c; 4884 char *arg ATTRIBUTE_UNUSED; 4885 { 4886 switch (c) 4887 { 4888 case 'n': 4889 optimize_align_code = 0; 4890 break; 4891 4892 case 'q': 4893 quiet_warnings = 1; 4894 break; 4895 4896 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 4897 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section 4898 should be emitted or not. FIXME: Not implemented. */ 4899 case 'Q': 4900 break; 4901 4902 /* -V: SVR4 argument to print version ID. */ 4903 case 'V': 4904 print_version_id (); 4905 break; 4906 4907 /* -k: Ignore for FreeBSD compatibility. */ 4908 case 'k': 4909 break; 4910 4911 case 's': 4912 /* -s: On i386 Solaris, this tells the native assembler to use 4913 .stab instead of .stab.excl. We always use .stab anyhow. */ 4914 break; 4915 4916 case OPTION_64: 4917 { 4918 const char **list, **l; 4919 4920 list = bfd_target_list (); 4921 for (l = list; *l != NULL; l++) 4922 if (strcmp (*l, "elf64-x86-64") == 0) 4923 { 4924 default_arch = "x86_64"; 4925 break; 4926 } 4927 if (*l == NULL) 4928 as_fatal (_("No compiled in support for x86_64")); 4929 free (list); 4930 } 4931 break; 4932 #endif 4933 4934 case OPTION_32: 4935 default_arch = "i386"; 4936 break; 4937 4938 default: 4939 return 0; 4940 } 4941 return 1; 4942 } 4943 4944 void 4945 md_show_usage (stream) 4946 FILE *stream; 4947 { 4948 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) 4949 fprintf (stream, _("\ 4950 -Q ignored\n\ 4951 -V print assembler version number\n\ 4952 -k ignored\n\ 4953 -n Do not optimize code alignment\n\ 4954 -q quieten some warnings\n\ 4955 -s ignored\n")); 4956 #else 4957 fprintf (stream, _("\ 4958 -n Do not optimize code alignment\n\ 4959 -q quieten some warnings\n")); 4960 #endif 4961 } 4962 4963 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ 4964 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 4965 4966 /* Pick the target format to use. */ 4967 4968 const char * 4969 i386_target_format () 4970 { 4971 if (!strcmp (default_arch, "x86_64")) 4972 set_code_flag (CODE_64BIT); 4973 else if (!strcmp (default_arch, "i386")) 4974 set_code_flag (CODE_32BIT); 4975 else 4976 as_fatal (_("Unknown architecture")); 4977 switch (OUTPUT_FLAVOR) 4978 { 4979 #ifdef OBJ_MAYBE_AOUT 4980 case bfd_target_aout_flavour: 4981 return AOUT_TARGET_FORMAT; 4982 #endif 4983 #ifdef OBJ_MAYBE_COFF 4984 case bfd_target_coff_flavour: 4985 return "coff-i386"; 4986 #endif 4987 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) 4988 case bfd_target_elf_flavour: 4989 { 4990 if (flag_code == CODE_64BIT) 4991 use_rela_relocations = 1; 4992 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT; 4993 } 4994 #endif 4995 default: 4996 abort (); 4997 return NULL; 4998 } 4999 } 5000 5001 #endif /* OBJ_MAYBE_ more than one */ 5002 5003 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) 5004 void i386_elf_emit_arch_note () 5005 { 5006 if (OUTPUT_FLAVOR == bfd_target_elf_flavour 5007 && cpu_arch_name != NULL) 5008 { 5009 char *p; 5010 asection *seg = now_seg; 5011 subsegT subseg = now_subseg; 5012 Elf_Internal_Note i_note; 5013 Elf_External_Note e_note; 5014 asection *note_secp; 5015 int len; 5016 5017 /* Create the .note section. */ 5018 note_secp = subseg_new (".note", 0); 5019 bfd_set_section_flags (stdoutput, 5020 note_secp, 5021 SEC_HAS_CONTENTS | SEC_READONLY); 5022 5023 /* Process the arch string. */ 5024 len = strlen (cpu_arch_name); 5025 5026 i_note.namesz = len + 1; 5027 i_note.descsz = 0; 5028 i_note.type = NT_ARCH; 5029 p = frag_more (sizeof (e_note.namesz)); 5030 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); 5031 p = frag_more (sizeof (e_note.descsz)); 5032 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); 5033 p = frag_more (sizeof (e_note.type)); 5034 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); 5035 p = frag_more (len + 1); 5036 strcpy (p, cpu_arch_name); 5037 5038 frag_align (2, 0, 0); 5039 5040 subseg_set (seg, subseg); 5041 } 5042 } 5043 #endif 5044 5045 symbolS * 5046 md_undefined_symbol (name) 5047 char *name; 5048 { 5049 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] 5050 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] 5051 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] 5052 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) 5053 { 5054 if (!GOT_symbol) 5055 { 5056 if (symbol_find (name)) 5057 as_bad (_("GOT already in symbol table")); 5058 GOT_symbol = symbol_new (name, undefined_section, 5059 (valueT) 0, &zero_address_frag); 5060 }; 5061 return GOT_symbol; 5062 } 5063 return 0; 5064 } 5065 5066 /* Round up a section size to the appropriate boundary. */ 5067 5068 valueT 5069 md_section_align (segment, size) 5070 segT segment ATTRIBUTE_UNUSED; 5071 valueT size; 5072 { 5073 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) 5074 if (OUTPUT_FLAVOR == bfd_target_aout_flavour) 5075 { 5076 /* For a.out, force the section size to be aligned. If we don't do 5077 this, BFD will align it for us, but it will not write out the 5078 final bytes of the section. This may be a bug in BFD, but it is 5079 easier to fix it here since that is how the other a.out targets 5080 work. */ 5081 int align; 5082 5083 align = bfd_get_section_alignment (stdoutput, segment); 5084 size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); 5085 } 5086 #endif 5087 5088 return size; 5089 } 5090 5091 /* On the i386, PC-relative offsets are relative to the start of the 5092 next instruction. That is, the address of the offset, plus its 5093 size, since the offset is always the last part of the insn. */ 5094 5095 long 5096 md_pcrel_from (fixP) 5097 fixS *fixP; 5098 { 5099 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; 5100 } 5101 5102 #ifndef I386COFF 5103 5104 static void 5105 s_bss (ignore) 5106 int ignore ATTRIBUTE_UNUSED; 5107 { 5108 int temp; 5109 5110 temp = get_absolute_expression (); 5111 subseg_set (bss_section, (subsegT) temp); 5112 demand_empty_rest_of_line (); 5113 } 5114 5115 #endif 5116 5117 void 5118 i386_validate_fix (fixp) 5119 fixS *fixp; 5120 { 5121 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) 5122 { 5123 /* GOTOFF relocation are nonsense in 64bit mode. */ 5124 if (fixp->fx_r_type == BFD_RELOC_32_PCREL) 5125 { 5126 if (flag_code != CODE_64BIT) 5127 abort (); 5128 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; 5129 } 5130 else 5131 { 5132 if (flag_code == CODE_64BIT) 5133 abort (); 5134 fixp->fx_r_type = BFD_RELOC_386_GOTOFF; 5135 } 5136 fixp->fx_subsy = 0; 5137 } 5138 } 5139 5140 arelent * 5141 tc_gen_reloc (section, fixp) 5142 asection *section ATTRIBUTE_UNUSED; 5143 fixS *fixp; 5144 { 5145 arelent *rel; 5146 bfd_reloc_code_real_type code; 5147 5148 switch (fixp->fx_r_type) 5149 { 5150 case BFD_RELOC_X86_64_PLT32: 5151 case BFD_RELOC_X86_64_GOT32: 5152 case BFD_RELOC_X86_64_GOTPCREL: 5153 case BFD_RELOC_386_PLT32: 5154 case BFD_RELOC_386_GOT32: 5155 case BFD_RELOC_386_GOTOFF: 5156 case BFD_RELOC_386_GOTPC: 5157 case BFD_RELOC_386_TLS_GD: 5158 case BFD_RELOC_386_TLS_LDM: 5159 case BFD_RELOC_386_TLS_LDO_32: 5160 case BFD_RELOC_386_TLS_IE_32: 5161 case BFD_RELOC_386_TLS_IE: 5162 case BFD_RELOC_386_TLS_GOTIE: 5163 case BFD_RELOC_386_TLS_LE_32: 5164 case BFD_RELOC_386_TLS_LE: 5165 case BFD_RELOC_X86_64_32S: 5166 case BFD_RELOC_X86_64_TLSGD: 5167 case BFD_RELOC_X86_64_TLSLD: 5168 case BFD_RELOC_X86_64_DTPOFF32: 5169 case BFD_RELOC_X86_64_GOTTPOFF: 5170 case BFD_RELOC_X86_64_TPOFF32: 5171 case BFD_RELOC_RVA: 5172 case BFD_RELOC_VTABLE_ENTRY: 5173 case BFD_RELOC_VTABLE_INHERIT: 5174 code = fixp->fx_r_type; 5175 break; 5176 default: 5177 if (fixp->fx_pcrel) 5178 { 5179 switch (fixp->fx_size) 5180 { 5181 default: 5182 as_bad_where (fixp->fx_file, fixp->fx_line, 5183 _("can not do %d byte pc-relative relocation"), 5184 fixp->fx_size); 5185 code = BFD_RELOC_32_PCREL; 5186 break; 5187 case 1: code = BFD_RELOC_8_PCREL; break; 5188 case 2: code = BFD_RELOC_16_PCREL; break; 5189 case 4: code = BFD_RELOC_32_PCREL; break; 5190 } 5191 } 5192 else 5193 { 5194 switch (fixp->fx_size) 5195 { 5196 default: 5197 as_bad_where (fixp->fx_file, fixp->fx_line, 5198 _("can not do %d byte relocation"), 5199 fixp->fx_size); 5200 code = BFD_RELOC_32; 5201 break; 5202 case 1: code = BFD_RELOC_8; break; 5203 case 2: code = BFD_RELOC_16; break; 5204 case 4: code = BFD_RELOC_32; break; 5205 #ifdef BFD64 5206 case 8: code = BFD_RELOC_64; break; 5207 #endif 5208 } 5209 } 5210 break; 5211 } 5212 5213 if (code == BFD_RELOC_32 5214 && GOT_symbol 5215 && fixp->fx_addsy == GOT_symbol) 5216 { 5217 /* We don't support GOTPC on 64bit targets. */ 5218 if (flag_code == CODE_64BIT) 5219 abort (); 5220 code = BFD_RELOC_386_GOTPC; 5221 } 5222 5223 rel = (arelent *) xmalloc (sizeof (arelent)); 5224 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 5225 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 5226 5227 rel->address = fixp->fx_frag->fr_address + fixp->fx_where; 5228 if (!use_rela_relocations) 5229 { 5230 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the 5231 vtable entry to be used in the relocation's section offset. */ 5232 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 5233 rel->address = fixp->fx_offset; 5234 5235 rel->addend = 0; 5236 } 5237 /* Use the rela in 64bit mode. */ 5238 else 5239 { 5240 if (!fixp->fx_pcrel) 5241 rel->addend = fixp->fx_offset; 5242 else 5243 switch (code) 5244 { 5245 case BFD_RELOC_X86_64_PLT32: 5246 case BFD_RELOC_X86_64_GOT32: 5247 case BFD_RELOC_X86_64_GOTPCREL: 5248 case BFD_RELOC_X86_64_TLSGD: 5249 case BFD_RELOC_X86_64_TLSLD: 5250 case BFD_RELOC_X86_64_GOTTPOFF: 5251 rel->addend = fixp->fx_offset - fixp->fx_size; 5252 break; 5253 default: 5254 rel->addend = (section->vma 5255 - fixp->fx_size 5256 + fixp->fx_addnumber 5257 + md_pcrel_from (fixp)); 5258 break; 5259 } 5260 } 5261 5262 rel->howto = bfd_reloc_type_lookup (stdoutput, code); 5263 if (rel->howto == NULL) 5264 { 5265 as_bad_where (fixp->fx_file, fixp->fx_line, 5266 _("cannot represent relocation type %s"), 5267 bfd_get_reloc_code_name (code)); 5268 /* Set howto to a garbage value so that we can keep going. */ 5269 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); 5270 assert (rel->howto != NULL); 5271 } 5272 5273 return rel; 5274 } 5275 5276 5277 /* Parse operands using Intel syntax. This implements a recursive descent 5278 parser based on the BNF grammar published in Appendix B of the MASM 6.1 5279 Programmer's Guide. 5280 5281 FIXME: We do not recognize the full operand grammar defined in the MASM 5282 documentation. In particular, all the structure/union and 5283 high-level macro operands are missing. 5284 5285 Uppercase words are terminals, lower case words are non-terminals. 5286 Objects surrounded by double brackets '[[' ']]' are optional. Vertical 5287 bars '|' denote choices. Most grammar productions are implemented in 5288 functions called 'intel_<production>'. 5289 5290 Initial production is 'expr'. 5291 5292 addOp + | - 5293 5294 alpha [a-zA-Z] 5295 5296 byteRegister AL | AH | BL | BH | CL | CH | DL | DH 5297 5298 constant digits [[ radixOverride ]] 5299 5300 dataType BYTE | WORD | DWORD | QWORD | XWORD 5301 5302 digits decdigit 5303 | digits decdigit 5304 | digits hexdigit 5305 5306 decdigit [0-9] 5307 5308 e05 e05 addOp e06 5309 | e06 5310 5311 e06 e06 mulOp e09 5312 | e09 5313 5314 e09 OFFSET e10 5315 | e09 PTR e10 5316 | e09 : e10 5317 | e10 5318 5319 e10 e10 [ expr ] 5320 | e11 5321 5322 e11 ( expr ) 5323 | [ expr ] 5324 | constant 5325 | dataType 5326 | id 5327 | $ 5328 | register 5329 5330 => expr SHORT e05 5331 | e05 5332 5333 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX 5334 | BP | EBP | SP | ESP | DI | EDI | SI | ESI 5335 5336 hexdigit a | b | c | d | e | f 5337 | A | B | C | D | E | F 5338 5339 id alpha 5340 | id alpha 5341 | id decdigit 5342 5343 mulOp * | / | MOD 5344 5345 quote " | ' 5346 5347 register specialRegister 5348 | gpRegister 5349 | byteRegister 5350 5351 segmentRegister CS | DS | ES | FS | GS | SS 5352 5353 specialRegister CR0 | CR2 | CR3 5354 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 5355 | TR3 | TR4 | TR5 | TR6 | TR7 5356 5357 We simplify the grammar in obvious places (e.g., register parsing is 5358 done by calling parse_register) and eliminate immediate left recursion 5359 to implement a recursive-descent parser. 5360 5361 expr SHORT e05 5362 | e05 5363 5364 e05 e06 e05' 5365 5366 e05' addOp e06 e05' 5367 | Empty 5368 5369 e06 e09 e06' 5370 5371 e06' mulOp e09 e06' 5372 | Empty 5373 5374 e09 OFFSET e10 e09' 5375 | e10 e09' 5376 5377 e09' PTR e10 e09' 5378 | : e10 e09' 5379 | Empty 5380 5381 e10 e11 e10' 5382 5383 e10' [ expr ] e10' 5384 | Empty 5385 5386 e11 ( expr ) 5387 | [ expr ] 5388 | BYTE 5389 | WORD 5390 | DWORD 5391 | QWORD 5392 | XWORD 5393 | . 5394 | $ 5395 | register 5396 | id 5397 | constant */ 5398 5399 /* Parsing structure for the intel syntax parser. Used to implement the 5400 semantic actions for the operand grammar. */ 5401 struct intel_parser_s 5402 { 5403 char *op_string; /* The string being parsed. */ 5404 int got_a_float; /* Whether the operand is a float. */ 5405 int op_modifier; /* Operand modifier. */ 5406 int is_mem; /* 1 if operand is memory reference. */ 5407 const reg_entry *reg; /* Last register reference found. */ 5408 char *disp; /* Displacement string being built. */ 5409 }; 5410 5411 static struct intel_parser_s intel_parser; 5412 5413 /* Token structure for parsing intel syntax. */ 5414 struct intel_token 5415 { 5416 int code; /* Token code. */ 5417 const reg_entry *reg; /* Register entry for register tokens. */ 5418 char *str; /* String representation. */ 5419 }; 5420 5421 static struct intel_token cur_token, prev_token; 5422 5423 /* Token codes for the intel parser. Since T_SHORT is already used 5424 by COFF, undefine it first to prevent a warning. */ 5425 #define T_NIL -1 5426 #define T_CONST 1 5427 #define T_REG 2 5428 #define T_BYTE 3 5429 #define T_WORD 4 5430 #define T_DWORD 5 5431 #define T_QWORD 6 5432 #define T_XWORD 7 5433 #undef T_SHORT 5434 #define T_SHORT 8 5435 #define T_OFFSET 9 5436 #define T_PTR 10 5437 #define T_ID 11 5438 5439 /* Prototypes for intel parser functions. */ 5440 static int intel_match_token PARAMS ((int code)); 5441 static void intel_get_token PARAMS ((void)); 5442 static void intel_putback_token PARAMS ((void)); 5443 static int intel_expr PARAMS ((void)); 5444 static int intel_e05 PARAMS ((void)); 5445 static int intel_e05_1 PARAMS ((void)); 5446 static int intel_e06 PARAMS ((void)); 5447 static int intel_e06_1 PARAMS ((void)); 5448 static int intel_e09 PARAMS ((void)); 5449 static int intel_e09_1 PARAMS ((void)); 5450 static int intel_e10 PARAMS ((void)); 5451 static int intel_e10_1 PARAMS ((void)); 5452 static int intel_e11 PARAMS ((void)); 5453 5454 static int 5455 i386_intel_operand (operand_string, got_a_float) 5456 char *operand_string; 5457 int got_a_float; 5458 { 5459 int ret; 5460 char *p; 5461 5462 /* Initialize token holders. */ 5463 cur_token.code = prev_token.code = T_NIL; 5464 cur_token.reg = prev_token.reg = NULL; 5465 cur_token.str = prev_token.str = NULL; 5466 5467 /* Initialize parser structure. */ 5468 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1); 5469 if (p == NULL) 5470 abort (); 5471 strcpy (intel_parser.op_string, operand_string); 5472 intel_parser.got_a_float = got_a_float; 5473 intel_parser.op_modifier = -1; 5474 intel_parser.is_mem = 0; 5475 intel_parser.reg = NULL; 5476 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1); 5477 if (intel_parser.disp == NULL) 5478 abort (); 5479 intel_parser.disp[0] = '\0'; 5480 5481 /* Read the first token and start the parser. */ 5482 intel_get_token (); 5483 ret = intel_expr (); 5484 5485 if (ret) 5486 { 5487 /* If we found a memory reference, hand it over to i386_displacement 5488 to fill in the rest of the operand fields. */ 5489 if (intel_parser.is_mem) 5490 { 5491 if ((i.mem_operands == 1 5492 && (current_templates->start->opcode_modifier & IsString) == 0) 5493 || i.mem_operands == 2) 5494 { 5495 as_bad (_("too many memory references for '%s'"), 5496 current_templates->start->name); 5497 ret = 0; 5498 } 5499 else 5500 { 5501 char *s = intel_parser.disp; 5502 i.mem_operands++; 5503 5504 /* Add the displacement expression. */ 5505 if (*s != '\0') 5506 ret = i386_displacement (s, s + strlen (s)); 5507 if (ret) 5508 ret = i386_index_check (operand_string); 5509 } 5510 } 5511 5512 /* Constant and OFFSET expressions are handled by i386_immediate. */ 5513 else if (intel_parser.op_modifier == OFFSET_FLAT 5514 || intel_parser.reg == NULL) 5515 ret = i386_immediate (intel_parser.disp); 5516 } 5517 5518 free (p); 5519 free (intel_parser.disp); 5520 5521 return ret; 5522 } 5523 5524 /* expr SHORT e05 5525 | e05 */ 5526 static int 5527 intel_expr () 5528 { 5529 /* expr SHORT e05 */ 5530 if (cur_token.code == T_SHORT) 5531 { 5532 intel_parser.op_modifier = SHORT; 5533 intel_match_token (T_SHORT); 5534 5535 return (intel_e05 ()); 5536 } 5537 5538 /* expr e05 */ 5539 else 5540 return intel_e05 (); 5541 } 5542 5543 /* e05 e06 e05' 5544 5545 e05' addOp e06 e05' 5546 | Empty */ 5547 static int 5548 intel_e05 () 5549 { 5550 return (intel_e06 () && intel_e05_1 ()); 5551 } 5552 5553 static int 5554 intel_e05_1 () 5555 { 5556 /* e05' addOp e06 e05' */ 5557 if (cur_token.code == '+' || cur_token.code == '-') 5558 { 5559 strcat (intel_parser.disp, cur_token.str); 5560 intel_match_token (cur_token.code); 5561 5562 return (intel_e06 () && intel_e05_1 ()); 5563 } 5564 5565 /* e05' Empty */ 5566 else 5567 return 1; 5568 } 5569 5570 /* e06 e09 e06' 5571 5572 e06' mulOp e09 e06' 5573 | Empty */ 5574 static int 5575 intel_e06 () 5576 { 5577 return (intel_e09 () && intel_e06_1 ()); 5578 } 5579 5580 static int 5581 intel_e06_1 () 5582 { 5583 /* e06' mulOp e09 e06' */ 5584 if (cur_token.code == '*' || cur_token.code == '/') 5585 { 5586 strcat (intel_parser.disp, cur_token.str); 5587 intel_match_token (cur_token.code); 5588 5589 return (intel_e09 () && intel_e06_1 ()); 5590 } 5591 5592 /* e06' Empty */ 5593 else 5594 return 1; 5595 } 5596 5597 /* e09 OFFSET e10 e09' 5598 | e10 e09' 5599 5600 e09' PTR e10 e09' 5601 | : e10 e09' 5602 | Empty */ 5603 static int 5604 intel_e09 () 5605 { 5606 /* e09 OFFSET e10 e09' */ 5607 if (cur_token.code == T_OFFSET) 5608 { 5609 intel_parser.is_mem = 0; 5610 intel_parser.op_modifier = OFFSET_FLAT; 5611 intel_match_token (T_OFFSET); 5612 5613 return (intel_e10 () && intel_e09_1 ()); 5614 } 5615 5616 /* e09 e10 e09' */ 5617 else 5618 return (intel_e10 () && intel_e09_1 ()); 5619 } 5620 5621 static int 5622 intel_e09_1 () 5623 { 5624 /* e09' PTR e10 e09' */ 5625 if (cur_token.code == T_PTR) 5626 { 5627 if (prev_token.code == T_BYTE) 5628 i.suffix = BYTE_MNEM_SUFFIX; 5629 5630 else if (prev_token.code == T_WORD) 5631 { 5632 if (intel_parser.got_a_float == 2) /* "fi..." */ 5633 i.suffix = SHORT_MNEM_SUFFIX; 5634 else 5635 i.suffix = WORD_MNEM_SUFFIX; 5636 } 5637 5638 else if (prev_token.code == T_DWORD) 5639 { 5640 if (intel_parser.got_a_float == 1) /* "f..." */ 5641 i.suffix = SHORT_MNEM_SUFFIX; 5642 else 5643 i.suffix = LONG_MNEM_SUFFIX; 5644 } 5645 5646 else if (prev_token.code == T_QWORD) 5647 { 5648 if (intel_parser.got_a_float == 1) /* "f..." */ 5649 i.suffix = LONG_MNEM_SUFFIX; 5650 else 5651 i.suffix = QWORD_MNEM_SUFFIX; 5652 } 5653 5654 else if (prev_token.code == T_XWORD) 5655 i.suffix = LONG_DOUBLE_MNEM_SUFFIX; 5656 5657 else 5658 { 5659 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str); 5660 return 0; 5661 } 5662 5663 intel_match_token (T_PTR); 5664 5665 return (intel_e10 () && intel_e09_1 ()); 5666 } 5667 5668 /* e09 : e10 e09' */ 5669 else if (cur_token.code == ':') 5670 { 5671 /* Mark as a memory operand only if it's not already known to be an 5672 offset expression. */ 5673 if (intel_parser.op_modifier != OFFSET_FLAT) 5674 intel_parser.is_mem = 1; 5675 5676 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ()); 5677 } 5678 5679 /* e09' Empty */ 5680 else 5681 return 1; 5682 } 5683 5684 /* e10 e11 e10' 5685 5686 e10' [ expr ] e10' 5687 | Empty */ 5688 static int 5689 intel_e10 () 5690 { 5691 return (intel_e11 () && intel_e10_1 ()); 5692 } 5693 5694 static int 5695 intel_e10_1 () 5696 { 5697 /* e10' [ expr ] e10' */ 5698 if (cur_token.code == '[') 5699 { 5700 intel_match_token ('['); 5701 5702 /* Mark as a memory operand only if it's not already known to be an 5703 offset expression. If it's an offset expression, we need to keep 5704 the brace in. */ 5705 if (intel_parser.op_modifier != OFFSET_FLAT) 5706 intel_parser.is_mem = 1; 5707 else 5708 strcat (intel_parser.disp, "["); 5709 5710 /* Add a '+' to the displacement string if necessary. */ 5711 if (*intel_parser.disp != '\0' 5712 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') 5713 strcat (intel_parser.disp, "+"); 5714 5715 if (intel_expr () && intel_match_token (']')) 5716 { 5717 /* Preserve brackets when the operand is an offset expression. */ 5718 if (intel_parser.op_modifier == OFFSET_FLAT) 5719 strcat (intel_parser.disp, "]"); 5720 5721 return intel_e10_1 (); 5722 } 5723 else 5724 return 0; 5725 } 5726 5727 /* e10' Empty */ 5728 else 5729 return 1; 5730 } 5731 5732 /* e11 ( expr ) 5733 | [ expr ] 5734 | BYTE 5735 | WORD 5736 | DWORD 5737 | QWORD 5738 | XWORD 5739 | $ 5740 | . 5741 | register 5742 | id 5743 | constant */ 5744 static int 5745 intel_e11 () 5746 { 5747 /* e11 ( expr ) */ 5748 if (cur_token.code == '(') 5749 { 5750 intel_match_token ('('); 5751 strcat (intel_parser.disp, "("); 5752 5753 if (intel_expr () && intel_match_token (')')) 5754 { 5755 strcat (intel_parser.disp, ")"); 5756 return 1; 5757 } 5758 else 5759 return 0; 5760 } 5761 5762 /* e11 [ expr ] */ 5763 else if (cur_token.code == '[') 5764 { 5765 intel_match_token ('['); 5766 5767 /* Mark as a memory operand only if it's not already known to be an 5768 offset expression. If it's an offset expression, we need to keep 5769 the brace in. */ 5770 if (intel_parser.op_modifier != OFFSET_FLAT) 5771 intel_parser.is_mem = 1; 5772 else 5773 strcat (intel_parser.disp, "["); 5774 5775 /* Operands for jump/call inside brackets denote absolute addresses. */ 5776 if (current_templates->start->opcode_modifier & Jump 5777 || current_templates->start->opcode_modifier & JumpDword 5778 || current_templates->start->opcode_modifier & JumpByte 5779 || current_templates->start->opcode_modifier & JumpInterSegment) 5780 i.types[this_operand] |= JumpAbsolute; 5781 5782 /* Add a '+' to the displacement string if necessary. */ 5783 if (*intel_parser.disp != '\0' 5784 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') 5785 strcat (intel_parser.disp, "+"); 5786 5787 if (intel_expr () && intel_match_token (']')) 5788 { 5789 /* Preserve brackets when the operand is an offset expression. */ 5790 if (intel_parser.op_modifier == OFFSET_FLAT) 5791 strcat (intel_parser.disp, "]"); 5792 5793 return 1; 5794 } 5795 else 5796 return 0; 5797 } 5798 5799 /* e11 BYTE 5800 | WORD 5801 | DWORD 5802 | QWORD 5803 | XWORD */ 5804 else if (cur_token.code == T_BYTE 5805 || cur_token.code == T_WORD 5806 || cur_token.code == T_DWORD 5807 || cur_token.code == T_QWORD 5808 || cur_token.code == T_XWORD) 5809 { 5810 intel_match_token (cur_token.code); 5811 5812 return 1; 5813 } 5814 5815 /* e11 $ 5816 | . */ 5817 else if (cur_token.code == '$' || cur_token.code == '.') 5818 { 5819 strcat (intel_parser.disp, cur_token.str); 5820 intel_match_token (cur_token.code); 5821 5822 /* Mark as a memory operand only if it's not already known to be an 5823 offset expression. */ 5824 if (intel_parser.op_modifier != OFFSET_FLAT) 5825 intel_parser.is_mem = 1; 5826 5827 return 1; 5828 } 5829 5830 /* e11 register */ 5831 else if (cur_token.code == T_REG) 5832 { 5833 const reg_entry *reg = intel_parser.reg = cur_token.reg; 5834 5835 intel_match_token (T_REG); 5836 5837 /* Check for segment change. */ 5838 if (cur_token.code == ':') 5839 { 5840 if (reg->reg_type & (SReg2 | SReg3)) 5841 { 5842 switch (reg->reg_num) 5843 { 5844 case 0: 5845 i.seg[i.mem_operands] = &es; 5846 break; 5847 case 1: 5848 i.seg[i.mem_operands] = &cs; 5849 break; 5850 case 2: 5851 i.seg[i.mem_operands] = &ss; 5852 break; 5853 case 3: 5854 i.seg[i.mem_operands] = &ds; 5855 break; 5856 case 4: 5857 i.seg[i.mem_operands] = &fs; 5858 break; 5859 case 5: 5860 i.seg[i.mem_operands] = &gs; 5861 break; 5862 } 5863 } 5864 else 5865 { 5866 as_bad (_("`%s' is not a valid segment register"), reg->reg_name); 5867 return 0; 5868 } 5869 } 5870 5871 /* Not a segment register. Check for register scaling. */ 5872 else if (cur_token.code == '*') 5873 { 5874 if (!intel_parser.is_mem) 5875 { 5876 as_bad (_("Register scaling only allowed in memory operands.")); 5877 return 0; 5878 } 5879 5880 /* What follows must be a valid scale. */ 5881 if (intel_match_token ('*') 5882 && strchr ("01248", *cur_token.str)) 5883 { 5884 i.index_reg = reg; 5885 i.types[this_operand] |= BaseIndex; 5886 5887 /* Set the scale after setting the register (otherwise, 5888 i386_scale will complain) */ 5889 i386_scale (cur_token.str); 5890 intel_match_token (T_CONST); 5891 } 5892 else 5893 { 5894 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), 5895 cur_token.str); 5896 return 0; 5897 } 5898 } 5899 5900 /* No scaling. If this is a memory operand, the register is either a 5901 base register (first occurrence) or an index register (second 5902 occurrence). */ 5903 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3))) 5904 { 5905 if (i.base_reg && i.index_reg) 5906 { 5907 as_bad (_("Too many register references in memory operand.\n")); 5908 return 0; 5909 } 5910 5911 if (i.base_reg == NULL) 5912 i.base_reg = reg; 5913 else 5914 i.index_reg = reg; 5915 5916 i.types[this_operand] |= BaseIndex; 5917 } 5918 5919 /* Offset modifier. Add the register to the displacement string to be 5920 parsed as an immediate expression after we're done. */ 5921 else if (intel_parser.op_modifier == OFFSET_FLAT) 5922 strcat (intel_parser.disp, reg->reg_name); 5923 5924 /* It's neither base nor index nor offset. */ 5925 else 5926 { 5927 i.types[this_operand] |= reg->reg_type & ~BaseIndex; 5928 i.op[this_operand].regs = reg; 5929 i.reg_operands++; 5930 } 5931 5932 /* Since registers are not part of the displacement string (except 5933 when we're parsing offset operands), we may need to remove any 5934 preceding '+' from the displacement string. */ 5935 if (*intel_parser.disp != '\0' 5936 && intel_parser.op_modifier != OFFSET_FLAT) 5937 { 5938 char *s = intel_parser.disp; 5939 s += strlen (s) - 1; 5940 if (*s == '+') 5941 *s = '\0'; 5942 } 5943 5944 return 1; 5945 } 5946 5947 /* e11 id */ 5948 else if (cur_token.code == T_ID) 5949 { 5950 /* Add the identifier to the displacement string. */ 5951 strcat (intel_parser.disp, cur_token.str); 5952 intel_match_token (T_ID); 5953 5954 /* The identifier represents a memory reference only if it's not 5955 preceded by an offset modifier. */ 5956 if (intel_parser.op_modifier != OFFSET_FLAT) 5957 intel_parser.is_mem = 1; 5958 5959 return 1; 5960 } 5961 5962 /* e11 constant */ 5963 else if (cur_token.code == T_CONST 5964 || cur_token.code == '-' 5965 || cur_token.code == '+') 5966 { 5967 char *save_str; 5968 5969 /* Allow constants that start with `+' or `-'. */ 5970 if (cur_token.code == '-' || cur_token.code == '+') 5971 { 5972 strcat (intel_parser.disp, cur_token.str); 5973 intel_match_token (cur_token.code); 5974 if (cur_token.code != T_CONST) 5975 { 5976 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"), 5977 cur_token.str); 5978 return 0; 5979 } 5980 } 5981 5982 save_str = (char *) malloc (strlen (cur_token.str) + 1); 5983 if (save_str == NULL) 5984 abort (); 5985 strcpy (save_str, cur_token.str); 5986 5987 /* Get the next token to check for register scaling. */ 5988 intel_match_token (cur_token.code); 5989 5990 /* Check if this constant is a scaling factor for an index register. */ 5991 if (cur_token.code == '*') 5992 { 5993 if (intel_match_token ('*') && cur_token.code == T_REG) 5994 { 5995 if (!intel_parser.is_mem) 5996 { 5997 as_bad (_("Register scaling only allowed in memory operands.")); 5998 return 0; 5999 } 6000 6001 /* The constant is followed by `* reg', so it must be 6002 a valid scale. */ 6003 if (strchr ("01248", *save_str)) 6004 { 6005 i.index_reg = cur_token.reg; 6006 i.types[this_operand] |= BaseIndex; 6007 6008 /* Set the scale after setting the register (otherwise, 6009 i386_scale will complain) */ 6010 i386_scale (save_str); 6011 intel_match_token (T_REG); 6012 6013 /* Since registers are not part of the displacement 6014 string, we may need to remove any preceding '+' from 6015 the displacement string. */ 6016 if (*intel_parser.disp != '\0') 6017 { 6018 char *s = intel_parser.disp; 6019 s += strlen (s) - 1; 6020 if (*s == '+') 6021 *s = '\0'; 6022 } 6023 6024 free (save_str); 6025 6026 return 1; 6027 } 6028 else 6029 return 0; 6030 } 6031 6032 /* The constant was not used for register scaling. Since we have 6033 already consumed the token following `*' we now need to put it 6034 back in the stream. */ 6035 else 6036 intel_putback_token (); 6037 } 6038 6039 /* Add the constant to the displacement string. */ 6040 strcat (intel_parser.disp, save_str); 6041 free (save_str); 6042 6043 return 1; 6044 } 6045 6046 as_bad (_("Unrecognized token '%s'"), cur_token.str); 6047 return 0; 6048 } 6049 6050 /* Match the given token against cur_token. If they match, read the next 6051 token from the operand string. */ 6052 static int 6053 intel_match_token (code) 6054 int code; 6055 { 6056 if (cur_token.code == code) 6057 { 6058 intel_get_token (); 6059 return 1; 6060 } 6061 else 6062 { 6063 as_bad (_("Unexpected token `%s'\n"), cur_token.str); 6064 return 0; 6065 } 6066 } 6067 6068 /* Read a new token from intel_parser.op_string and store it in cur_token. */ 6069 static void 6070 intel_get_token () 6071 { 6072 char *end_op; 6073 const reg_entry *reg; 6074 struct intel_token new_token; 6075 6076 new_token.code = T_NIL; 6077 new_token.reg = NULL; 6078 new_token.str = NULL; 6079 6080 /* Free the memory allocated to the previous token and move 6081 cur_token to prev_token. */ 6082 if (prev_token.str) 6083 free (prev_token.str); 6084 6085 prev_token = cur_token; 6086 6087 /* Skip whitespace. */ 6088 while (is_space_char (*intel_parser.op_string)) 6089 intel_parser.op_string++; 6090 6091 /* Return an empty token if we find nothing else on the line. */ 6092 if (*intel_parser.op_string == '\0') 6093 { 6094 cur_token = new_token; 6095 return; 6096 } 6097 6098 /* The new token cannot be larger than the remainder of the operand 6099 string. */ 6100 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1); 6101 if (new_token.str == NULL) 6102 abort (); 6103 new_token.str[0] = '\0'; 6104 6105 if (strchr ("0123456789", *intel_parser.op_string)) 6106 { 6107 char *p = new_token.str; 6108 char *q = intel_parser.op_string; 6109 new_token.code = T_CONST; 6110 6111 /* Allow any kind of identifier char to encompass floating point and 6112 hexadecimal numbers. */ 6113 while (is_identifier_char (*q)) 6114 *p++ = *q++; 6115 *p = '\0'; 6116 6117 /* Recognize special symbol names [0-9][bf]. */ 6118 if (strlen (intel_parser.op_string) == 2 6119 && (intel_parser.op_string[1] == 'b' 6120 || intel_parser.op_string[1] == 'f')) 6121 new_token.code = T_ID; 6122 } 6123 6124 else if (strchr ("+-/*:[]()", *intel_parser.op_string)) 6125 { 6126 new_token.code = *intel_parser.op_string; 6127 new_token.str[0] = *intel_parser.op_string; 6128 new_token.str[1] = '\0'; 6129 } 6130 6131 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg) 6132 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)) 6133 { 6134 new_token.code = T_REG; 6135 new_token.reg = reg; 6136 6137 if (*intel_parser.op_string == REGISTER_PREFIX) 6138 { 6139 new_token.str[0] = REGISTER_PREFIX; 6140 new_token.str[1] = '\0'; 6141 } 6142 6143 strcat (new_token.str, reg->reg_name); 6144 } 6145 6146 else if (is_identifier_char (*intel_parser.op_string)) 6147 { 6148 char *p = new_token.str; 6149 char *q = intel_parser.op_string; 6150 6151 /* A '.' or '$' followed by an identifier char is an identifier. 6152 Otherwise, it's operator '.' followed by an expression. */ 6153 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) 6154 { 6155 new_token.code = *q; 6156 new_token.str[0] = *q; 6157 new_token.str[1] = '\0'; 6158 } 6159 else 6160 { 6161 while (is_identifier_char (*q) || *q == '@') 6162 *p++ = *q++; 6163 *p = '\0'; 6164 6165 if (strcasecmp (new_token.str, "BYTE") == 0) 6166 new_token.code = T_BYTE; 6167 6168 else if (strcasecmp (new_token.str, "WORD") == 0) 6169 new_token.code = T_WORD; 6170 6171 else if (strcasecmp (new_token.str, "DWORD") == 0) 6172 new_token.code = T_DWORD; 6173 6174 else if (strcasecmp (new_token.str, "QWORD") == 0) 6175 new_token.code = T_QWORD; 6176 6177 else if (strcasecmp (new_token.str, "XWORD") == 0) 6178 new_token.code = T_XWORD; 6179 6180 else if (strcasecmp (new_token.str, "PTR") == 0) 6181 new_token.code = T_PTR; 6182 6183 else if (strcasecmp (new_token.str, "SHORT") == 0) 6184 new_token.code = T_SHORT; 6185 6186 else if (strcasecmp (new_token.str, "OFFSET") == 0) 6187 { 6188 new_token.code = T_OFFSET; 6189 6190 /* ??? This is not mentioned in the MASM grammar but gcc 6191 makes use of it with -mintel-syntax. OFFSET may be 6192 followed by FLAT: */ 6193 if (strncasecmp (q, " FLAT:", 6) == 0) 6194 strcat (new_token.str, " FLAT:"); 6195 } 6196 6197 /* ??? This is not mentioned in the MASM grammar. */ 6198 else if (strcasecmp (new_token.str, "FLAT") == 0) 6199 new_token.code = T_OFFSET; 6200 6201 else 6202 new_token.code = T_ID; 6203 } 6204 } 6205 6206 else 6207 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string); 6208 6209 intel_parser.op_string += strlen (new_token.str); 6210 cur_token = new_token; 6211 } 6212 6213 /* Put cur_token back into the token stream and make cur_token point to 6214 prev_token. */ 6215 static void 6216 intel_putback_token () 6217 { 6218 intel_parser.op_string -= strlen (cur_token.str); 6219 free (cur_token.str); 6220 cur_token = prev_token; 6221 6222 /* Forget prev_token. */ 6223 prev_token.code = T_NIL; 6224 prev_token.reg = NULL; 6225 prev_token.str = NULL; 6226 } 6227 6228 int 6229 tc_x86_regname_to_dw2regnum (const char *regname) 6230 { 6231 unsigned int regnum; 6232 unsigned int regnames_count; 6233 static const char *const regnames_32[] = 6234 { 6235 "eax", "ecx", "edx", "ebx", 6236 "esp", "ebp", "esi", "edi", 6237 "eip", "eflags", NULL, 6238 "st0", "st1", "st2", "st3", 6239 "st4", "st5", "st6", "st7", 6240 NULL, NULL, 6241 "xmm0", "xmm1", "xmm2", "xmm3", 6242 "xmm4", "xmm5", "xmm6", "xmm7", 6243 "mm0", "mm1", "mm2", "mm3", 6244 "mm4", "mm5", "mm6", "mm7", 6245 "fcw", "fsw", "mxcsr", 6246 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, 6247 "tr", "ldtr" 6248 }; 6249 static const char *const regnames_64[] = 6250 { 6251 "rax", "rdx", "rcx", "rbx", 6252 "rsi", "rdi", "rbp", "rsp", 6253 "r8", "r9", "r10", "r11", 6254 "r12", "r13", "r14", "r15", 6255 "rip", 6256 "xmm0", "xmm1", "xmm2", "xmm3", 6257 "xmm4", "xmm5", "xmm6", "xmm7", 6258 "xmm8", "xmm9", "xmm10", "xmm11", 6259 "xmm12", "xmm13", "xmm14", "xmm15", 6260 "st0", "st1", "st2", "st3", 6261 "st4", "st5", "st6", "st7", 6262 "mm0", "mm1", "mm2", "mm3", 6263 "mm4", "mm5", "mm6", "mm7", 6264 "rflags", 6265 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, 6266 "fs.base", "gs.base", NULL, NULL, 6267 "tr", "ldtr", 6268 "mxcsr", "fcw", "fsw" 6269 }; 6270 const char *const *regnames; 6271 6272 if (flag_code == CODE_64BIT) 6273 { 6274 regnames = regnames_64; 6275 regnames_count = ARRAY_SIZE (regnames_64); 6276 } 6277 else 6278 { 6279 regnames = regnames_32; 6280 regnames_count = ARRAY_SIZE (regnames_32); 6281 } 6282 6283 for (regnum = 0; regnum < regnames_count; regnum++) 6284 if (regnames[regnum] != NULL 6285 && strcmp (regname, regnames[regnum]) == 0) 6286 return regnum; 6287 6288 return -1; 6289 } 6290 6291 void 6292 tc_x86_frame_initial_instructions (void) 6293 { 6294 static unsigned int sp_regno; 6295 6296 if (!sp_regno) 6297 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT 6298 ? "rsp" : "esp"); 6299 6300 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment); 6301 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); 6302 } 6303