1 /* tc-m32r.c -- Assembler for the Renesas M32R. 2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 3 Free Software Foundation, Inc. 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 2, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to 19 the Free Software Foundation, 59 Temple Place - Suite 330, 20 Boston, MA 02111-1307, USA. */ 21 22 #include <stdio.h> 23 #include "as.h" 24 #include "safe-ctype.h" 25 #include "subsegs.h" 26 #include "symcat.h" 27 #include "opcodes/m32r-desc.h" 28 #include "opcodes/m32r-opc.h" 29 #include "cgen.h" 30 #include "elf/m32r.h" 31 32 /* Linked list of symbols that are debugging symbols to be defined as the 33 beginning of the current instruction. */ 34 typedef struct sym_link 35 { 36 struct sym_link *next; 37 symbolS *symbol; 38 } sym_linkS; 39 40 static sym_linkS *debug_sym_link = (sym_linkS *) 0; 41 42 /* Structure to hold all of the different components describing 43 an individual instruction. */ 44 typedef struct 45 { 46 const CGEN_INSN *insn; 47 const CGEN_INSN *orig_insn; 48 CGEN_FIELDS fields; 49 #if CGEN_INT_INSN_P 50 CGEN_INSN_INT buffer[1]; 51 #define INSN_VALUE(buf) (*(buf)) 52 #else 53 unsigned char buffer[CGEN_MAX_INSN_SIZE]; 54 #define INSN_VALUE(buf) (buf) 55 #endif 56 char *addr; 57 fragS *frag; 58 int num_fixups; 59 fixS *fixups[GAS_CGEN_MAX_FIXUPS]; 60 int indices[MAX_OPERAND_INSTANCES]; 61 sym_linkS *debug_sym_link; 62 } 63 m32r_insn; 64 65 /* prev_insn.insn is non-null if last insn was a 16 bit insn on a 32 bit 66 boundary (i.e. was the first of two 16 bit insns). */ 67 static m32r_insn prev_insn; 68 69 /* Non-zero if we've seen a relaxable insn since the last 32 bit 70 alignment request. */ 71 static int seen_relaxable_p = 0; 72 73 /* Non-zero if we are generating PIC code. */ 74 int pic_code; 75 76 /* Non-zero if -relax specified, in which case sufficient relocs are output 77 for the linker to do relaxing. 78 We do simple forms of relaxing internally, but they are always done. 79 This flag does not apply to them. */ 80 static int m32r_relax; 81 82 #if 0 83 /* Not supported yet. */ 84 /* If non-NULL, pointer to cpu description file to read. 85 This allows runtime additions to the assembler. */ 86 static const char *m32r_cpu_desc; 87 #endif 88 89 /* Non-zero if warn when a high/shigh reloc has no matching low reloc. 90 Each high/shigh reloc must be paired with it's low cousin in order to 91 properly calculate the addend in a relocatable link (since there is a 92 potential carry from the low to the high/shigh). 93 This option is off by default though for user-written assembler code it 94 might make sense to make the default be on (i.e. have gcc pass a flag 95 to turn it off). This warning must not be on for GCC created code as 96 optimization may delete the low but not the high/shigh (at least we 97 shouldn't assume or require it to). */ 98 static int warn_unmatched_high = 0; 99 100 /* 1 if -m32rx has been specified, in which case support for 101 the extended M32RX instruction set should be enabled. 102 2 if -m32r2 has been specified, in which case support for 103 the extended M32R2 instruction set should be enabled. */ 104 static int enable_m32rx = 0; /* Default to M32R. */ 105 106 /* Non-zero if -m32rx -hidden has been specified, in which case support for 107 the special M32RX instruction set should be enabled. */ 108 static int enable_special = 0; 109 110 /* Non-zero if -bitinst has been specified, in which case support 111 for extended M32R bit-field instruction set should be enabled. */ 112 static int enable_special_m32r = 0; 113 114 /* Non-zero if -float has been specified, in which case support for 115 extended M32R floating point instruction set should be enabled. */ 116 static int enable_special_float = 0; 117 118 /* Non-zero if the programmer should be warned when an explicit parallel 119 instruction might have constraint violations. */ 120 static int warn_explicit_parallel_conflicts = 1; 121 122 /* Non-zero if the programmer should not receive any messages about 123 parallel instruction with potential or real constraint violations. 124 The ability to suppress these messages is intended only for hardware 125 vendors testing the chip. It superceedes 126 warn_explicit_parallel_conflicts. */ 127 static int ignore_parallel_conflicts = 0; 128 129 /* Non-zero if insns can be made parallel. */ 130 static int use_parallel = 1; 131 132 /* Non-zero if optimizations should be performed. */ 133 static int optimize; 134 135 /* m32r er_flags. */ 136 static int m32r_flags = 0; 137 138 /* Stuff for .scomm symbols. */ 139 static segT sbss_section; 140 static asection scom_section; 141 static asymbol scom_symbol; 142 143 const char comment_chars[] = ";"; 144 const char line_comment_chars[] = "#"; 145 const char line_separator_chars[] = "!"; 146 const char EXP_CHARS[] = "eE"; 147 const char FLT_CHARS[] = "dD"; 148 149 /* Relocations against symbols are done in two 150 parts, with a HI relocation and a LO relocation. Each relocation 151 has only 16 bits of space to store an addend. This means that in 152 order for the linker to handle carries correctly, it must be able 153 to locate both the HI and the LO relocation. This means that the 154 relocations must appear in order in the relocation table. 155 156 In order to implement this, we keep track of each unmatched HI 157 relocation. We then sort them so that they immediately precede the 158 corresponding LO relocation. */ 159 160 struct m32r_hi_fixup 161 { 162 /* Next HI fixup. */ 163 struct m32r_hi_fixup *next; 164 165 /* This fixup. */ 166 fixS *fixp; 167 168 /* The section this fixup is in. */ 169 segT seg; 170 }; 171 172 /* The list of unmatched HI relocs. */ 173 174 static struct m32r_hi_fixup *m32r_hi_fixup_list; 175 176 struct { 177 enum bfd_architecture bfd_mach; 178 int mach_flags; 179 } mach_table[] = 180 { 181 { bfd_mach_m32r, (1<<MACH_M32R) }, 182 { bfd_mach_m32rx, (1<<MACH_M32RX) }, 183 { bfd_mach_m32r2, (1<<MACH_M32R2) } 184 }; 185 186 static void allow_m32rx (int); 187 188 static void 189 allow_m32rx (int on) 190 { 191 enable_m32rx = on; 192 193 if (stdoutput != NULL) 194 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach_table[on].bfd_mach); 195 196 if (gas_cgen_cpu_desc != NULL) 197 gas_cgen_cpu_desc->machs = mach_table[on].mach_flags; 198 } 199 200 #define M32R_SHORTOPTS "O::K:" 201 202 const char *md_shortopts = M32R_SHORTOPTS; 203 204 struct option md_longopts[] = 205 { 206 #define OPTION_M32R (OPTION_MD_BASE) 207 #define OPTION_M32RX (OPTION_M32R + 1) 208 #define OPTION_M32R2 (OPTION_M32RX + 1) 209 #define OPTION_BIG (OPTION_M32R2 + 1) 210 #define OPTION_LITTLE (OPTION_BIG + 1) 211 #define OPTION_PARALLEL (OPTION_LITTLE + 1) 212 #define OPTION_NO_PARALLEL (OPTION_PARALLEL + 1) 213 #define OPTION_WARN_PARALLEL (OPTION_NO_PARALLEL + 1) 214 #define OPTION_NO_WARN_PARALLEL (OPTION_WARN_PARALLEL + 1) 215 #define OPTION_IGNORE_PARALLEL (OPTION_NO_WARN_PARALLEL + 1) 216 #define OPTION_NO_IGNORE_PARALLEL (OPTION_IGNORE_PARALLEL + 1) 217 #define OPTION_SPECIAL (OPTION_NO_IGNORE_PARALLEL + 1) 218 #define OPTION_SPECIAL_M32R (OPTION_SPECIAL + 1) 219 #define OPTION_SPECIAL_FLOAT (OPTION_SPECIAL_M32R + 1) 220 #define OPTION_WARN_UNMATCHED (OPTION_SPECIAL_FLOAT + 1) 221 #define OPTION_NO_WARN_UNMATCHED (OPTION_WARN_UNMATCHED + 1) 222 {"m32r", no_argument, NULL, OPTION_M32R}, 223 {"m32rx", no_argument, NULL, OPTION_M32RX}, 224 {"m32r2", no_argument, NULL, OPTION_M32R2}, 225 {"big", no_argument, NULL, OPTION_BIG}, 226 {"little", no_argument, NULL, OPTION_LITTLE}, 227 {"EB", no_argument, NULL, OPTION_BIG}, 228 {"EL", no_argument, NULL, OPTION_LITTLE}, 229 {"parallel", no_argument, NULL, OPTION_PARALLEL}, 230 {"no-parallel", no_argument, NULL, OPTION_NO_PARALLEL}, 231 {"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL}, 232 {"Wp", no_argument, NULL, OPTION_WARN_PARALLEL}, 233 {"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, 234 {"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL}, 235 {"ignore-parallel-conflicts", no_argument, NULL, OPTION_IGNORE_PARALLEL}, 236 {"Ip", no_argument, NULL, OPTION_IGNORE_PARALLEL}, 237 {"no-ignore-parallel-conflicts", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL}, 238 {"nIp", no_argument, NULL, OPTION_NO_IGNORE_PARALLEL}, 239 {"hidden", no_argument, NULL, OPTION_SPECIAL}, 240 {"bitinst", no_argument, NULL, OPTION_SPECIAL_M32R}, 241 {"float", no_argument, NULL, OPTION_SPECIAL_FLOAT}, 242 /* Sigh. I guess all warnings must now have both variants. */ 243 {"warn-unmatched-high", no_argument, NULL, OPTION_WARN_UNMATCHED}, 244 {"Wuh", no_argument, NULL, OPTION_WARN_UNMATCHED}, 245 {"no-warn-unmatched-high", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, 246 {"Wnuh", no_argument, NULL, OPTION_NO_WARN_UNMATCHED}, 247 248 #if 0 249 /* Not supported yet. */ 250 #define OPTION_RELAX (OPTION_NO_WARN_UNMATCHED + 1) 251 #define OPTION_CPU_DESC (OPTION_RELAX + 1) 252 {"relax", no_argument, NULL, OPTION_RELAX}, 253 {"cpu-desc", required_argument, NULL, OPTION_CPU_DESC}, 254 #endif 255 {NULL, no_argument, NULL, 0} 256 }; 257 258 size_t md_longopts_size = sizeof (md_longopts); 259 260 static void little (int); 261 static int parallel (void); 262 263 static void 264 little (int on) 265 { 266 target_big_endian = ! on; 267 } 268 269 /* Use parallel execution. */ 270 271 static int 272 parallel (void) 273 { 274 if (! enable_m32rx) 275 return 0; 276 277 if (use_parallel == 1) 278 return 1; 279 280 return 0; 281 } 282 283 int 284 md_parse_option (c, arg) 285 int c; 286 char *arg ATTRIBUTE_UNUSED; 287 { 288 switch (c) 289 { 290 case 'O': 291 optimize = 1; 292 use_parallel = 1; 293 break; 294 295 case OPTION_M32R: 296 allow_m32rx (0); 297 break; 298 299 case OPTION_M32RX: 300 allow_m32rx (1); 301 break; 302 303 case OPTION_M32R2: 304 allow_m32rx (2); 305 enable_special = 1; 306 enable_special_m32r = 1; 307 break; 308 309 case OPTION_BIG: 310 target_big_endian = 1; 311 break; 312 313 case OPTION_LITTLE: 314 target_big_endian = 0; 315 break; 316 317 case OPTION_PARALLEL: 318 use_parallel = 1; 319 break; 320 321 case OPTION_NO_PARALLEL: 322 use_parallel = 0; 323 break; 324 325 case OPTION_WARN_PARALLEL: 326 warn_explicit_parallel_conflicts = 1; 327 break; 328 329 case OPTION_NO_WARN_PARALLEL: 330 warn_explicit_parallel_conflicts = 0; 331 break; 332 333 case OPTION_IGNORE_PARALLEL: 334 ignore_parallel_conflicts = 1; 335 break; 336 337 case OPTION_NO_IGNORE_PARALLEL: 338 ignore_parallel_conflicts = 0; 339 break; 340 341 case OPTION_SPECIAL: 342 if (enable_m32rx) 343 enable_special = 1; 344 else 345 { 346 /* Pretend that we do not recognise this option. */ 347 as_bad (_("Unrecognised option: -hidden")); 348 return 0; 349 } 350 break; 351 352 case OPTION_SPECIAL_M32R: 353 enable_special_m32r = 1; 354 break; 355 356 case OPTION_SPECIAL_FLOAT: 357 enable_special_float = 1; 358 break; 359 360 case OPTION_WARN_UNMATCHED: 361 warn_unmatched_high = 1; 362 break; 363 364 case OPTION_NO_WARN_UNMATCHED: 365 warn_unmatched_high = 0; 366 break; 367 368 case 'K': 369 if (strcmp (arg, "PIC") != 0) 370 as_warn (_("Unrecognized option following -K")); 371 else 372 pic_code = 1; 373 break; 374 375 #if 0 376 /* Not supported yet. */ 377 case OPTION_RELAX: 378 m32r_relax = 1; 379 break; 380 case OPTION_CPU_DESC: 381 m32r_cpu_desc = arg; 382 break; 383 #endif 384 385 default: 386 return 0; 387 } 388 389 return 1; 390 } 391 392 void 393 md_show_usage (stream) 394 FILE *stream; 395 { 396 fprintf (stream, _(" M32R specific command line options:\n")); 397 398 fprintf (stream, _("\ 399 -m32r disable support for the m32rx instruction set\n")); 400 fprintf (stream, _("\ 401 -m32rx support the extended m32rx instruction set\n")); 402 fprintf (stream, _("\ 403 -m32r2 support the extended m32r2 instruction set\n")); 404 fprintf (stream, _("\ 405 -EL,-little produce little endian code and data\n")); 406 fprintf (stream, _("\ 407 -EB,-big produce big endian code and data\n")); 408 fprintf (stream, _("\ 409 -parallel try to combine instructions in parallel\n")); 410 fprintf (stream, _("\ 411 -no-parallel disable -parallel\n")); 412 fprintf (stream, _("\ 413 -O try to optimize code. Implies -parallel\n")); 414 415 fprintf (stream, _("\ 416 -warn-explicit-parallel-conflicts warn when parallel instructions\n")); 417 fprintf (stream, _("\ 418 might violate contraints\n")); 419 fprintf (stream, _("\ 420 -no-warn-explicit-parallel-conflicts do not warn when parallel\n")); 421 fprintf (stream, _("\ 422 instructions might violate contraints\n")); 423 fprintf (stream, _("\ 424 -Wp synonym for -warn-explicit-parallel-conflicts\n")); 425 fprintf (stream, _("\ 426 -Wnp synonym for -no-warn-explicit-parallel-conflicts\n")); 427 fprintf (stream, _("\ 428 -ignore-parallel-conflicts do not check parallel instructions\n")); 429 fprintf (stream, _("\ 430 fo contraint violations\n")); 431 fprintf (stream, _("\ 432 -no-ignore-parallel-conflicts check parallel instructions for\n")); 433 fprintf (stream, _("\ 434 contraint violations\n")); 435 fprintf (stream, _("\ 436 -Ip synonym for -ignore-parallel-conflicts\n")); 437 fprintf (stream, _("\ 438 -nIp synonym for -no-ignore-parallel-conflicts\n")); 439 440 fprintf (stream, _("\ 441 -warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n")); 442 fprintf (stream, _("\ 443 -no-warn-unmatched-high do not warn about missing low relocs\n")); 444 fprintf (stream, _("\ 445 -Wuh synonym for -warn-unmatched-high\n")); 446 fprintf (stream, _("\ 447 -Wnuh synonym for -no-warn-unmatched-high\n")); 448 449 fprintf (stream, _("\ 450 -KPIC generate PIC\n")); 451 452 #if 0 453 fprintf (stream, _("\ 454 -relax create linker relaxable code\n")); 455 fprintf (stream, _("\ 456 -cpu-desc provide runtime cpu description file\n")); 457 #endif 458 } 459 460 static void fill_insn PARAMS ((int)); 461 static void m32r_scomm PARAMS ((int)); 462 static void debug_sym PARAMS ((int)); 463 static void expand_debug_syms PARAMS ((sym_linkS *, int)); 464 465 /* Set by md_assemble for use by m32r_fill_insn. */ 466 static subsegT prev_subseg; 467 static segT prev_seg; 468 469 /* The target specific pseudo-ops which we support. */ 470 const pseudo_typeS md_pseudo_table[] = 471 { 472 { "word", cons, 4 }, 473 { "fillinsn", fill_insn, 0 }, 474 { "scomm", m32r_scomm, 0 }, 475 { "debugsym", debug_sym, 0 }, 476 { "m32r", allow_m32rx, 0 }, 477 { "m32rx", allow_m32rx, 1 }, 478 { "m32r2", allow_m32rx, 2 }, 479 { "little", little, 1 }, 480 { "big", little, 0 }, 481 { NULL, NULL, 0 } 482 }; 483 484 /* FIXME: Should be machine generated. */ 485 #define NOP_INSN 0x7000 486 #define PAR_NOP_INSN 0xf000 /* Can only be used in 2nd slot. */ 487 488 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents 489 of an rs_align_code fragment. */ 490 491 void 492 m32r_handle_align (fragp) 493 fragS *fragp; 494 { 495 static const unsigned char nop_pattern[] = { 0xf0, 0x00 }; 496 static const unsigned char multi_nop_pattern[] = { 0x70, 0x00, 0xf0, 0x00 }; 497 498 int bytes, fix; 499 char *p; 500 501 if (fragp->fr_type != rs_align_code) 502 return; 503 504 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 505 p = fragp->fr_literal + fragp->fr_fix; 506 fix = 0; 507 508 if (bytes & 1) 509 { 510 fix = 1; 511 *p++ = 0; 512 bytes--; 513 } 514 515 if (bytes & 2) 516 { 517 memcpy (p, nop_pattern, 2); 518 p += 2; 519 bytes -= 2; 520 fix += 2; 521 } 522 523 memcpy (p, multi_nop_pattern, 4); 524 525 fragp->fr_fix += fix; 526 fragp->fr_var = 4; 527 } 528 529 /* If the last instruction was the first of 2 16 bit insns, 530 output a nop to move the PC to a 32 bit boundary. 531 532 This is done via an alignment specification since branch relaxing 533 may make it unnecessary. 534 535 Internally, we need to output one of these each time a 32 bit insn is 536 seen after an insn that is relaxable. */ 537 538 static void 539 fill_insn (ignore) 540 int ignore ATTRIBUTE_UNUSED; 541 { 542 frag_align_code (2, 0); 543 prev_insn.insn = NULL; 544 seen_relaxable_p = 0; 545 } 546 547 /* Record the symbol so that when we output the insn, we can create 548 a symbol that is at the start of the instruction. This is used 549 to emit the label for the start of a breakpoint without causing 550 the assembler to emit a NOP if the previous instruction was a 551 16 bit instruction. */ 552 553 static void 554 debug_sym (ignore) 555 int ignore ATTRIBUTE_UNUSED; 556 { 557 register char *name; 558 register char delim; 559 register char *end_name; 560 register symbolS *symbolP; 561 register sym_linkS *link; 562 563 name = input_line_pointer; 564 delim = get_symbol_end (); 565 end_name = input_line_pointer; 566 567 if ((symbolP = symbol_find (name)) == NULL 568 && (symbolP = md_undefined_symbol (name)) == NULL) 569 { 570 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag); 571 } 572 573 symbol_table_insert (symbolP); 574 if (S_IS_DEFINED (symbolP) && (S_GET_SEGMENT (symbolP) != reg_section 575 || S_IS_EXTERNAL (symbolP) 576 || S_IS_WEAK (symbolP))) 577 /* xgettext:c-format */ 578 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP)); 579 580 else 581 { 582 link = (sym_linkS *) xmalloc (sizeof (sym_linkS)); 583 link->symbol = symbolP; 584 link->next = debug_sym_link; 585 debug_sym_link = link; 586 symbol_get_obj (symbolP)->local = 1; 587 } 588 589 *end_name = delim; 590 demand_empty_rest_of_line (); 591 } 592 593 /* Second pass to expanding the debug symbols, go through linked 594 list of symbols and reassign the address. */ 595 596 static void 597 expand_debug_syms (syms, align) 598 sym_linkS *syms; 599 int align; 600 { 601 char *save_input_line = input_line_pointer; 602 sym_linkS *next_syms; 603 604 if (!syms) 605 return; 606 607 (void) frag_align_code (align, 0); 608 for (; syms != (sym_linkS *) 0; syms = next_syms) 609 { 610 symbolS *symbolP = syms->symbol; 611 next_syms = syms->next; 612 input_line_pointer = ".\n"; 613 pseudo_set (symbolP); 614 free ((char *) syms); 615 } 616 617 input_line_pointer = save_input_line; 618 } 619 620 void 621 m32r_flush_pending_output() 622 { 623 if (debug_sym_link) 624 { 625 expand_debug_syms (debug_sym_link, 1); 626 debug_sym_link = (sym_linkS *) 0; 627 } 628 } 629 630 /* Cover function to fill_insn called after a label and at end of assembly. 631 The result is always 1: we're called in a conditional to see if the 632 current line is a label. */ 633 634 int 635 m32r_fill_insn (done) 636 int done; 637 { 638 if (prev_seg != NULL) 639 { 640 segT seg = now_seg; 641 subsegT subseg = now_subseg; 642 643 subseg_set (prev_seg, prev_subseg); 644 645 fill_insn (0); 646 647 subseg_set (seg, subseg); 648 } 649 650 if (done && debug_sym_link) 651 { 652 expand_debug_syms (debug_sym_link, 1); 653 debug_sym_link = (sym_linkS *) 0; 654 } 655 656 return 1; 657 } 658 659 /* The default target format to use. */ 660 661 const char * 662 m32r_target_format () 663 { 664 #ifdef TE_LINUX 665 if (target_big_endian) 666 return "elf32-m32r-linux"; 667 else 668 return "elf32-m32rle-linux"; 669 #else 670 if (target_big_endian) 671 return "elf32-m32r"; 672 else 673 return "elf32-m32rle"; 674 #endif 675 } 676 677 void 678 md_begin () 679 { 680 flagword applicable; 681 segT seg; 682 subsegT subseg; 683 684 /* Initialize the `cgen' interface. */ 685 686 /* Set the machine number and endian. */ 687 gas_cgen_cpu_desc = m32r_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, 688 CGEN_CPU_OPEN_ENDIAN, 689 (target_big_endian ? 690 CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE), 691 CGEN_CPU_OPEN_END); 692 m32r_cgen_init_asm (gas_cgen_cpu_desc); 693 694 /* The operand instance table is used during optimization to determine 695 which insns can be executed in parallel. It is also used to give 696 warnings regarding operand interference in parallel insns. */ 697 m32r_cgen_init_opinst_table (gas_cgen_cpu_desc); 698 699 /* This is a callback from cgen to gas to parse operands. */ 700 cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); 701 702 #if 0 703 /* Not supported yet. */ 704 /* If a runtime cpu description file was provided, parse it. */ 705 if (m32r_cpu_desc != NULL) 706 { 707 const char *errmsg; 708 709 errmsg = cgen_read_cpu_file (gas_cgen_cpu_desc, m32r_cpu_desc); 710 if (errmsg != NULL) 711 as_bad ("%s: %s", m32r_cpu_desc, errmsg); 712 } 713 #endif 714 715 /* Save the current subseg so we can restore it [it's the default one and 716 we don't want the initial section to be .sbss]. */ 717 seg = now_seg; 718 subseg = now_subseg; 719 720 /* The sbss section is for local .scomm symbols. */ 721 sbss_section = subseg_new (".sbss", 0); 722 723 /* This is copied from perform_an_assembly_pass. */ 724 applicable = bfd_applicable_section_flags (stdoutput); 725 bfd_set_section_flags (stdoutput, sbss_section, applicable & SEC_ALLOC); 726 727 #if 0 728 /* What does this do? [see perform_an_assembly_pass] */ 729 seg_info (bss_section)->bss = 1; 730 #endif 731 732 subseg_set (seg, subseg); 733 734 /* We must construct a fake section similar to bfd_com_section 735 but with the name .scommon. */ 736 scom_section = bfd_com_section; 737 scom_section.name = ".scommon"; 738 scom_section.output_section = &scom_section; 739 scom_section.symbol = &scom_symbol; 740 scom_section.symbol_ptr_ptr = &scom_section.symbol; 741 scom_symbol = *bfd_com_section.symbol; 742 scom_symbol.name = ".scommon"; 743 scom_symbol.section = &scom_section; 744 745 allow_m32rx (enable_m32rx); 746 747 gas_cgen_initialize_saved_fixups_array (); 748 } 749 750 #define OPERAND_IS_COND_BIT(operand, indices, index) \ 751 ((operand)->hw_type == HW_H_COND \ 752 || ((operand)->hw_type == HW_H_PSW) \ 753 || ((operand)->hw_type == HW_H_CR \ 754 && (indices [index] == 0 || indices [index] == 1))) 755 756 /* Returns true if an output of instruction 'a' is referenced by an operand 757 of instruction 'b'. If 'check_outputs' is true then b's outputs are 758 checked, otherwise its inputs are examined. */ 759 760 static int first_writes_to_seconds_operands 761 PARAMS ((m32r_insn *, m32r_insn *, const int)); 762 763 static int 764 first_writes_to_seconds_operands (a, b, check_outputs) 765 m32r_insn *a; 766 m32r_insn *b; 767 const int check_outputs; 768 { 769 const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn); 770 const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn); 771 int a_index; 772 773 if (ignore_parallel_conflicts) 774 return 0; 775 776 /* If at least one of the instructions takes no operands, then there is 777 nothing to check. There really are instructions without operands, 778 eg 'nop'. */ 779 if (a_operands == NULL || b_ops == NULL) 780 return 0; 781 782 /* Scan the operand list of 'a' looking for an output operand. */ 783 for (a_index = 0; 784 a_operands->type != CGEN_OPINST_END; 785 a_index ++, a_operands ++) 786 { 787 if (a_operands->type == CGEN_OPINST_OUTPUT) 788 { 789 int b_index; 790 const CGEN_OPINST *b_operands = b_ops; 791 792 /* Special Case: 793 The Condition bit 'C' is a shadow of the CBR register (control 794 register 1) and also a shadow of bit 31 of the program status 795 word (control register 0). For now this is handled here, rather 796 than by cgen.... */ 797 798 if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index)) 799 { 800 /* Scan operand list of 'b' looking for another reference to the 801 condition bit, which goes in the right direction. */ 802 for (b_index = 0; 803 b_operands->type != CGEN_OPINST_END; 804 b_index++, b_operands++) 805 { 806 if ((b_operands->type 807 == (check_outputs 808 ? CGEN_OPINST_OUTPUT 809 : CGEN_OPINST_INPUT)) 810 && OPERAND_IS_COND_BIT (b_operands, b->indices, b_index)) 811 return 1; 812 } 813 } 814 else 815 { 816 /* Scan operand list of 'b' looking for an operand that 817 references the same hardware element, and which goes in the 818 right direction. */ 819 for (b_index = 0; 820 b_operands->type != CGEN_OPINST_END; 821 b_index++, b_operands++) 822 { 823 if ((b_operands->type 824 == (check_outputs 825 ? CGEN_OPINST_OUTPUT 826 : CGEN_OPINST_INPUT)) 827 && (b_operands->hw_type == a_operands->hw_type) 828 && (a->indices[a_index] == b->indices[b_index])) 829 return 1; 830 } 831 } 832 } 833 } 834 835 return 0; 836 } 837 838 /* Returns true if the insn can (potentially) alter the program counter. */ 839 840 static int writes_to_pc PARAMS ((m32r_insn *)); 841 842 static int 843 writes_to_pc (a) 844 m32r_insn *a; 845 { 846 #if 0 847 /* Once PC operands are working.... */ 848 const CGEN_OPINST *a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc, 849 a->insn); 850 851 if (a_operands == NULL) 852 return 0; 853 854 while (a_operands->type != CGEN_OPINST_END) 855 { 856 if (a_operands->operand != NULL 857 && CGEN_OPERAND_INDEX (gas_cgen_cpu_desc, 858 a_operands->operand) == M32R_OPERAND_PC) 859 return 1; 860 861 a_operands++; 862 } 863 #else 864 if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI) 865 || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI)) 866 return 1; 867 #endif 868 return 0; 869 } 870 871 /* Return NULL if the two 16 bit insns can be executed in parallel. 872 Otherwise return a pointer to an error message explaining why not. */ 873 874 static const char *can_make_parallel PARAMS ((m32r_insn *, m32r_insn *)); 875 876 static const char * 877 can_make_parallel (a, b) 878 m32r_insn *a; 879 m32r_insn *b; 880 { 881 PIPE_ATTR a_pipe; 882 PIPE_ATTR b_pipe; 883 884 /* Make sure the instructions are the right length. */ 885 if (CGEN_FIELDS_BITSIZE (&a->fields) != 16 886 || CGEN_FIELDS_BITSIZE (&b->fields) != 16) 887 abort (); 888 889 if (first_writes_to_seconds_operands (a, b, TRUE)) 890 return _("instructions write to the same destination register."); 891 892 a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE); 893 b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE); 894 895 /* Make sure that the instructions use the correct execution pipelines. */ 896 if (a_pipe == PIPE_NONE 897 || b_pipe == PIPE_NONE) 898 return _("Instructions do not use parallel execution pipelines."); 899 900 /* Leave this test for last, since it is the only test that can 901 go away if the instructions are swapped, and we want to make 902 sure that any other errors are detected before this happens. */ 903 if (a_pipe == PIPE_S 904 || b_pipe == PIPE_O 905 || (b_pipe == PIPE_O_OS && (enable_m32rx != 2))) 906 return _("Instructions share the same execution pipeline"); 907 908 return NULL; 909 } 910 911 /* Force the top bit of the second 16-bit insn to be set. */ 912 913 static void make_parallel PARAMS ((CGEN_INSN_BYTES_PTR)); 914 915 static void 916 make_parallel (buffer) 917 CGEN_INSN_BYTES_PTR buffer; 918 { 919 #if CGEN_INT_INSN_P 920 *buffer |= 0x8000; 921 #else 922 buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] 923 |= 0x80; 924 #endif 925 } 926 927 /* Same as make_parallel except buffer contains the bytes in target order. */ 928 929 static void target_make_parallel PARAMS ((char *)); 930 931 static void 932 target_make_parallel (buffer) 933 char *buffer; 934 { 935 buffer[CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1] 936 |= 0x80; 937 } 938 939 /* Assemble two instructions with an explicit parallel operation (||) or 940 sequential operation (->). */ 941 942 static void assemble_two_insns PARAMS ((char *, char *, int)); 943 944 static void 945 assemble_two_insns (str, str2, parallel_p) 946 char *str; 947 char *str2; 948 int parallel_p; 949 { 950 char *str3; 951 m32r_insn first; 952 m32r_insn second; 953 char *errmsg; 954 char save_str2 = *str2; 955 956 /* Separate the two instructions. */ 957 *str2 = 0; 958 959 /* Make sure the two insns begin on a 32 bit boundary. 960 This is also done for the serial case (foo -> bar), relaxing doesn't 961 affect insns written like this. 962 Note that we must always do this as we can't assume anything about 963 whether we're currently on a 32 bit boundary or not. Relaxing may 964 change this. */ 965 fill_insn (0); 966 967 first.debug_sym_link = debug_sym_link; 968 debug_sym_link = (sym_linkS *) 0; 969 970 /* Parse the first instruction. */ 971 if (! (first.insn = m32r_cgen_assemble_insn 972 (gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg))) 973 { 974 as_bad (errmsg); 975 return; 976 } 977 978 /* Check it. */ 979 if (CGEN_FIELDS_BITSIZE (&first.fields) != 16) 980 { 981 /* xgettext:c-format */ 982 as_bad (_("not a 16 bit instruction '%s'"), str); 983 return; 984 } 985 #ifdef E_M32R2_ARCH 986 else if ((enable_m32rx == 1) 987 /* FIXME: Need standard macro to perform this test. */ 988 && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) 989 & (1 << MACH_M32R2)) 990 && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) 991 & (1 << MACH_M32RX))))) 992 { 993 /* xgettext:c-format */ 994 as_bad (_("instruction '%s' is for the M32R2 only"), str); 995 return; 996 } 997 else if ((! enable_special 998 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) 999 || (! enable_special_m32r 1000 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R))) 1001 #else 1002 else if (! enable_special 1003 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL)) 1004 #endif 1005 { 1006 /* xgettext:c-format */ 1007 as_bad (_("unknown instruction '%s'"), str); 1008 return; 1009 } 1010 else if (! enable_m32rx 1011 /* FIXME: Need standard macro to perform this test. */ 1012 && (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) 1013 == (1 << MACH_M32RX))) 1014 { 1015 /* xgettext:c-format */ 1016 as_bad (_("instruction '%s' is for the M32RX only"), str); 1017 return; 1018 } 1019 1020 /* Check to see if this is an allowable parallel insn. */ 1021 if (parallel_p 1022 && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE) 1023 { 1024 /* xgettext:c-format */ 1025 as_bad (_("instruction '%s' cannot be executed in parallel."), str); 1026 return; 1027 } 1028 1029 /* Restore the original assembly text, just in case it is needed. */ 1030 *str2 = save_str2; 1031 1032 /* Save the original string pointer. */ 1033 str3 = str; 1034 1035 /* Advanced past the parsed string. */ 1036 str = str2 + 2; 1037 1038 /* Remember the entire string in case it is needed for error 1039 messages. */ 1040 str2 = str3; 1041 1042 /* Convert the opcode to lower case. */ 1043 { 1044 char *s2 = str; 1045 1046 while (ISSPACE (*s2++)) 1047 continue; 1048 1049 --s2; 1050 1051 while (ISALNUM (*s2)) 1052 { 1053 *s2 = TOLOWER (*s2); 1054 s2++; 1055 } 1056 } 1057 1058 /* Preserve any fixups that have been generated and reset the list 1059 to empty. */ 1060 gas_cgen_save_fixups (0); 1061 1062 /* Get the indices of the operands of the instruction. */ 1063 /* FIXME: CGEN_FIELDS is already recorded, but relying on that fact 1064 doesn't seem right. Perhaps allow passing fields like we do insn. */ 1065 /* FIXME: ALIAS insns do not have operands, so we use this function 1066 to find the equivalent insn and overwrite the value stored in our 1067 structure. We still need the original insn, however, since this 1068 may have certain attributes that are not present in the unaliased 1069 version (eg relaxability). When aliases behave differently this 1070 may have to change. */ 1071 first.orig_insn = first.insn; 1072 { 1073 CGEN_FIELDS tmp_fields; 1074 first.insn = cgen_lookup_get_insn_operands 1075 (gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16, 1076 first.indices, &tmp_fields); 1077 } 1078 1079 if (first.insn == NULL) 1080 as_fatal (_("internal error: lookup/get operands failed")); 1081 1082 second.debug_sym_link = NULL; 1083 1084 /* Parse the second instruction. */ 1085 if (! (second.insn = m32r_cgen_assemble_insn 1086 (gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg))) 1087 { 1088 as_bad (errmsg); 1089 return; 1090 } 1091 1092 /* Check it. */ 1093 if (CGEN_FIELDS_BITSIZE (&second.fields) != 16) 1094 { 1095 /* xgettext:c-format */ 1096 as_bad (_("not a 16 bit instruction '%s'"), str); 1097 return; 1098 } 1099 #ifdef E_M32R2_ARCH 1100 else if ((enable_m32rx == 1) 1101 /* FIXME: Need standard macro to perform this test. */ 1102 && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) 1103 & (1 << MACH_M32R2)) 1104 && !((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) 1105 & (1 << MACH_M32RX))))) 1106 { 1107 /* xgettext:c-format */ 1108 as_bad (_("instruction '%s' is for the M32R2 only"), str); 1109 return; 1110 } 1111 else if ((! enable_special 1112 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) 1113 || (! enable_special_m32r 1114 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R))) 1115 #else 1116 else if (! enable_special 1117 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) 1118 #endif 1119 { 1120 /* xgettext:c-format */ 1121 as_bad (_("unknown instruction '%s'"), str); 1122 return; 1123 } 1124 else if (! enable_m32rx 1125 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) 1126 { 1127 /* xgettext:c-format */ 1128 as_bad (_("instruction '%s' is for the M32RX only"), str); 1129 return; 1130 } 1131 1132 /* Check to see if this is an allowable parallel insn. */ 1133 if (parallel_p 1134 && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE) 1135 { 1136 /* xgettext:c-format */ 1137 as_bad (_("instruction '%s' cannot be executed in parallel."), str); 1138 return; 1139 } 1140 1141 if (parallel_p && ! enable_m32rx) 1142 { 1143 if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP 1144 && CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP) 1145 { 1146 /* xgettext:c-format */ 1147 as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2); 1148 return; 1149 } 1150 } 1151 1152 /* Get the indices of the operands of the instruction. */ 1153 second.orig_insn = second.insn; 1154 { 1155 CGEN_FIELDS tmp_fields; 1156 second.insn = cgen_lookup_get_insn_operands 1157 (gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16, 1158 second.indices, &tmp_fields); 1159 } 1160 1161 if (second.insn == NULL) 1162 as_fatal (_("internal error: lookup/get operands failed")); 1163 1164 /* We assume that if the first instruction writes to a register that is 1165 read by the second instruction it is because the programmer intended 1166 this to happen, (after all they have explicitly requested that these 1167 two instructions be executed in parallel). Although if the global 1168 variable warn_explicit_parallel_conflicts is true then we do generate 1169 a warning message. Similarly we assume that parallel branch and jump 1170 instructions are deliberate and should not produce errors. */ 1171 1172 if (parallel_p && warn_explicit_parallel_conflicts) 1173 { 1174 if (first_writes_to_seconds_operands (&first, &second, FALSE)) 1175 /* xgettext:c-format */ 1176 as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2); 1177 1178 if (first_writes_to_seconds_operands (&second, &first, FALSE)) 1179 /* xgettext:c-format */ 1180 as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2); 1181 } 1182 1183 if (!parallel_p 1184 || (errmsg = (char *) can_make_parallel (&first, &second)) == NULL) 1185 { 1186 /* Get the fixups for the first instruction. */ 1187 gas_cgen_swap_fixups (0); 1188 1189 /* Write it out. */ 1190 expand_debug_syms (first.debug_sym_link, 1); 1191 gas_cgen_finish_insn (first.orig_insn, first.buffer, 1192 CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); 1193 1194 /* Force the top bit of the second insn to be set. */ 1195 if (parallel_p) 1196 make_parallel (second.buffer); 1197 1198 /* Get its fixups. */ 1199 gas_cgen_restore_fixups (0); 1200 1201 /* Write it out. */ 1202 expand_debug_syms (second.debug_sym_link, 1); 1203 gas_cgen_finish_insn (second.orig_insn, second.buffer, 1204 CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); 1205 } 1206 /* Try swapping the instructions to see if they work that way. */ 1207 else if (can_make_parallel (&second, &first) == NULL) 1208 { 1209 /* Write out the second instruction first. */ 1210 expand_debug_syms (second.debug_sym_link, 1); 1211 gas_cgen_finish_insn (second.orig_insn, second.buffer, 1212 CGEN_FIELDS_BITSIZE (&second.fields), 0, NULL); 1213 1214 /* Force the top bit of the first instruction to be set. */ 1215 make_parallel (first.buffer); 1216 1217 /* Get the fixups for the first instruction. */ 1218 gas_cgen_restore_fixups (0); 1219 1220 /* Write out the first instruction. */ 1221 expand_debug_syms (first.debug_sym_link, 1); 1222 gas_cgen_finish_insn (first.orig_insn, first.buffer, 1223 CGEN_FIELDS_BITSIZE (&first.fields), 0, NULL); 1224 } 1225 else 1226 { 1227 as_bad ("'%s': %s", str2, errmsg); 1228 return; 1229 } 1230 1231 if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL) 1232 || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL)) 1233 m32r_flags |= E_M32R_HAS_HIDDEN_INST; 1234 if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_M32R) 1235 || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_M32R)) 1236 m32r_flags |= E_M32R_HAS_BIT_INST; 1237 if (CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL_FLOAT) 1238 || CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL_FLOAT)) 1239 m32r_flags |= E_M32R_HAS_FLOAT_INST; 1240 1241 /* Set these so m32r_fill_insn can use them. */ 1242 prev_seg = now_seg; 1243 prev_subseg = now_subseg; 1244 } 1245 1246 void 1247 md_assemble (str) 1248 char *str; 1249 { 1250 m32r_insn insn; 1251 char *errmsg; 1252 char *str2 = NULL; 1253 1254 /* Initialize GAS's cgen interface for a new instruction. */ 1255 gas_cgen_init_parse (); 1256 1257 /* Look for a parallel instruction separator. */ 1258 if ((str2 = strstr (str, "||")) != NULL) 1259 { 1260 assemble_two_insns (str, str2, 1); 1261 m32r_flags |= E_M32R_HAS_PARALLEL; 1262 return; 1263 } 1264 1265 /* Also look for a sequential instruction separator. */ 1266 if ((str2 = strstr (str, "->")) != NULL) 1267 { 1268 assemble_two_insns (str, str2, 0); 1269 return; 1270 } 1271 1272 insn.debug_sym_link = debug_sym_link; 1273 debug_sym_link = (sym_linkS *) 0; 1274 1275 insn.insn = m32r_cgen_assemble_insn 1276 (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg); 1277 1278 if (!insn.insn) 1279 { 1280 as_bad (errmsg); 1281 return; 1282 } 1283 1284 #ifdef E_M32R2_ARCH 1285 if ((enable_m32rx == 1) 1286 /* FIXME: Need standard macro to perform this test. */ 1287 && ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) 1288 & (1 << MACH_M32R2)) 1289 && !((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) 1290 & (1 << MACH_M32RX))))) 1291 { 1292 /* xgettext:c-format */ 1293 as_bad (_("instruction '%s' is for the M32R2 only"), str); 1294 return; 1295 } 1296 else if ((! enable_special 1297 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) 1298 || (! enable_special_m32r 1299 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R))) 1300 #else 1301 if (! enable_special 1302 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) 1303 #endif 1304 { 1305 /* xgettext:c-format */ 1306 as_bad (_("unknown instruction '%s'"), str); 1307 return; 1308 } 1309 else if (! enable_m32rx 1310 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX)) 1311 { 1312 /* xgettext:c-format */ 1313 as_bad (_("instruction '%s' is for the M32RX only"), str); 1314 return; 1315 } 1316 1317 if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL)) 1318 m32r_flags |= E_M32R_HAS_HIDDEN_INST; 1319 if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_M32R)) 1320 m32r_flags |= E_M32R_HAS_BIT_INST; 1321 if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL_FLOAT)) 1322 m32r_flags |= E_M32R_HAS_FLOAT_INST; 1323 1324 if (CGEN_INSN_BITSIZE (insn.insn) == 32) 1325 { 1326 /* 32 bit insns must live on 32 bit boundaries. */ 1327 if (prev_insn.insn || seen_relaxable_p) 1328 { 1329 /* ??? If calling fill_insn too many times turns us into a memory 1330 pig, can we call a fn to assemble a nop instead of 1331 !seen_relaxable_p? */ 1332 fill_insn (0); 1333 } 1334 1335 expand_debug_syms (insn.debug_sym_link, 2); 1336 1337 /* Doesn't really matter what we pass for RELAX_P here. */ 1338 gas_cgen_finish_insn (insn.insn, insn.buffer, 1339 CGEN_FIELDS_BITSIZE (&insn.fields), 1, NULL); 1340 } 1341 else 1342 { 1343 int on_32bit_boundary_p; 1344 int swap = FALSE; 1345 1346 if (CGEN_INSN_BITSIZE (insn.insn) != 16) 1347 abort (); 1348 1349 insn.orig_insn = insn.insn; 1350 1351 /* If the previous insn was relaxable, then it may be expanded 1352 to fill the current 16 bit slot. Emit a NOP here to occupy 1353 this slot, so that we can start at optimizing at a 32 bit 1354 boundary. */ 1355 if (prev_insn.insn && seen_relaxable_p && optimize) 1356 fill_insn (0); 1357 1358 if (enable_m32rx) 1359 { 1360 /* Get the indices of the operands of the instruction. 1361 FIXME: See assemble_parallel for notes on orig_insn. */ 1362 { 1363 CGEN_FIELDS tmp_fields; 1364 insn.insn = cgen_lookup_get_insn_operands 1365 (gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL, 1366 16, insn.indices, &tmp_fields); 1367 } 1368 1369 if (insn.insn == NULL) 1370 as_fatal (_("internal error: lookup/get operands failed")); 1371 } 1372 1373 /* Compute whether we're on a 32 bit boundary or not. 1374 prev_insn.insn is NULL when we're on a 32 bit boundary. */ 1375 on_32bit_boundary_p = prev_insn.insn == NULL; 1376 1377 /* Look to see if this instruction can be combined with the 1378 previous instruction to make one, parallel, 32 bit instruction. 1379 If the previous instruction (potentially) changed the flow of 1380 program control, then it cannot be combined with the current 1381 instruction. If the current instruction is relaxable, then it 1382 might be replaced with a longer version, so we cannot combine it. 1383 Also if the output of the previous instruction is used as an 1384 input to the current instruction then it cannot be combined. 1385 Otherwise call can_make_parallel() with both orderings of the 1386 instructions to see if they can be combined. */ 1387 if (! on_32bit_boundary_p 1388 && parallel () 1389 && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0 1390 && ! writes_to_pc (&prev_insn) 1391 && ! first_writes_to_seconds_operands (&prev_insn, &insn, FALSE)) 1392 { 1393 if (can_make_parallel (&prev_insn, &insn) == NULL) 1394 make_parallel (insn.buffer); 1395 else if (can_make_parallel (&insn, &prev_insn) == NULL) 1396 swap = TRUE; 1397 } 1398 1399 expand_debug_syms (insn.debug_sym_link, 1); 1400 1401 { 1402 int i; 1403 finished_insnS fi; 1404 1405 /* Ensure each pair of 16 bit insns is in the same frag. */ 1406 frag_grow (4); 1407 1408 gas_cgen_finish_insn (insn.orig_insn, insn.buffer, 1409 CGEN_FIELDS_BITSIZE (&insn.fields), 1410 1 /* relax_p */, &fi); 1411 insn.addr = fi.addr; 1412 insn.frag = fi.frag; 1413 insn.num_fixups = fi.num_fixups; 1414 for (i = 0; i < fi.num_fixups; ++i) 1415 insn.fixups[i] = fi.fixups[i]; 1416 } 1417 1418 if (swap) 1419 { 1420 int i, tmp; 1421 1422 #define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp 1423 1424 /* Swap the two insns */ 1425 SWAP_BYTES (prev_insn.addr[0], insn.addr[0]); 1426 SWAP_BYTES (prev_insn.addr[1], insn.addr[1]); 1427 1428 target_make_parallel (insn.addr); 1429 1430 /* Swap any relaxable frags recorded for the two insns. */ 1431 /* FIXME: Clarify. relaxation precludes parallel insns */ 1432 if (prev_insn.frag->fr_opcode == prev_insn.addr) 1433 prev_insn.frag->fr_opcode = insn.addr; 1434 else if (insn.frag->fr_opcode == insn.addr) 1435 insn.frag->fr_opcode = prev_insn.addr; 1436 1437 /* Update the addresses in any fixups. 1438 Note that we don't have to handle the case where each insn is in 1439 a different frag as we ensure they're in the same frag above. */ 1440 for (i = 0; i < prev_insn.num_fixups; ++i) 1441 prev_insn.fixups[i]->fx_where += 2; 1442 for (i = 0; i < insn.num_fixups; ++i) 1443 insn.fixups[i]->fx_where -= 2; 1444 } 1445 1446 /* Keep track of whether we've seen a pair of 16 bit insns. 1447 prev_insn.insn is NULL when we're on a 32 bit boundary. */ 1448 if (on_32bit_boundary_p) 1449 prev_insn = insn; 1450 else 1451 prev_insn.insn = NULL; 1452 1453 /* If the insn needs the following one to be on a 32 bit boundary 1454 (e.g. subroutine calls), fill this insn's slot. */ 1455 if (on_32bit_boundary_p 1456 && CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_FILL_SLOT) != 0) 1457 fill_insn (0); 1458 1459 /* If this is a relaxable insn (can be replaced with a larger version) 1460 mark the fact so that we can emit an alignment directive for a 1461 following 32 bit insn if we see one. */ 1462 if (CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) != 0) 1463 seen_relaxable_p = 1; 1464 } 1465 1466 /* Set these so m32r_fill_insn can use them. */ 1467 prev_seg = now_seg; 1468 prev_subseg = now_subseg; 1469 } 1470 1471 /* The syntax in the manual says constants begin with '#'. 1472 We just ignore it. */ 1473 1474 void 1475 md_operand (expressionP) 1476 expressionS *expressionP; 1477 { 1478 if (*input_line_pointer == '#') 1479 { 1480 input_line_pointer++; 1481 expression (expressionP); 1482 } 1483 } 1484 1485 valueT 1486 md_section_align (segment, size) 1487 segT segment; 1488 valueT size; 1489 { 1490 int align = bfd_get_section_alignment (stdoutput, segment); 1491 return ((size + (1 << align) - 1) & (-1 << align)); 1492 } 1493 1494 symbolS * 1495 md_undefined_symbol (name) 1496 char *name ATTRIBUTE_UNUSED; 1497 { 1498 return 0; 1499 } 1500 1501 /* .scomm pseudo-op handler. 1502 1503 This is a new pseudo-op to handle putting objects in .scommon. 1504 By doing this the linker won't need to do any work, 1505 and more importantly it removes the implicit -G arg necessary to 1506 correctly link the object file. */ 1507 1508 static void 1509 m32r_scomm (ignore) 1510 int ignore ATTRIBUTE_UNUSED; 1511 { 1512 register char *name; 1513 register char c; 1514 register char *p; 1515 offsetT size; 1516 register symbolS *symbolP; 1517 offsetT align; 1518 int align2; 1519 1520 name = input_line_pointer; 1521 c = get_symbol_end (); 1522 1523 /* Just after name is now '\0'. */ 1524 p = input_line_pointer; 1525 *p = c; 1526 SKIP_WHITESPACE (); 1527 if (*input_line_pointer != ',') 1528 { 1529 as_bad (_("Expected comma after symbol-name: rest of line ignored.")); 1530 ignore_rest_of_line (); 1531 return; 1532 } 1533 1534 /* Skip ','. */ 1535 input_line_pointer++; 1536 if ((size = get_absolute_expression ()) < 0) 1537 { 1538 /* xgettext:c-format */ 1539 as_warn (_(".SCOMMon length (%ld.) <0! Ignored."), (long) size); 1540 ignore_rest_of_line (); 1541 return; 1542 } 1543 1544 /* The third argument to .scomm is the alignment. */ 1545 if (*input_line_pointer != ',') 1546 align = 8; 1547 else 1548 { 1549 ++input_line_pointer; 1550 align = get_absolute_expression (); 1551 if (align <= 0) 1552 { 1553 as_warn (_("ignoring bad alignment")); 1554 align = 8; 1555 } 1556 } 1557 1558 /* Convert to a power of 2 alignment. */ 1559 if (align) 1560 { 1561 for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2) 1562 continue; 1563 if (align != 1) 1564 { 1565 as_bad (_("Common alignment not a power of 2")); 1566 ignore_rest_of_line (); 1567 return; 1568 } 1569 } 1570 else 1571 align2 = 0; 1572 1573 *p = 0; 1574 symbolP = symbol_find_or_make (name); 1575 *p = c; 1576 1577 if (S_IS_DEFINED (symbolP)) 1578 { 1579 /* xgettext:c-format */ 1580 as_bad (_("Ignoring attempt to re-define symbol `%s'."), 1581 S_GET_NAME (symbolP)); 1582 ignore_rest_of_line (); 1583 return; 1584 } 1585 1586 if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) 1587 { 1588 /* xgettext:c-format */ 1589 as_bad (_("Length of .scomm \"%s\" is already %ld. Not changed to %ld."), 1590 S_GET_NAME (symbolP), 1591 (long) S_GET_VALUE (symbolP), 1592 (long) size); 1593 1594 ignore_rest_of_line (); 1595 return; 1596 } 1597 1598 if (symbol_get_obj (symbolP)->local) 1599 { 1600 segT old_sec = now_seg; 1601 int old_subsec = now_subseg; 1602 char *pfrag; 1603 1604 record_alignment (sbss_section, align2); 1605 subseg_set (sbss_section, 0); 1606 1607 if (align2) 1608 frag_align (align2, 0, 0); 1609 1610 if (S_GET_SEGMENT (symbolP) == sbss_section) 1611 symbol_get_frag (symbolP)->fr_symbol = 0; 1612 1613 symbol_set_frag (symbolP, frag_now); 1614 1615 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, 1616 (char *) 0); 1617 *pfrag = 0; 1618 S_SET_SIZE (symbolP, size); 1619 S_SET_SEGMENT (symbolP, sbss_section); 1620 S_CLEAR_EXTERNAL (symbolP); 1621 subseg_set (old_sec, old_subsec); 1622 } 1623 else 1624 { 1625 S_SET_VALUE (symbolP, (valueT) size); 1626 S_SET_ALIGN (symbolP, align2); 1627 S_SET_EXTERNAL (symbolP); 1628 S_SET_SEGMENT (symbolP, &scom_section); 1629 } 1630 1631 demand_empty_rest_of_line (); 1632 } 1633 1634 /* Interface to relax_segment. */ 1635 1636 /* FIXME: Build table by hand, get it working, then machine generate. */ 1637 1638 const relax_typeS md_relax_table[] = 1639 { 1640 /* The fields are: 1641 1) most positive reach of this state, 1642 2) most negative reach of this state, 1643 3) how many bytes this mode will add to the size of the current frag 1644 4) which index into the table to try if we can't fit into this one. */ 1645 1646 /* The first entry must be unused because an `rlx_more' value of zero ends 1647 each list. */ 1648 {1, 1, 0, 0}, 1649 1650 /* The displacement used by GAS is from the end of the 2 byte insn, 1651 so we subtract 2 from the following. */ 1652 /* 16 bit insn, 8 bit disp -> 10 bit range. 1653 This doesn't handle a branch in the right slot at the border: 1654 the "& -4" isn't taken into account. It's not important enough to 1655 complicate things over it, so we subtract an extra 2 (or + 2 in -ve 1656 case). */ 1657 {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, 1658 /* 32 bit insn, 24 bit disp -> 26 bit range. */ 1659 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, 1660 /* Same thing, but with leading nop for alignment. */ 1661 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } 1662 }; 1663 1664 long 1665 m32r_relax_frag (segment, fragP, stretch) 1666 segT segment; 1667 fragS *fragP; 1668 long stretch; 1669 { 1670 /* Address of branch insn. */ 1671 long address = fragP->fr_address + fragP->fr_fix - 2; 1672 long growth = 0; 1673 1674 /* Keep 32 bit insns aligned on 32 bit boundaries. */ 1675 if (fragP->fr_subtype == 2) 1676 { 1677 if ((address & 3) != 0) 1678 { 1679 fragP->fr_subtype = 3; 1680 growth = 2; 1681 } 1682 } 1683 else if (fragP->fr_subtype == 3) 1684 { 1685 if ((address & 3) == 0) 1686 { 1687 fragP->fr_subtype = 2; 1688 growth = -2; 1689 } 1690 } 1691 else 1692 { 1693 growth = relax_frag (segment, fragP, stretch); 1694 1695 /* Long jump on odd halfword boundary? */ 1696 if (fragP->fr_subtype == 2 && (address & 3) != 0) 1697 { 1698 fragP->fr_subtype = 3; 1699 growth += 2; 1700 } 1701 } 1702 1703 return growth; 1704 } 1705 1706 /* Return an initial guess of the length by which a fragment must grow to 1707 hold a branch to reach its destination. 1708 Also updates fr_type/fr_subtype as necessary. 1709 1710 Called just before doing relaxation. 1711 Any symbol that is now undefined will not become defined. 1712 The guess for fr_var is ACTUALLY the growth beyond fr_fix. 1713 Whatever we do to grow fr_fix or fr_var contributes to our returned value. 1714 Although it may not be explicit in the frag, pretend fr_var starts 1715 with a 0 value. */ 1716 1717 int 1718 md_estimate_size_before_relax (fragP, segment) 1719 fragS *fragP; 1720 segT segment; 1721 { 1722 /* The only thing we have to handle here are symbols outside of the 1723 current segment. They may be undefined or in a different segment in 1724 which case linker scripts may place them anywhere. 1725 However, we can't finish the fragment here and emit the reloc as insn 1726 alignment requirements may move the insn about. */ 1727 1728 if (S_GET_SEGMENT (fragP->fr_symbol) != segment 1729 || S_IS_EXTERNAL (fragP->fr_symbol) 1730 || S_IS_WEAK (fragP->fr_symbol)) 1731 { 1732 #if 0 1733 int old_fr_fix = fragP->fr_fix; 1734 #endif 1735 1736 /* The symbol is undefined in this segment. 1737 Change the relaxation subtype to the max allowable and leave 1738 all further handling to md_convert_frag. */ 1739 fragP->fr_subtype = 2; 1740 1741 #if 0 1742 /* Can't use this, but leave in for illustration. */ 1743 /* Change 16 bit insn to 32 bit insn. */ 1744 fragP->fr_opcode[0] |= 0x80; 1745 1746 /* Increase known (fixed) size of fragment. */ 1747 fragP->fr_fix += 2; 1748 1749 /* Create a relocation for it. */ 1750 fix_new (fragP, old_fr_fix, 4, 1751 fragP->fr_symbol, 1752 fragP->fr_offset, 1 /* pcrel */, 1753 /* FIXME: Can't use a real BFD reloc here. 1754 gas_cgen_md_apply_fix3 can't handle it. */ 1755 BFD_RELOC_M32R_26_PCREL); 1756 1757 /* Mark this fragment as finished. */ 1758 frag_wane (fragP); 1759 return fragP->fr_fix - old_fr_fix; 1760 #else 1761 { 1762 const CGEN_INSN *insn; 1763 int i; 1764 1765 /* Update the recorded insn. 1766 Fortunately we don't have to look very far. 1767 FIXME: Change this to record in the instruction the next higher 1768 relaxable insn to use. */ 1769 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) 1770 { 1771 if ((strcmp (CGEN_INSN_MNEMONIC (insn), 1772 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) 1773 == 0) 1774 && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED)) 1775 break; 1776 } 1777 if (i == 4) 1778 abort (); 1779 1780 fragP->fr_cgen.insn = insn; 1781 return 2; 1782 } 1783 #endif 1784 } 1785 1786 return md_relax_table[fragP->fr_subtype].rlx_length; 1787 } 1788 1789 /* *FRAGP has been relaxed to its final size, and now needs to have 1790 the bytes inside it modified to conform to the new size. 1791 1792 Called after relaxation is finished. 1793 fragP->fr_type == rs_machine_dependent. 1794 fragP->fr_subtype is the subtype of what the address relaxed to. */ 1795 1796 void 1797 md_convert_frag (abfd, sec, fragP) 1798 bfd *abfd ATTRIBUTE_UNUSED; 1799 segT sec; 1800 fragS *fragP; 1801 { 1802 char *opcode; 1803 char *displacement; 1804 int target_address; 1805 int opcode_address; 1806 int extension; 1807 int addend; 1808 1809 opcode = fragP->fr_opcode; 1810 1811 /* Address opcode resides at in file space. */ 1812 opcode_address = fragP->fr_address + fragP->fr_fix - 2; 1813 1814 switch (fragP->fr_subtype) 1815 { 1816 case 1: 1817 extension = 0; 1818 displacement = &opcode[1]; 1819 break; 1820 case 2: 1821 opcode[0] |= 0x80; 1822 extension = 2; 1823 displacement = &opcode[1]; 1824 break; 1825 case 3: 1826 opcode[2] = opcode[0] | 0x80; 1827 md_number_to_chars (opcode, PAR_NOP_INSN, 2); 1828 opcode_address += 2; 1829 extension = 4; 1830 displacement = &opcode[3]; 1831 break; 1832 default: 1833 abort (); 1834 } 1835 1836 if (S_GET_SEGMENT (fragP->fr_symbol) != sec 1837 || S_IS_EXTERNAL (fragP->fr_symbol) 1838 || S_IS_WEAK (fragP->fr_symbol)) 1839 { 1840 /* Symbol must be resolved by linker. */ 1841 if (fragP->fr_offset & 3) 1842 as_warn (_("Addend to unresolved symbol not on word boundary.")); 1843 #ifdef USE_M32R_OLD_RELOC 1844 addend = fragP->fr_offset >> 2; /* Old M32R used USE_REL. */ 1845 #else 1846 addend = 0; 1847 #endif 1848 } 1849 else 1850 { 1851 /* Address we want to reach in file space. */ 1852 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; 1853 addend = (target_address - (opcode_address & -4)) >> 2; 1854 } 1855 1856 /* Create a relocation for symbols that must be resolved by the linker. 1857 Otherwise output the completed insn. */ 1858 1859 if (S_GET_SEGMENT (fragP->fr_symbol) != sec 1860 || S_IS_EXTERNAL (fragP->fr_symbol) 1861 || S_IS_WEAK (fragP->fr_symbol)) 1862 { 1863 assert (fragP->fr_subtype != 1); 1864 assert (fragP->fr_cgen.insn != 0); 1865 gas_cgen_record_fixup (fragP, 1866 /* Offset of branch insn in frag. */ 1867 fragP->fr_fix + extension - 4, 1868 fragP->fr_cgen.insn, 1869 4 /* Length. */, 1870 /* FIXME: quick hack. */ 1871 #if 0 1872 cgen_operand_lookup_by_num (gas_cgen_cpu_desc, 1873 fragP->fr_cgen.opindex), 1874 #else 1875 cgen_operand_lookup_by_num (gas_cgen_cpu_desc, 1876 M32R_OPERAND_DISP24), 1877 #endif 1878 fragP->fr_cgen.opinfo, 1879 fragP->fr_symbol, fragP->fr_offset); 1880 } 1881 1882 #define SIZE_FROM_RELAX_STATE(n) ((n) == 1 ? 1 : 3) 1883 1884 md_number_to_chars (displacement, (valueT) addend, 1885 SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); 1886 1887 fragP->fr_fix += extension; 1888 } 1889 1890 /* Functions concerning relocs. */ 1891 1892 /* The location from which a PC relative jump should be calculated, 1893 given a PC relative reloc. */ 1894 1895 long 1896 md_pcrel_from_section (fixP, sec) 1897 fixS *fixP; 1898 segT sec; 1899 { 1900 if (fixP->fx_addsy != (symbolS *) NULL 1901 && (! S_IS_DEFINED (fixP->fx_addsy) 1902 || S_GET_SEGMENT (fixP->fx_addsy) != sec 1903 || S_IS_EXTERNAL (fixP->fx_addsy) 1904 || S_IS_WEAK (fixP->fx_addsy))) 1905 { 1906 /* The symbol is undefined (or is defined but not in this section). 1907 Let the linker figure it out. */ 1908 return 0; 1909 } 1910 1911 return (fixP->fx_frag->fr_address + fixP->fx_where) & -4L; 1912 } 1913 1914 /* Return the bfd reloc type for OPERAND of INSN at fixup FIXP. 1915 Returns BFD_RELOC_NONE if no reloc type can be found. 1916 *FIXP may be modified if desired. */ 1917 1918 bfd_reloc_code_real_type 1919 md_cgen_lookup_reloc (insn, operand, fixP) 1920 const CGEN_INSN *insn ATTRIBUTE_UNUSED; 1921 const CGEN_OPERAND *operand; 1922 fixS *fixP; 1923 { 1924 switch (operand->type) 1925 { 1926 case M32R_OPERAND_DISP8: return BFD_RELOC_M32R_10_PCREL; 1927 case M32R_OPERAND_DISP16: return BFD_RELOC_M32R_18_PCREL; 1928 case M32R_OPERAND_DISP24: return BFD_RELOC_M32R_26_PCREL; 1929 case M32R_OPERAND_UIMM24: return BFD_RELOC_M32R_24; 1930 case M32R_OPERAND_HI16: 1931 case M32R_OPERAND_SLO16: 1932 case M32R_OPERAND_ULO16: 1933 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ 1934 if (fixP->fx_cgen.opinfo != 0) 1935 return fixP->fx_cgen.opinfo; 1936 break; 1937 default: 1938 /* Avoid -Wall warning. */ 1939 break; 1940 } 1941 return BFD_RELOC_NONE; 1942 } 1943 1944 /* Record a HI16 reloc for later matching with its LO16 cousin. */ 1945 1946 static void m32r_record_hi16 PARAMS ((int, fixS *, segT)); 1947 1948 static void 1949 m32r_record_hi16 (reloc_type, fixP, seg) 1950 int reloc_type; 1951 fixS *fixP; 1952 segT seg ATTRIBUTE_UNUSED; 1953 { 1954 struct m32r_hi_fixup *hi_fixup; 1955 1956 assert (reloc_type == BFD_RELOC_M32R_HI16_SLO 1957 || reloc_type == BFD_RELOC_M32R_HI16_ULO); 1958 1959 hi_fixup = ((struct m32r_hi_fixup *) 1960 xmalloc (sizeof (struct m32r_hi_fixup))); 1961 hi_fixup->fixp = fixP; 1962 hi_fixup->seg = now_seg; 1963 hi_fixup->next = m32r_hi_fixup_list; 1964 1965 m32r_hi_fixup_list = hi_fixup; 1966 } 1967 1968 /* Called while parsing an instruction to create a fixup. 1969 We need to check for HI16 relocs and queue them up for later sorting. */ 1970 1971 fixS * 1972 m32r_cgen_record_fixup_exp (frag, where, insn, length, operand, opinfo, exp) 1973 fragS *frag; 1974 int where; 1975 const CGEN_INSN *insn; 1976 int length; 1977 const CGEN_OPERAND *operand; 1978 int opinfo; 1979 expressionS *exp; 1980 { 1981 fixS *fixP = gas_cgen_record_fixup_exp (frag, where, insn, length, 1982 operand, opinfo, exp); 1983 1984 switch (operand->type) 1985 { 1986 case M32R_OPERAND_HI16: 1987 /* If low/high/shigh/sda was used, it is recorded in `opinfo'. */ 1988 if (fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_SLO 1989 || fixP->fx_cgen.opinfo == BFD_RELOC_M32R_HI16_ULO) 1990 m32r_record_hi16 (fixP->fx_cgen.opinfo, fixP, now_seg); 1991 break; 1992 default: 1993 /* Avoid -Wall warning */ 1994 break; 1995 } 1996 1997 return fixP; 1998 } 1999 2000 /* Return BFD reloc type from opinfo field in a fixS. 2001 It's tricky using fx_r_type in m32r_frob_file because the values 2002 are BFD_RELOC_UNUSED + operand number. */ 2003 #define FX_OPINFO_R_TYPE(f) ((f)->fx_cgen.opinfo) 2004 2005 /* Sort any unmatched HI16 relocs so that they immediately precede 2006 the corresponding LO16 reloc. This is called before md_apply_fix3 and 2007 tc_gen_reloc. */ 2008 2009 void 2010 m32r_frob_file () 2011 { 2012 struct m32r_hi_fixup *l; 2013 2014 for (l = m32r_hi_fixup_list; l != NULL; l = l->next) 2015 { 2016 segment_info_type *seginfo; 2017 int pass; 2018 2019 assert (FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_SLO 2020 || FX_OPINFO_R_TYPE (l->fixp) == BFD_RELOC_M32R_HI16_ULO); 2021 2022 /* Check quickly whether the next fixup happens to be a matching low. */ 2023 if (l->fixp->fx_next != NULL 2024 && FX_OPINFO_R_TYPE (l->fixp->fx_next) == BFD_RELOC_M32R_LO16 2025 && l->fixp->fx_addsy == l->fixp->fx_next->fx_addsy 2026 && l->fixp->fx_offset == l->fixp->fx_next->fx_offset) 2027 continue; 2028 2029 /* Look through the fixups for this segment for a matching `low'. 2030 When we find one, move the high/shigh just in front of it. We do 2031 this in two passes. In the first pass, we try to find a 2032 unique `low'. In the second pass, we permit multiple high's 2033 relocs for a single `low'. */ 2034 seginfo = seg_info (l->seg); 2035 for (pass = 0; pass < 2; pass++) 2036 { 2037 fixS *f; 2038 fixS *prev; 2039 2040 prev = NULL; 2041 for (f = seginfo->fix_root; f != NULL; f = f->fx_next) 2042 { 2043 /* Check whether this is a `low' fixup which matches l->fixp. */ 2044 if (FX_OPINFO_R_TYPE (f) == BFD_RELOC_M32R_LO16 2045 && f->fx_addsy == l->fixp->fx_addsy 2046 && f->fx_offset == l->fixp->fx_offset 2047 && (pass == 1 2048 || prev == NULL 2049 || (FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_SLO 2050 && FX_OPINFO_R_TYPE (prev) != BFD_RELOC_M32R_HI16_ULO) 2051 || prev->fx_addsy != f->fx_addsy 2052 || prev->fx_offset != f->fx_offset)) 2053 { 2054 fixS **pf; 2055 2056 /* Move l->fixp before f. */ 2057 for (pf = &seginfo->fix_root; 2058 *pf != l->fixp; 2059 pf = & (*pf)->fx_next) 2060 assert (*pf != NULL); 2061 2062 *pf = l->fixp->fx_next; 2063 2064 l->fixp->fx_next = f; 2065 if (prev == NULL) 2066 seginfo->fix_root = l->fixp; 2067 else 2068 prev->fx_next = l->fixp; 2069 2070 break; 2071 } 2072 2073 prev = f; 2074 } 2075 2076 if (f != NULL) 2077 break; 2078 2079 if (pass == 1 2080 && warn_unmatched_high) 2081 as_warn_where (l->fixp->fx_file, l->fixp->fx_line, 2082 _("Unmatched high/shigh reloc")); 2083 } 2084 } 2085 } 2086 2087 /* See whether we need to force a relocation into the output file. 2088 This is used to force out switch and PC relative relocations when 2089 relaxing. */ 2090 2091 int 2092 m32r_force_relocation (fix) 2093 fixS *fix; 2094 { 2095 if (generic_force_reloc (fix)) 2096 return 1; 2097 2098 if (! m32r_relax) 2099 return 0; 2100 2101 return fix->fx_pcrel; 2102 } 2103 2104 /* Write a value out to the object file, using the appropriate endianness. */ 2105 2106 void 2107 md_number_to_chars (buf, val, n) 2108 char *buf; 2109 valueT val; 2110 int n; 2111 { 2112 if (target_big_endian) 2113 number_to_chars_bigendian (buf, val, n); 2114 else 2115 number_to_chars_littleendian (buf, val, n); 2116 } 2117 2118 /* Turn a string in input_line_pointer into a floating point constant 2119 of type TYPE, and store the appropriate bytes in *LITP. The number 2120 of LITTLENUMS emitted is stored in *SIZEP. An error message is 2121 returned, or NULL on OK. */ 2122 2123 /* Equal to MAX_PRECISION in atof-ieee.c. */ 2124 #define MAX_LITTLENUMS 6 2125 2126 char * 2127 md_atof (type, litP, sizeP) 2128 char type; 2129 char *litP; 2130 int *sizeP; 2131 { 2132 int i; 2133 int prec; 2134 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 2135 char *t; 2136 2137 switch (type) 2138 { 2139 case 'f': 2140 case 'F': 2141 case 's': 2142 case 'S': 2143 prec = 2; 2144 break; 2145 2146 case 'd': 2147 case 'D': 2148 case 'r': 2149 case 'R': 2150 prec = 4; 2151 break; 2152 2153 /* FIXME: Some targets allow other format chars for bigger sizes 2154 here. */ 2155 2156 default: 2157 *sizeP = 0; 2158 return _("Bad call to md_atof()"); 2159 } 2160 2161 t = atof_ieee (input_line_pointer, type, words); 2162 if (t) 2163 input_line_pointer = t; 2164 *sizeP = prec * sizeof (LITTLENUM_TYPE); 2165 2166 if (target_big_endian) 2167 { 2168 for (i = 0; i < prec; i++) 2169 { 2170 md_number_to_chars (litP, (valueT) words[i], 2171 sizeof (LITTLENUM_TYPE)); 2172 litP += sizeof (LITTLENUM_TYPE); 2173 } 2174 } 2175 else 2176 { 2177 for (i = prec - 1; i >= 0; i--) 2178 { 2179 md_number_to_chars (litP, (valueT) words[i], 2180 sizeof (LITTLENUM_TYPE)); 2181 litP += sizeof (LITTLENUM_TYPE); 2182 } 2183 } 2184 2185 return 0; 2186 } 2187 2188 void 2189 m32r_elf_section_change_hook () 2190 { 2191 /* If we have reached the end of a section and we have just emitted a 2192 16 bit insn, then emit a nop to make sure that the section ends on 2193 a 32 bit boundary. */ 2194 2195 if (prev_insn.insn || seen_relaxable_p) 2196 (void) m32r_fill_insn (0); 2197 } 2198 2199 /* Return true if can adjust the reloc to be relative to its section 2200 (such as .data) instead of relative to some symbol. */ 2201 2202 bfd_boolean 2203 m32r_fix_adjustable (fixP) 2204 fixS *fixP; 2205 { 2206 bfd_reloc_code_real_type reloc_type; 2207 2208 if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) 2209 { 2210 const CGEN_INSN *insn = NULL; 2211 int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; 2212 const CGEN_OPERAND *operand = 2213 cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex); 2214 reloc_type = md_cgen_lookup_reloc (insn, operand, fixP); 2215 } 2216 else 2217 reloc_type = fixP->fx_r_type; 2218 2219 if (fixP->fx_addsy == NULL) 2220 return 1; 2221 2222 /* Prevent all adjustments to global symbols. */ 2223 if (S_IS_EXTERN (fixP->fx_addsy)) 2224 return 0; 2225 if (S_IS_WEAK (fixP->fx_addsy)) 2226 return 0; 2227 2228 if (pic_code 2229 && (reloc_type == BFD_RELOC_M32R_24 2230 || reloc_type == BFD_RELOC_M32R_26_PCREL 2231 || reloc_type == BFD_RELOC_M32R_HI16_SLO 2232 || reloc_type == BFD_RELOC_M32R_HI16_ULO 2233 || reloc_type == BFD_RELOC_M32R_LO16)) 2234 return 0; 2235 2236 /* We need the symbol name for the VTABLE entries. */ 2237 if (reloc_type == BFD_RELOC_VTABLE_INHERIT 2238 || reloc_type == BFD_RELOC_VTABLE_ENTRY) 2239 return 0; 2240 2241 return 1; 2242 } 2243 2244 void 2245 m32r_elf_final_processing () 2246 { 2247 if (use_parallel) 2248 m32r_flags |= E_M32R_HAS_PARALLEL; 2249 elf_elfheader (stdoutput)->e_flags |= m32r_flags; 2250 } 2251 2252 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 2253 2254 /* Translate internal representation of relocation info to BFD target 2255 format. */ 2256 arelent * 2257 tc_gen_reloc (section, fixP) 2258 asection * section; 2259 fixS * fixP; 2260 { 2261 arelent * reloc; 2262 bfd_reloc_code_real_type code; 2263 2264 reloc = (arelent *) xmalloc (sizeof (arelent)); 2265 2266 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 2267 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); 2268 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where; 2269 2270 code = fixP->fx_r_type; 2271 if (pic_code) 2272 { 2273 #ifdef DEBUG_PIC 2274 printf("%s",bfd_get_reloc_code_name(code)); 2275 #endif 2276 switch (code) 2277 { 2278 case BFD_RELOC_M32R_26_PCREL: 2279 code = BFD_RELOC_M32R_26_PLTREL; 2280 break; 2281 case BFD_RELOC_M32R_24: 2282 if (fixP->fx_addsy != NULL 2283 && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) 2284 code = BFD_RELOC_M32R_GOTPC24; 2285 else 2286 code = BFD_RELOC_M32R_GOT24; 2287 break; 2288 case BFD_RELOC_M32R_HI16_ULO: 2289 if (fixP->fx_addsy != NULL 2290 && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) 2291 code = BFD_RELOC_M32R_GOTPC_HI_ULO; 2292 else 2293 code = BFD_RELOC_M32R_GOT16_HI_ULO; 2294 break; 2295 case BFD_RELOC_M32R_HI16_SLO: 2296 if (fixP->fx_addsy != NULL 2297 && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) 2298 code = BFD_RELOC_M32R_GOTPC_HI_SLO; 2299 else 2300 code = BFD_RELOC_M32R_GOT16_HI_SLO; 2301 break; 2302 case BFD_RELOC_M32R_LO16: 2303 if (fixP->fx_addsy != NULL 2304 && strcmp (S_GET_NAME (fixP->fx_addsy), GOT_NAME) == 0) 2305 code = BFD_RELOC_M32R_GOTPC_LO; 2306 else 2307 code = BFD_RELOC_M32R_GOT16_LO; 2308 break; 2309 default: 2310 break; 2311 } 2312 #ifdef DEBUG_PIC 2313 printf(" => %s",bfd_get_reloc_code_name(code)); 2314 #endif 2315 } 2316 2317 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 2318 #ifdef DEBUG_PIC 2319 printf(" => %s\n",reloc->howto->name); 2320 #endif 2321 if (reloc->howto == (reloc_howto_type *) NULL) 2322 { 2323 as_bad_where (fixP->fx_file, fixP->fx_line, 2324 _("internal error: can't export reloc type %d (`%s')"), 2325 fixP->fx_r_type, bfd_get_reloc_code_name (code)); 2326 return NULL; 2327 } 2328 2329 /* Use fx_offset for these cases */ 2330 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY 2331 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT) 2332 reloc->addend = fixP->fx_offset; 2333 else if (!pic_code 2334 && fixP->fx_pcrel 2335 && fixP->fx_addsy != NULL 2336 && (S_GET_SEGMENT(fixP->fx_addsy) != section) 2337 && S_IS_DEFINED (fixP->fx_addsy) 2338 && ! S_IS_EXTERNAL(fixP->fx_addsy) 2339 && ! S_IS_WEAK(fixP->fx_addsy)) 2340 /* already used fx_offset in the opcode field itseld. */ 2341 reloc->addend = 0; 2342 else 2343 reloc->addend = fixP->fx_addnumber; 2344 2345 return reloc; 2346 } 2347