1@c Copyright (C) 1991, 92, 93, 94, 95, 1997 Free Software Foundation, Inc. 2@c This is part of the GAS manual. 3@c For copying conditions, see the file as.texinfo. 4@ifset GENERIC 5@page 6@node MIPS-Dependent 7@chapter MIPS Dependent Features 8@end ifset 9@ifclear GENERIC 10@node Machine Dependencies 11@chapter MIPS Dependent Features 12@end ifclear 13 14@cindex MIPS processor 15@sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several 16different @sc{mips} processors, and MIPS ISA levels I through IV. For 17information about the @sc{mips} instruction set, see @cite{MIPS RISC 18Architecture}, by Kane and Heindrich (Prentice-Hall). For an overview 19of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language 20Programming'' in the same work. 21 22@menu 23* MIPS Opts:: Assembler options 24* MIPS Object:: ECOFF object code 25* MIPS Stabs:: Directives for debugging information 26* MIPS ISA:: Directives to override the ISA level 27* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 28* MIPS insn:: Directive to mark data as an instruction 29* MIPS option stack:: Directives to save and restore options 30@end menu 31 32@node MIPS Opts 33@section Assembler options 34 35The @sc{mips} configurations of @sc{gnu} @code{@value{AS}} support these 36special options: 37 38@table @code 39@cindex @code{-G} option (MIPS) 40@item -G @var{num} 41This option sets the largest size of an object that can be referenced 42implicitly with the @code{gp} register. It is only accepted for targets 43that use @sc{ecoff} format. The default value is 8. 44 45@cindex @code{-EB} option (MIPS) 46@cindex @code{-EL} option (MIPS) 47@cindex MIPS big-endian output 48@cindex MIPS little-endian output 49@cindex big-endian output, MIPS 50@cindex little-endian output, MIPS 51@item -EB 52@itemx -EL 53Any @sc{mips} configuration of @code{@value{AS}} can select big-endian or 54little-endian output at run time (unlike the other @sc{gnu} development 55tools, which must be configured for one or the other). Use @samp{-EB} 56to select big-endian output, and @samp{-EL} for little-endian. 57 58@cindex MIPS architecture options 59@item -mips1 60@itemx -mips2 61@itemx -mips3 62@itemx -mips4 63Generate code for a particular MIPS Instruction Set Architecture level. 64@samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, 65@samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the 66@sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and 67@sc{r10000} processors. You can also switch instruction sets during the 68assembly; see @ref{MIPS ISA,, Directives to override the ISA level}. 69 70@item -mgp32 71Assume that 32-bit general purpose registers are available. This 72affects synthetic instructions such as @code{move}, which will assemble 73to a 32-bit or a 64-bit instruction depending on this flag. On some 74MIPS variants there is a 32-bit mode flag; when this flag is set, 7564-bit instructions generate a trap. Also, some 32-bit OSes only save 76the 32-bit registers on a context switch, so it is essential never to 77use the 64-bit registers. 78 79@item -mgp64 80Assume that 64-bit general purpose registers are available. This is 81provided in the interests of symmetry with -gp32. 82 83@item -mips16 84@itemx -no-mips16 85Generate code for the MIPS 16 processor. This is equivalent to putting 86@samp{.set mips16} at the start of the assembly file. @samp{-no-mips16} 87turns off this option. 88 89@item -mfix7000 90@itemx -no-mfix7000 91Cause nops to be inserted if the read of the destination register 92of an mfhi or mflo instruction occurs in the following two instructions. 93 94@item -m4010 95@itemx -no-m4010 96Generate code for the LSI @sc{r4010} chip. This tells the assembler to 97accept the @sc{r4010} specific instructions (@samp{addciu}, @samp{ffc}, 98etc.), and to not schedule @samp{nop} instructions around accesses to 99the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this 100option. 101 102@item -m4650 103@itemx -no-m4650 104Generate code for the MIPS @sc{r4650} chip. This tells the assembler to accept 105the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} 106instructions around accesses to the @samp{HI} and @samp{LO} registers. 107@samp{-no-m4650} turns off this option. 108 109@itemx -m3900 110@itemx -no-m3900 111@itemx -m4100 112@itemx -no-m4100 113For each option @samp{-m@var{nnnn}}, generate code for the MIPS 114@sc{r@var{nnnn}} chip. This tells the assembler to accept instructions 115specific to that chip, and to schedule for that chip's hazards. 116 117@item -mcpu=@var{cpu} 118Generate code for a particular MIPS cpu. It is exactly equivalent to 119@samp{-m@var{cpu}}, except that there are more value of @var{cpu} 120understood. Valid @var{cpu} value are: 121 122@quotation 1232000, 1243000, 1253900, 1264000, 1274010, 1284100, 1294111, 1304300, 1314400, 1324600, 1334650, 1345000, 1356000, 1368000, 13710000 138@end quotation 139 140 141@cindex @code{-nocpp} ignored (MIPS) 142@item -nocpp 143This option is ignored. It is accepted for command-line compatibility with 144other assemblers, which use it to turn off C style preprocessing. With 145@sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the 146@sc{gnu} assembler itself never runs the C preprocessor. 147 148@item --trap 149@itemx --no-break 150@c FIXME! (1) reflect these options (next item too) in option summaries; 151@c (2) stop teasing, say _which_ instructions expanded _how_. 152@code{@value{AS}} automatically macro expands certain division and 153multiplication instructions to check for overflow and division by zero. This 154option causes @code{@value{AS}} to generate code to take a trap exception 155rather than a break exception when an error is detected. The trap instructions 156are only supported at Instruction Set Architecture level 2 and higher. 157 158@item --break 159@itemx --no-trap 160Generate code to take a break exception rather than a trap exception when an 161error is detected. This is the default. 162@end table 163 164@node MIPS Object 165@section MIPS ECOFF object code 166 167@cindex ECOFF sections 168@cindex MIPS ECOFF sections 169Assembling for a @sc{mips} @sc{ecoff} target supports some additional sections 170besides the usual @code{.text}, @code{.data} and @code{.bss}. The 171additional sections are @code{.rdata}, used for read-only data, 172@code{.sdata}, used for small data, and @code{.sbss}, used for small 173common objects. 174 175@cindex small objects, MIPS ECOFF 176@cindex @code{gp} register, MIPS 177When assembling for @sc{ecoff}, the assembler uses the @code{$gp} (@code{$28}) 178register to form the address of a ``small object''. Any object in the 179@code{.sdata} or @code{.sbss} sections is considered ``small'' in this sense. 180For external objects, or for objects in the @code{.bss} section, you can use 181the @code{@value{GCC}} @samp{-G} option to control the size of objects addressed via 182@code{$gp}; the default value is 8, meaning that a reference to any object 183eight bytes or smaller uses @code{$gp}. Passing @samp{-G 0} to 184@code{@value{AS}} prevents it from using the @code{$gp} register on the basis 185of object size (but the assembler uses @code{$gp} for objects in @code{.sdata} 186or @code{sbss} in any case). The size of an object in the @code{.bss} section 187is set by the @code{.comm} or @code{.lcomm} directive that defines it. The 188size of an external object may be set with the @code{.extern} directive. For 189example, @samp{.extern sym,4} declares that the object at @code{sym} is 4 bytes 190in length, whie leaving @code{sym} otherwise undefined. 191 192Using small @sc{ecoff} objects requires linker support, and assumes that the 193@code{$gp} register is correctly initialized (normally done automatically by 194the startup code). @sc{mips} @sc{ecoff} assembly code must not modify the 195@code{$gp} register. 196 197@node MIPS Stabs 198@section Directives for debugging information 199 200@cindex MIPS debugging directives 201@sc{mips} @sc{ecoff} @code{@value{AS}} supports several directives used for 202generating debugging information which are not support by traditional @sc{mips} 203assemblers. These are @code{.def}, @code{.endef}, @code{.dim}, @code{.file}, 204@code{.scl}, @code{.size}, @code{.tag}, @code{.type}, @code{.val}, 205@code{.stabd}, @code{.stabn}, and @code{.stabs}. The debugging information 206generated by the three @code{.stab} directives can only be read by @sc{gdb}, 207not by traditional @sc{mips} debuggers (this enhancement is required to fully 208support C++ debugging). These directives are primarily used by compilers, not 209assembly language programmers! 210 211@node MIPS ISA 212@section Directives to override the ISA level 213 214@cindex MIPS ISA override 215@kindex @code{.set mips@var{n}} 216@sc{gnu} @code{@value{AS}} supports an additional directive to change 217the @sc{mips} Instruction Set Architecture level on the fly: @code{.set 218mips@var{n}}. @var{n} should be a number from 0 to 4. A value from 1 219to 4 makes the assembler accept instructions for the corresponding 220@sc{isa} level, from that point on in the assembly. @code{.set 221mips@var{n}} affects not only which instructions are permitted, but also 222how certain macros are expanded. @code{.set mips0} restores the 223@sc{isa} level to its original level: either the level you selected with 224command line options, or the default for your configuration. You can 225use this feature to permit specific @sc{r4000} instructions while 226assembling in 32 bit mode. Use this directive with care! 227 228The directive @samp{.set mips16} puts the assembler into MIPS 16 mode, 229in which it will assemble instructions for the MIPS 16 processor. Use 230@samp{.set nomips16} to return to normal 32 bit mode. 231 232Traditional @sc{mips} assemblers do not support this directive. 233 234@node MIPS autoextend 235@section Directives for extending MIPS 16 bit instructions 236 237@kindex @code{.set autoextend} 238@kindex @code{.set noautoextend} 239By default, MIPS 16 instructions are automatically extended to 32 bits 240when necessary. The directive @samp{.set noautoextend} will turn this 241off. When @samp{.set noautoextend} is in effect, any 32 bit instruction 242must be explicitly extended with the @samp{.e} modifier (e.g., 243@samp{li.e $4,1000}). The directive @samp{.set autoextend} may be used 244to once again automatically extend instructions when necessary. 245 246This directive is only meaningful when in MIPS 16 mode. Traditional 247@sc{mips} assemblers do not support this directive. 248 249@node MIPS insn 250@section Directive to mark data as an instruction 251 252@kindex @code{.insn} 253The @code{.insn} directive tells @code{@value{AS}} that the following 254data is actually instructions. This makes a difference in MIPS 16 mode: 255when loading the address of a label which precedes instructions, 256@code{@value{AS}} automatically adds 1 to the value, so that jumping to 257the loaded address will do the right thing. 258 259@node MIPS option stack 260@section Directives to save and restore options 261 262@cindex MIPS option stack 263@kindex @code{.set push} 264@kindex @code{.set pop} 265The directives @code{.set push} and @code{.set pop} may be used to save 266and restore the current settings for all the options which are 267controlled by @code{.set}. The @code{.set push} directive saves the 268current settings on a stack. The @code{.set pop} directive pops the 269stack and restores the settings. 270 271These directives can be useful inside an macro which must change an 272option such as the ISA level or instruction reordering but does not want 273to change the state of the code which invoked the macro. 274 275Traditional @sc{mips} assemblers do not support these directives. 276