1@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2004 2@c Free Software Foundation, Inc. 3@c This is part of the GAS manual. 4@c For copying conditions, see the file as.texinfo. 5@page 6@node SH-Dependent 7@chapter Renesas / SuperH SH Dependent Features 8 9@cindex SH support 10@menu 11* SH Options:: Options 12* SH Syntax:: Syntax 13* SH Floating Point:: Floating Point 14* SH Directives:: SH Machine Directives 15* SH Opcodes:: Opcodes 16@end menu 17 18@node SH Options 19@section Options 20 21@cindex SH options 22@cindex options, SH 23@code{@value{AS}} has following command-line options for the Renesas 24(formerly Hitachi) / SuperH SH family. 25 26@table @code 27@kindex -little 28@kindex -big 29@kindex -relax 30@kindex -small 31@kindex -dsp 32@kindex -renesas 33 34@item -little 35Generate little endian code. 36 37@item -big 38Generate big endian code. 39 40@item -relax 41Alter jump instructions for long displacements. 42 43@item -small 44Align sections to 4 byte boundaries, not 16. 45 46@item -dsp 47Enable sh-dsp insns, and disable sh3e / sh4 insns. 48 49@item -renesas 50Disable optimization with section symbol for compatibility with 51Renesas assembler. 52 53@item -isa=sh4 | sh4a 54Specify the sh4 or sh4a instruction set. 55@item -isa=dsp 56Enable sh-dsp insns, and disable sh3e / sh4 insns. 57@item -isa=fp 58Enable sh2e, sh3e, sh4, and sh4a insn sets. 59@item -isa=all 60Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 61 62@end table 63 64@node SH Syntax 65@section Syntax 66 67@menu 68* SH-Chars:: Special Characters 69* SH-Regs:: Register Names 70* SH-Addressing:: Addressing Modes 71@end menu 72 73@node SH-Chars 74@subsection Special Characters 75 76@cindex line comment character, SH 77@cindex SH line comment character 78@samp{!} is the line comment character. 79 80@cindex line separator, SH 81@cindex statement separator, SH 82@cindex SH line separator 83You can use @samp{;} instead of a newline to separate statements. 84 85@cindex symbol names, @samp{$} in 86@cindex @code{$} in symbol names 87Since @samp{$} has no special meaning, you may use it in symbol names. 88 89@node SH-Regs 90@subsection Register Names 91 92@cindex SH registers 93@cindex registers, SH 94You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2}, 95@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, @samp{r7}, @samp{r8}, 96@samp{r9}, @samp{r10}, @samp{r11}, @samp{r12}, @samp{r13}, @samp{r14}, 97and @samp{r15} to refer to the SH registers. 98 99The SH also has these control registers: 100 101@table @code 102@item pr 103procedure register (holds return address) 104 105@item pc 106program counter 107 108@item mach 109@itemx macl 110high and low multiply accumulator registers 111 112@item sr 113status register 114 115@item gbr 116global base register 117 118@item vbr 119vector base register (for interrupt vectors) 120@end table 121 122@node SH-Addressing 123@subsection Addressing Modes 124 125@cindex addressing modes, SH 126@cindex SH addressing modes 127@code{@value{AS}} understands the following addressing modes for the SH. 128@code{R@var{n}} in the following refers to any of the numbered 129registers, but @emph{not} the control registers. 130 131@table @code 132@item R@var{n} 133Register direct 134 135@item @@R@var{n} 136Register indirect 137 138@item @@-R@var{n} 139Register indirect with pre-decrement 140 141@item @@R@var{n}+ 142Register indirect with post-increment 143 144@item @@(@var{disp}, R@var{n}) 145Register indirect with displacement 146 147@item @@(R0, R@var{n}) 148Register indexed 149 150@item @@(@var{disp}, GBR) 151@code{GBR} offset 152 153@item @@(R0, GBR) 154GBR indexed 155 156@item @var{addr} 157@itemx @@(@var{disp}, PC) 158PC relative address (for branch or for addressing memory). The 159@code{@value{AS}} implementation allows you to use the simpler form 160@var{addr} anywhere a PC relative address is called for; the alternate 161form is supported for compatibility with other assemblers. 162 163@item #@var{imm} 164Immediate data 165@end table 166 167@node SH Floating Point 168@section Floating Point 169 170@cindex floating point, SH (@sc{ieee}) 171@cindex SH floating point (@sc{ieee}) 172SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other 173SH groups can use @code{.float} directive to generate @sc{ieee} 174floating-point numbers. 175 176SH2E and SH3E support single-precision floating point calculations as 177well as entirely PCAPI compatible emulation of double-precision 178floating point calculations. SH2E and SH3E instructions are a subset of 179the floating point calculations conforming to the IEEE754 standard. 180 181In addition to single-precision and double-precision floating-point 182operation capability, the on-chip FPU of SH4 has a 128-bit graphic 183engine that enables 32-bit floating-point data to be processed 128 184bits at a time. It also supports 4 * 4 array operations and inner 185product operations. Also, a superscalar architecture is employed that 186enables simultaneous execution of two instructions (including FPU 187instructions), providing performance of up to twice that of 188conventional architectures at the same frequency. 189 190@node SH Directives 191@section SH Machine Directives 192 193@cindex SH machine directives 194@cindex machine directives, SH 195@cindex @code{uaword} directive, SH 196@cindex @code{ualong} directive, SH 197 198@table @code 199@item uaword 200@itemx ualong 201@code{@value{AS}} will issue a warning when a misaligned @code{.word} or 202@code{.long} directive is used. You may use @code{.uaword} or 203@code{.ualong} to indicate that the value is intentionally misaligned. 204@end table 205 206@node SH Opcodes 207@section Opcodes 208 209@cindex SH opcode summary 210@cindex opcode summary, SH 211@cindex mnemonics, SH 212@cindex instruction summary, SH 213For detailed information on the SH machine instruction set, see 214@cite{SH-Microcomputer User's Manual} (Renesas) or 215@cite{SH-4 32-bit CPU Core Architecture} (SuperH) and 216@cite{SuperH (SH) 64-Bit RISC Series} (SuperH). 217 218@code{@value{AS}} implements all the standard SH opcodes. No additional 219pseudo-instructions are needed on this family. Note, however, that 220because @code{@value{AS}} supports a simpler form of PC-relative 221addressing, you may simply write (for example) 222 223@example 224mov.l bar,r0 225@end example 226 227@noindent 228where other assemblers might require an explicit displacement to 229@code{bar} from the program counter: 230 231@example 232mov.l @@(@var{disp}, PC) 233@end example 234 235@ifset SMALL 236@c this table, due to the multi-col faking and hardcoded order, looks silly 237@c except in smallbook. See comments below "@set SMALL" near top of this file. 238 239Here is a summary of SH opcodes: 240 241@page 242@smallexample 243@i{Legend:} 244Rn @r{a numbered register} 245Rm @r{another numbered register} 246#imm @r{immediate data} 247disp @r{displacement} 248disp8 @r{8-bit displacement} 249disp12 @r{12-bit displacement} 250 251add #imm,Rn lds.l @@Rn+,PR 252add Rm,Rn mac.w @@Rm+,@@Rn+ 253addc Rm,Rn mov #imm,Rn 254addv Rm,Rn mov Rm,Rn 255and #imm,R0 mov.b Rm,@@(R0,Rn) 256and Rm,Rn mov.b Rm,@@-Rn 257and.b #imm,@@(R0,GBR) mov.b Rm,@@Rn 258bf disp8 mov.b @@(disp,Rm),R0 259bra disp12 mov.b @@(disp,GBR),R0 260bsr disp12 mov.b @@(R0,Rm),Rn 261bt disp8 mov.b @@Rm+,Rn 262clrmac mov.b @@Rm,Rn 263clrt mov.b R0,@@(disp,Rm) 264cmp/eq #imm,R0 mov.b R0,@@(disp,GBR) 265cmp/eq Rm,Rn mov.l Rm,@@(disp,Rn) 266cmp/ge Rm,Rn mov.l Rm,@@(R0,Rn) 267cmp/gt Rm,Rn mov.l Rm,@@-Rn 268cmp/hi Rm,Rn mov.l Rm,@@Rn 269cmp/hs Rm,Rn mov.l @@(disp,Rn),Rm 270cmp/pl Rn mov.l @@(disp,GBR),R0 271cmp/pz Rn mov.l @@(disp,PC),Rn 272cmp/str Rm,Rn mov.l @@(R0,Rm),Rn 273div0s Rm,Rn mov.l @@Rm+,Rn 274div0u mov.l @@Rm,Rn 275div1 Rm,Rn mov.l R0,@@(disp,GBR) 276exts.b Rm,Rn mov.w Rm,@@(R0,Rn) 277exts.w Rm,Rn mov.w Rm,@@-Rn 278extu.b Rm,Rn mov.w Rm,@@Rn 279extu.w Rm,Rn mov.w @@(disp,Rm),R0 280jmp @@Rn mov.w @@(disp,GBR),R0 281jsr @@Rn mov.w @@(disp,PC),Rn 282ldc Rn,GBR mov.w @@(R0,Rm),Rn 283ldc Rn,SR mov.w @@Rm+,Rn 284ldc Rn,VBR mov.w @@Rm,Rn 285ldc.l @@Rn+,GBR mov.w R0,@@(disp,Rm) 286ldc.l @@Rn+,SR mov.w R0,@@(disp,GBR) 287ldc.l @@Rn+,VBR mova @@(disp,PC),R0 288lds Rn,MACH movt Rn 289lds Rn,MACL muls Rm,Rn 290lds Rn,PR mulu Rm,Rn 291lds.l @@Rn+,MACH neg Rm,Rn 292lds.l @@Rn+,MACL negc Rm,Rn 293@page 294nop stc VBR,Rn 295not Rm,Rn stc.l GBR,@@-Rn 296or #imm,R0 stc.l SR,@@-Rn 297or Rm,Rn stc.l VBR,@@-Rn 298or.b #imm,@@(R0,GBR) sts MACH,Rn 299rotcl Rn sts MACL,Rn 300rotcr Rn sts PR,Rn 301rotl Rn sts.l MACH,@@-Rn 302rotr Rn sts.l MACL,@@-Rn 303rte sts.l PR,@@-Rn 304rts sub Rm,Rn 305sett subc Rm,Rn 306shal Rn subv Rm,Rn 307shar Rn swap.b Rm,Rn 308shll Rn swap.w Rm,Rn 309shll16 Rn tas.b @@Rn 310shll2 Rn trapa #imm 311shll8 Rn tst #imm,R0 312shlr Rn tst Rm,Rn 313shlr16 Rn tst.b #imm,@@(R0,GBR) 314shlr2 Rn xor #imm,R0 315shlr8 Rn xor Rm,Rn 316sleep xor.b #imm,@@(R0,GBR) 317stc GBR,Rn xtrct Rm,Rn 318stc SR,Rn 319@end smallexample 320@end ifset 321 322@ifset Renesas-all 323@ifclear GENERIC 324@raisesections 325@end ifclear 326@end ifset 327 328