1 /* Caching code. Typically used by remote back ends for 2 caching remote memory. 3 4 Copyright 1992, 1993, 1995 Free Software Foundation, Inc. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program; if not, write to the Free Software 20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 21 22 #include "defs.h" 23 #include "dcache.h" 24 #include "gdbcmd.h" 25 #include "gdb_string.h" 26 #include "gdbcore.h" 27 28 /* 29 The data cache could lead to incorrect results because it doesn't know 30 about volatile variables, thus making it impossible to debug 31 functions which use memory mapped I/O devices. 32 33 set remotecache 0 34 35 In those cases. 36 37 In general the dcache speeds up performance, some speed improvement 38 comes from the actual caching mechanism, but the major gain is in 39 the reduction of the remote protocol overhead; instead of reading 40 or writing a large area of memory in 4 byte requests, the cache 41 bundles up the requests into 32 byte (actually LINE_SIZE) chunks. 42 Reducing the overhead to an eighth of what it was. This is very 43 obvious when displaying a large amount of data, 44 45 eg, x/200x 0 46 47 caching | no yes 48 ---------------------------- 49 first time | 4 sec 2 sec improvement due to chunking 50 second time | 4 sec 0 sec improvement due to caching 51 52 The cache structure is unusual, we keep a number of cache blocks 53 (DCACHE_SIZE) and each one caches a LINE_SIZEed area of memory. 54 Within each line we remember the address of the line (always a 55 multiple of the LINE_SIZE) and a vector of bytes over the range. 56 There's another vector which contains the state of the bytes. 57 58 ENTRY_BAD means that the byte is just plain wrong, and has no 59 correspondence with anything else (as it would when the cache is 60 turned on, but nothing has been done to it. 61 62 ENTRY_DIRTY means that the byte has some data in it which should be 63 written out to the remote target one day, but contains correct 64 data. ENTRY_OK means that the data is the same in the cache as it 65 is in remote memory. 66 67 68 The ENTRY_DIRTY state is necessary because GDB likes to write large 69 lumps of memory in small bits. If the caching mechanism didn't 70 maintain the DIRTY information, then something like a two byte 71 write would mean that the entire cache line would have to be read, 72 the two bytes modified and then written out again. The alternative 73 would be to not read in the cache line in the first place, and just 74 write the two bytes directly into target memory. The trouble with 75 that is that it really nails performance, because of the remote 76 protocol overhead. This way, all those little writes are bundled 77 up into an entire cache line write in one go, without having to 78 read the cache line in the first place. 79 80 81 */ 82 83 84 /* This value regulates the number of cache blocks stored. 85 Smaller values reduce the time spent searching for a cache 86 line, and reduce memory requirements, but increase the risk 87 of a line not being in memory */ 88 89 #define DCACHE_SIZE 64 90 91 /* This value regulates the size of a cache line. Smaller values 92 reduce the time taken to read a single byte, but reduce overall 93 throughput. */ 94 95 #define LINE_SIZE_POWER (5) 96 #define LINE_SIZE (1 << LINE_SIZE_POWER) 97 98 /* Each cache block holds LINE_SIZE bytes of data 99 starting at a multiple-of-LINE_SIZE address. */ 100 101 #define LINE_SIZE_MASK ((LINE_SIZE - 1)) 102 #define XFORM(x) ((x) & LINE_SIZE_MASK) 103 #define MASK(x) ((x) & ~LINE_SIZE_MASK) 104 105 106 #define ENTRY_BAD 0 /* data at this byte is wrong */ 107 #define ENTRY_DIRTY 1 /* data at this byte needs to be written back */ 108 #define ENTRY_OK 2 /* data at this byte is same as in memory */ 109 110 111 struct dcache_block 112 { 113 struct dcache_block *p; /* next in list */ 114 CORE_ADDR addr; /* Address for which data is recorded. */ 115 char data[LINE_SIZE]; /* bytes at given address */ 116 unsigned char state[LINE_SIZE]; /* what state the data is in */ 117 118 /* whether anything in state is dirty - used to speed up the 119 dirty scan. */ 120 int anydirty; 121 122 int refs; 123 }; 124 125 126 struct dcache_struct 127 { 128 /* Function to actually read the target memory. */ 129 memxferfunc read_memory; 130 131 /* Function to actually write the target memory */ 132 memxferfunc write_memory; 133 134 /* free list */ 135 struct dcache_block *free_head; 136 struct dcache_block *free_tail; 137 138 /* in use list */ 139 struct dcache_block *valid_head; 140 struct dcache_block *valid_tail; 141 142 /* The cache itself. */ 143 struct dcache_block *the_cache; 144 145 /* potentially, if the cache was enabled, and then turned off, and 146 then turned on again, the stuff in it could be stale, so this is 147 used to mark it */ 148 int cache_has_stuff; 149 } ; 150 151 static int 152 dcache_poke_byte PARAMS ((DCACHE *dcache, CORE_ADDR addr, char *ptr)); 153 154 static int 155 dcache_peek_byte PARAMS ((DCACHE *dcache, CORE_ADDR addr, char *ptr)); 156 157 static struct dcache_block * 158 dcache_hit PARAMS ((DCACHE *dcache, CORE_ADDR addr)); 159 160 static int dcache_write_line PARAMS ((DCACHE *dcache,struct dcache_block *db)); 161 162 static struct dcache_block *dcache_alloc PARAMS ((DCACHE *dcache)); 163 164 static int dcache_writeback PARAMS ((DCACHE *dcache)); 165 166 static void dcache_info PARAMS ((char *exp, int tty)); 167 168 int remote_dcache = 0; 169 170 DCACHE *last_cache; /* Used by info dcache */ 171 172 173 174 /* Free all the data cache blocks, thus discarding all cached data. */ 175 176 void 177 dcache_flush (dcache) 178 DCACHE *dcache; 179 { 180 int i; 181 dcache->valid_head = 0; 182 dcache->valid_tail = 0; 183 184 dcache->free_head = 0; 185 dcache->free_tail = 0; 186 187 for (i = 0; i < DCACHE_SIZE; i++) 188 { 189 struct dcache_block *db = dcache->the_cache + i; 190 191 if (!dcache->free_head) 192 dcache->free_head = db; 193 else 194 dcache->free_tail->p = db; 195 dcache->free_tail = db; 196 db->p = 0; 197 } 198 199 dcache->cache_has_stuff = 0; 200 201 return; 202 } 203 204 /* If addr is present in the dcache, return the address of the block 205 containing it. */ 206 207 static struct dcache_block * 208 dcache_hit (dcache, addr) 209 DCACHE *dcache; 210 CORE_ADDR addr; 211 { 212 register struct dcache_block *db; 213 214 /* Search all cache blocks for one that is at this address. */ 215 db = dcache->valid_head; 216 217 while (db) 218 { 219 if (MASK(addr) == db->addr) 220 { 221 db->refs++; 222 return db; 223 } 224 db = db->p; 225 } 226 227 return NULL; 228 } 229 230 /* Make sure that anything in this line which needs to 231 be written is. */ 232 233 static int 234 dcache_write_line (dcache, db) 235 DCACHE *dcache; 236 register struct dcache_block *db; 237 { 238 int s; 239 int e; 240 s = 0; 241 if (db->anydirty) 242 { 243 for (s = 0; s < LINE_SIZE; s++) 244 { 245 if (db->state[s] == ENTRY_DIRTY) 246 { 247 int len = 0; 248 for (e = s ; e < LINE_SIZE; e++, len++) 249 if (db->state[e] != ENTRY_DIRTY) 250 break; 251 { 252 /* all bytes from s..s+len-1 need to 253 be written out */ 254 int done = 0; 255 while (done < len) { 256 int t = dcache->write_memory (db->addr + s + done, 257 db->data + s + done, 258 len - done); 259 if (t == 0) 260 return 0; 261 done += t; 262 } 263 memset (db->state + s, ENTRY_OK, len); 264 s = e; 265 } 266 } 267 } 268 db->anydirty = 0; 269 } 270 return 1; 271 } 272 273 274 /* Get a free cache block, put or keep it on the valid list, 275 and return its address. The caller should store into the block 276 the address and data that it describes, then remque it from the 277 free list and insert it into the valid list. This procedure 278 prevents errors from creeping in if a memory retrieval is 279 interrupted (which used to put garbage blocks in the valid 280 list...). */ 281 282 static struct dcache_block * 283 dcache_alloc (dcache) 284 DCACHE *dcache; 285 { 286 register struct dcache_block *db; 287 288 if (remote_dcache == 0) 289 abort (); 290 291 /* Take something from the free list */ 292 db = dcache->free_head; 293 if (db) 294 { 295 dcache->free_head = db->p; 296 } 297 else 298 { 299 /* Nothing left on free list, so grab one from the valid list */ 300 db = dcache->valid_head; 301 dcache->valid_head = db->p; 302 303 dcache_write_line (dcache, db); 304 } 305 306 /* append this line to end of valid list */ 307 if (!dcache->valid_head) 308 dcache->valid_head = db; 309 else 310 dcache->valid_tail->p = db; 311 dcache->valid_tail = db; 312 db->p = 0; 313 314 return db; 315 } 316 317 /* Using the data cache DCACHE return the contents of the byte at 318 address ADDR in the remote machine. 319 320 Returns 0 on error. */ 321 322 static int 323 dcache_peek_byte (dcache, addr, ptr) 324 DCACHE *dcache; 325 CORE_ADDR addr; 326 char *ptr; 327 { 328 register struct dcache_block *db = dcache_hit (dcache, addr); 329 int ok=1; 330 int done = 0; 331 if (db == 0 332 || db->state[XFORM (addr)] == ENTRY_BAD) 333 { 334 if (db) 335 { 336 dcache_write_line (dcache, db); 337 } 338 else 339 db = dcache_alloc (dcache); 340 immediate_quit++; 341 db->addr = MASK (addr); 342 while (done < LINE_SIZE) 343 { 344 int try = 345 (*dcache->read_memory) 346 (db->addr + done, 347 db->data + done, 348 LINE_SIZE - done); 349 if (try == 0) 350 return 0; 351 done += try; 352 } 353 immediate_quit--; 354 355 memset (db->state, ENTRY_OK, sizeof (db->data)); 356 db->anydirty = 0; 357 } 358 *ptr = db->data[XFORM (addr)]; 359 return ok; 360 } 361 362 /* Writeback any dirty lines to the remote. */ 363 static int 364 dcache_writeback (dcache) 365 DCACHE *dcache; 366 { 367 struct dcache_block *db; 368 369 db = dcache->valid_head; 370 371 while (db) 372 { 373 if (!dcache_write_line (dcache, db)) 374 return 0; 375 db = db->p; 376 } 377 return 1; 378 } 379 380 381 /* Using the data cache DCACHE return the contents of the word at 382 address ADDR in the remote machine. */ 383 int 384 dcache_fetch (dcache, addr) 385 DCACHE *dcache; 386 CORE_ADDR addr; 387 { 388 int res; 389 390 if (dcache_xfer_memory (dcache, addr, (char *)&res, sizeof res, 0) != sizeof res) 391 memory_error (EIO, addr); 392 393 return res; 394 } 395 396 397 /* Write the byte at PTR into ADDR in the data cache. 398 Return zero on write error. 399 */ 400 401 static int 402 dcache_poke_byte (dcache, addr, ptr) 403 DCACHE *dcache; 404 CORE_ADDR addr; 405 char *ptr; 406 { 407 register struct dcache_block *db = dcache_hit (dcache, addr); 408 409 if (!db) 410 { 411 db = dcache_alloc (dcache); 412 db->addr = MASK (addr); 413 memset (db->state, ENTRY_BAD, sizeof (db->data)); 414 } 415 416 db->data[XFORM (addr)] = *ptr; 417 db->state[XFORM (addr)] = ENTRY_DIRTY; 418 db->anydirty = 1; 419 return 1; 420 } 421 422 /* Write the word at ADDR both in the data cache and in the remote machine. 423 Return zero on write error. 424 */ 425 426 int 427 dcache_poke (dcache, addr, data) 428 DCACHE *dcache; 429 CORE_ADDR addr; 430 int data; 431 { 432 if (dcache_xfer_memory (dcache, addr, (char *)&data, sizeof data, 1) != sizeof data) 433 return 0; 434 435 return dcache_writeback (dcache); 436 } 437 438 439 /* Initialize the data cache. */ 440 DCACHE * 441 dcache_init (reading, writing) 442 memxferfunc reading; 443 memxferfunc writing; 444 { 445 int csize = sizeof (struct dcache_block) * DCACHE_SIZE; 446 DCACHE *dcache; 447 448 dcache = (DCACHE *) xmalloc (sizeof (*dcache)); 449 dcache->read_memory = reading; 450 dcache->write_memory = writing; 451 452 dcache->the_cache = (struct dcache_block *) xmalloc (csize); 453 memset (dcache->the_cache, 0, csize); 454 455 dcache_flush (dcache); 456 457 last_cache = dcache; 458 return dcache; 459 } 460 461 /* Read or write LEN bytes from inferior memory at MEMADDR, transferring 462 to or from debugger address MYADDR. Write to inferior if SHOULD_WRITE is 463 nonzero. 464 465 Returns length of data written or read; 0 for error. 466 467 This routine is indended to be called by remote_xfer_ functions. */ 468 469 int 470 dcache_xfer_memory (dcache, memaddr, myaddr, len, should_write) 471 DCACHE *dcache; 472 CORE_ADDR memaddr; 473 char *myaddr; 474 int len; 475 int should_write; 476 { 477 int i; 478 479 if (remote_dcache) 480 { 481 int (*xfunc) PARAMS ((DCACHE *dcache, CORE_ADDR addr, char *ptr)); 482 xfunc = should_write ? dcache_poke_byte : dcache_peek_byte; 483 484 for (i = 0; i < len; i++) 485 { 486 if (!xfunc (dcache, memaddr + i, myaddr + i)) 487 return 0; 488 } 489 dcache->cache_has_stuff = 1; 490 dcache_writeback (dcache); 491 } 492 else 493 { 494 memxferfunc xfunc; 495 xfunc = should_write ? dcache->write_memory : dcache->read_memory; 496 497 if (dcache->cache_has_stuff) 498 dcache_flush (dcache); 499 500 len = xfunc (memaddr, myaddr, len); 501 } 502 return len; 503 } 504 505 static void 506 dcache_info (exp, tty) 507 char *exp; 508 int tty; 509 { 510 struct dcache_block *p; 511 512 if (!remote_dcache) 513 { 514 printf_filtered ("Dcache not enabled\n"); 515 return; 516 } 517 printf_filtered ("Dcache enabled, line width %d, depth %d\n", 518 LINE_SIZE, DCACHE_SIZE); 519 520 printf_filtered ("Cache state:\n"); 521 522 for (p = last_cache->valid_head; p; p = p->p) 523 { 524 int j; 525 printf_filtered ("Line at %08xd, referenced %d times\n", 526 p->addr, p->refs); 527 528 for (j = 0; j < LINE_SIZE; j++) 529 printf_filtered ("%02x", p->data[j] & 0xFF); 530 printf_filtered ("\n"); 531 532 for (j = 0; j < LINE_SIZE; j++) 533 printf_filtered (" %2x", p->state[j]); 534 printf_filtered ("\n"); 535 } 536 } 537 538 void 539 _initialize_dcache () 540 { 541 add_show_from_set 542 (add_set_cmd ("remotecache", class_support, var_boolean, 543 (char *) &remote_dcache, 544 "\ 545 Set cache use for remote targets.\n\ 546 When on, use data caching for remote targets. For many remote targets\n\ 547 this option can offer better throughput for reading target memory.\n\ 548 Unfortunately, gdb does not currently know anything about volatile\n\ 549 registers and thus data caching will produce incorrect results with\n\ 550 volatile registers are in use. By default, this option is on.", 551 &setlist), 552 &showlist); 553 554 add_info ("dcache", dcache_info, 555 "Print information on the dcache performance."); 556 557 } 558