1 /* Opcode table for the ARM. 2 3 Copyright 1994, 1995 Free Software Foundation, Inc. 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2, or (at your option) 8 any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 18 19 20 struct arm_opcode { 21 unsigned long value, mask; /* recognise instruction if (op&mask)==value */ 22 char *assembler; /* how to disassemble this instruction */ 23 }; 24 25 /* format of the assembler string : 26 27 %% % 28 %<bitfield>d print the bitfield in decimal 29 %<bitfield>x print the bitfield in hex 30 %<bitfield>r print as an ARM register 31 %<bitfield>f print a floating point constant if >7 else a 32 floating point register 33 %c print condition code (always bits 28-31) 34 %P print floating point precision in arithmetic insn 35 %Q print floating point precision in ldf/stf insn 36 %R print floating point rounding mode 37 %<bitnum>'c print specified char iff bit is one 38 %<bitnum>`c print specified char iff bit is zero 39 %<bitnum>?ab print a if bit is one else print b 40 %p print 'p' iff bits 12-15 are 15 41 %t print 't' iff bit 21 set and bit 24 clear 42 %o print operand2 (immediate or register + shift) 43 %a print address for ldr/str instruction 44 %b print branch destination 45 %A print address for ldc/stc/ldf/stf instruction 46 %m print register mask for ldm/stm instruction 47 %C print the PSR sub type. 48 %F print the COUNT field of a LFM/SFM instruction. 49 */ 50 51 /* Note: There is a partial ordering in this table - it must be searched from 52 the top to obtain a correct match. */ 53 54 static struct arm_opcode arm_opcodes[] = { 55 /* ARM instructions */ 56 {0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"}, 57 {0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"}, 58 {0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"}, 59 {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, 60 {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, 61 {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, 62 {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, 63 {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, 64 {0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"}, 65 {0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"}, 66 {0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"}, 67 {0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"}, 68 {0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"}, 69 {0x0120f000, 0x0db6f000, "msr%c\t%22?scpsr%C, %o"}, 70 {0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?scpsr"}, 71 {0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"}, 72 {0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"}, 73 {0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"}, 74 {0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"}, 75 {0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"}, 76 {0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"}, 77 {0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"}, 78 {0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"}, 79 {0x04000000, 0x0c100000, "str%c%22'b%t\t%12-15r, %a"}, 80 {0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"}, 81 {0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, 82 {0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"}, 83 {0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, 84 {0x0f000000, 0x0f000000, "swi%c\t%0-23x"}, 85 86 /* Floating point coprocessor instructions */ 87 {0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 88 {0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 89 {0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 90 {0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 91 {0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 92 {0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 93 {0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, 94 {0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, 95 {0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, 96 {0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, 97 {0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, 98 {0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, 99 {0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, 100 {0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, 101 {0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, 102 {0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, 103 {0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, 104 {0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, 105 {0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, 106 {0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, 107 {0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, 108 {0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, 109 {0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, 110 {0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, 111 {0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, 112 {0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, 113 {0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, 114 {0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, 115 {0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, 116 {0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, 117 {0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, 118 {0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, 119 {0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, 120 {0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, 121 {0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, 122 {0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, 123 {0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, 124 {0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, 125 {0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, 126 {0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, 127 {0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, 128 {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, 129 {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, 130 131 /* Generic coprocessor instructions */ 132 {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, 133 {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 134 {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, 135 {0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"}, 136 {0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"}, 137 /* the rest */ 138 {0x00000000, 0x00000000, "undefined instruction %0-31x"}, 139 {0x00000000, 0x00000000, 0} 140 }; 141 142 #define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) 143