1# $OpenBSD: Makefile,v 1.1 2019/01/29 00:18:23 jsg Exp $
2
3.include <bsd.own.mk>
4
5LLVM_SRCS=	${.CURDIR}/../../../../../llvm
6
7HDRS=	AMDGPUGenAsmMatcher.inc AMDGPUGenAsmWriter.inc \
8	AMDGPUGenCallingConv.inc AMDGPUGenDAGISel.inc \
9	AMDGPUGenDisassemblerTables.inc AMDGPUGenInstrInfo.inc \
10	AMDGPUGenIntrinsicEnums.inc AMDGPUGenIntrinsicImpl.inc \
11	AMDGPUGenMCCodeEmitter.inc AMDGPUGenMCPseudoLowering.inc \
12	AMDGPUGenRegisterBank.inc AMDGPUGenRegisterInfo.inc \
13	AMDGPUGenSearchableTables.inc AMDGPUGenSubtargetInfo.inc
14
15HDRS+=	AMDGPUGenGlobalISel.inc
16
17HDRS+=	R600GenAsmWriter.inc R600GenCallingConv.inc \
18	R600GenDAGISel.inc R600GenDFAPacketizer.inc \
19	R600GenInstrInfo.inc R600GenMCCodeEmitter.inc \
20	R600GenRegisterInfo.inc R600GenSubtargetInfo.inc
21
22all: ${HDRS}
23
24install:
25	@# Nothing here so far ...
26
27clean cleandir:
28	rm -f ${HDRS}
29
30AMDGPUGenAsmMatcher.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
31	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-matcher \
32		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
33		-o ${.TARGET} ${.ALLSRC}
34AMDGPUGenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
35	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-writer \
36		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
37		-o ${.TARGET} ${.ALLSRC}
38AMDGPUGenCallingConv.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
39	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-callingconv \
40		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
41		-o ${.TARGET} ${.ALLSRC}
42AMDGPUGenDAGISel.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
43	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-dag-isel \
44		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
45		-o ${.TARGET} ${.ALLSRC}
46AMDGPUGenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
47	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-disassembler \
48		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
49		-o ${.TARGET} ${.ALLSRC}
50AMDGPUGenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
51	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-instr-info \
52		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
53		-o ${.TARGET} ${.ALLSRC}
54AMDGPUGenIntrinsicEnums.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
55	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-tgt-intrinsic-enums \
56		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
57		-o ${.TARGET} ${.ALLSRC}
58AMDGPUGenIntrinsicImpl.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
59	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-tgt-intrinsic-impl \
60		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
61		-o ${.TARGET} ${.ALLSRC}
62AMDGPUGenMCCodeEmitter.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
63	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-emitter \
64		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
65		-o ${.TARGET} ${.ALLSRC}
66AMDGPUGenMCPseudoLowering.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
67	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-pseudo-lowering \
68		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
69		-o ${.TARGET} ${.ALLSRC}
70AMDGPUGenRegisterBank.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
71	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-bank \
72		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
73		-o ${.TARGET} ${.ALLSRC}
74AMDGPUGenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
75	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-info \
76		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
77		-o ${.TARGET} ${.ALLSRC}
78AMDGPUGenSearchableTables.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
79	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-searchable-tables \
80		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
81		-o ${.TARGET} ${.ALLSRC}
82AMDGPUGenSubtargetInfo.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPU.td
83	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-subtarget \
84		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
85		-o ${.TARGET} ${.ALLSRC}
86
87AMDGPUGenGlobalISel.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/AMDGPUGISel.td
88	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel \
89		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
90		-o ${.TARGET} ${.ALLSRC}
91
92R600GenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
93	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-writer \
94		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
95		-o ${.TARGET} ${.ALLSRC}
96R600GenCallingConv.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
97	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-callingconv \
98		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
99		-o ${.TARGET} ${.ALLSRC}
100R600GenDAGISel.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
101	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-dag-isel \
102		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
103		-o ${.TARGET} ${.ALLSRC}
104R600GenDFAPacketizer.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
105	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-dfa-packetizer \
106		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
107		-o ${.TARGET} ${.ALLSRC}
108R600GenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
109	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-instr-info \
110		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
111		-o ${.TARGET} ${.ALLSRC}
112R600GenMCCodeEmitter.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
113	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-emitter \
114		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
115		-o ${.TARGET} ${.ALLSRC}
116R600GenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
117	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-info \
118		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
119		-o ${.TARGET} ${.ALLSRC}
120R600GenSubtargetInfo.inc: ${LLVM_SRCS}/lib/Target/AMDGPU/R600.td
121	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-subtarget \
122		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/AMDGPU \
123		-o ${.TARGET} ${.ALLSRC}
124
125.include <bsd.obj.mk>
126