1# $OpenBSD: Makefile,v 1.3 2018/04/06 14:44:04 patrick Exp $ 2 3.include <bsd.own.mk> 4 5LLVM_SRCS= ${.CURDIR}/../../../../../llvm 6 7HDRS= ARMGenAsmMatcher.inc ARMGenAsmWriter.inc \ 8 ARMGenCallingConv.inc ARMGenDAGISel.inc ARMGenDisassemblerTables.inc \ 9 ARMGenFastISel.inc ARMGenInstrInfo.inc ARMGenRegisterInfo.inc \ 10 ARMGenSubtargetInfo.inc \ 11 ARMGenMCCodeEmitter.inc ARMGenMCPseudoLowering.inc \ 12 ARMGenDisassemblerTables.inc ARMGenSystemRegister.inc \ 13 ARMGenRegisterBank.inc ARMGenGlobalISel.inc 14 15all: ${HDRS} 16 17install: 18 @# Nothing here so far ... 19 20clean cleandir: 21 rm -f ${HDRS} 22 23ARMGenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 24 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-info \ 25 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 26 -o ${.TARGET} ${.ALLSRC} 27 28ARMGenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 29 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-disassembler \ 30 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 31 -o ${.TARGET} ${.ALLSRC} 32 33ARMGenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 34 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-instr-info \ 35 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 36 -o ${.TARGET} ${.ALLSRC} 37 38ARMGenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 39 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-writer \ 40 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 41 -o ${.TARGET} ${.ALLSRC} 42 43ARMGenAsmMatcher.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 44 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-matcher \ 45 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 46 -o ${.TARGET} ${.ALLSRC} 47 48ARMGenDAGISel.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 49 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-dag-isel \ 50 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 51 -o ${.TARGET} ${.ALLSRC} 52 53ARMGenFastISel.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 54 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-fast-isel \ 55 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 56 -o ${.TARGET} ${.ALLSRC} 57 58ARMGenCallingConv.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 59 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-callingconv \ 60 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 61 -o ${.TARGET} ${.ALLSRC} 62 63ARMGenSubtargetInfo.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 64 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-subtarget \ 65 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 66 -o ${.TARGET} ${.ALLSRC} 67 68ARMGenMCCodeEmitter.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 69 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-emitter \ 70 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 71 -o ${.TARGET} ${.ALLSRC} 72 73ARMGenMCPseudoLowering.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 74 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-pseudo-lowering \ 75 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 76 -o ${.TARGET} ${.ALLSRC} 77 78ARMGenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 79 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-disassembler \ 80 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 81 -o ${.TARGET} ${.ALLSRC} 82 83ARMGenSystemRegister.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 84 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-searchable-tables \ 85 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 86 -o ${.TARGET} ${.ALLSRC} 87 88ARMGenRegisterBank.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 89 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-bank \ 90 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 91 -o ${.TARGET} ${.ALLSRC} 92 93ARMGenGlobalISel.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 94 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel \ 95 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 96 -o ${.TARGET} ${.ALLSRC} 97 98.include <bsd.obj.mk> 99