1# $OpenBSD: Makefile,v 1.5 2021/04/28 12:55:38 patrick Exp $ 2 3.include <bsd.own.mk> 4 5LLVM_SRCS= ${.CURDIR}/../../../../../llvm/llvm 6 7HDRS= ARMGenAsmMatcher.inc \ 8 ARMGenAsmWriter.inc \ 9 ARMGenCallingConv.inc \ 10 ARMGenDAGISel.inc \ 11 ARMGenDisassemblerTables.inc \ 12 ARMGenFastISel.inc \ 13 ARMGenGlobalISel.inc \ 14 ARMGenInstrInfo.inc \ 15 ARMGenMCCodeEmitter.inc \ 16 ARMGenMCPseudoLowering.inc \ 17 ARMGenRegisterBank.inc \ 18 ARMGenRegisterInfo.inc \ 19 ARMGenSubtargetInfo.inc \ 20 ARMGenSystemRegister.inc 21 22all: ${HDRS} 23 24install: 25 @# Nothing here so far ... 26 27clean cleandir: 28 rm -f ${HDRS} 29 30ARMGenAsmMatcher.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 31 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-matcher \ 32 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 33 -o ${.TARGET} ${.ALLSRC} 34 35ARMGenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 36 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-writer \ 37 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 38 -o ${.TARGET} ${.ALLSRC} 39 40ARMGenCallingConv.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 41 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-callingconv \ 42 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 43 -o ${.TARGET} ${.ALLSRC} 44 45ARMGenDAGISel.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 46 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-dag-isel \ 47 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 48 -o ${.TARGET} ${.ALLSRC} 49 50ARMGenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 51 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-disassembler \ 52 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 53 -o ${.TARGET} ${.ALLSRC} 54 55ARMGenFastISel.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 56 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-fast-isel \ 57 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 58 -o ${.TARGET} ${.ALLSRC} 59 60ARMGenGlobalISel.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 61 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel \ 62 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 63 -o ${.TARGET} ${.ALLSRC} 64 65ARMGenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 66 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-instr-info \ 67 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 68 -o ${.TARGET} ${.ALLSRC} 69 70ARMGenMCCodeEmitter.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 71 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-emitter \ 72 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 73 -o ${.TARGET} ${.ALLSRC} 74 75ARMGenMCPseudoLowering.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 76 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-pseudo-lowering \ 77 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 78 -o ${.TARGET} ${.ALLSRC} 79 80ARMGenRegisterBank.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 81 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-bank \ 82 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 83 -o ${.TARGET} ${.ALLSRC} 84 85ARMGenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 86 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-info \ 87 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 88 -o ${.TARGET} ${.ALLSRC} 89 90ARMGenSubtargetInfo.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 91 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-subtarget \ 92 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 93 -o ${.TARGET} ${.ALLSRC} 94 95ARMGenSystemRegister.inc: ${LLVM_SRCS}/lib/Target/ARM/ARM.td 96 ${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-searchable-tables \ 97 -I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/ARM \ 98 -o ${.TARGET} ${.ALLSRC} 99 100.include <bsd.obj.mk> 101