1# $OpenBSD: Makefile,v 1.5 2021/04/28 12:55:38 patrick Exp $
2
3.include <bsd.own.mk>
4
5LLVM_SRCS=	${.CURDIR}/../../../../../llvm/llvm
6
7HDRS=	MipsGenAsmMatcher.inc \
8	MipsGenAsmWriter.inc \
9	MipsGenCallingConv.inc \
10	MipsGenDAGISel.inc \
11	MipsGenDisassemblerTables.inc \
12	MipsGenFastISel.inc \
13	MipsGenGlobalISel.inc \
14	MipsGenInstrInfo.inc \
15	MipsGenMCCodeEmitter.inc \
16	MipsGenMCPseudoLowering.inc \
17	MipsGenRegisterBank.inc \
18	MipsGenRegisterInfo.inc \
19	MipsGenSubtargetInfo.inc \
20	MipsGenExegesis.inc
21
22all: ${HDRS}
23
24install:
25	@# Nothing here so far ...
26
27clean cleandir:
28	rm -f ${HDRS}
29
30MipsGenAsmMatcher.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
31	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-matcher \
32		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
33		-o ${.TARGET} ${.ALLSRC}
34
35MipsGenAsmWriter.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
36	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-asm-writer \
37		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
38		-o ${.TARGET} ${.ALLSRC}
39
40MipsGenCallingConv.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
41	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-callingconv \
42		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
43		-o ${.TARGET} ${.ALLSRC}
44
45MipsGenDAGISel.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
46	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-dag-isel \
47		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
48		-o ${.TARGET} ${.ALLSRC}
49
50MipsGenDisassemblerTables.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
51	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-disassembler \
52		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
53		-o ${.TARGET} ${.ALLSRC}
54
55MipsGenFastISel.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
56	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-fast-isel \
57		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
58		-o ${.TARGET} ${.ALLSRC}
59
60MipsGenGlobalISel.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
61	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-global-isel \
62		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
63		-o ${.TARGET} ${.ALLSRC}
64
65MipsGenInstrInfo.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
66	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-instr-info \
67		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
68		-o ${.TARGET} ${.ALLSRC}
69
70MipsGenMCCodeEmitter.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
71	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-emitter \
72		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
73		-o ${.TARGET} ${.ALLSRC}
74
75MipsGenMCPseudoLowering.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
76	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-pseudo-lowering \
77		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
78		-o ${.TARGET} ${.ALLSRC}
79
80MipsGenRegisterBank.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
81	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-bank \
82		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
83		-o ${.TARGET} ${.ALLSRC}
84
85MipsGenRegisterInfo.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
86	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-register-info \
87		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
88		-o ${.TARGET} ${.ALLSRC}
89
90MipsGenSubtargetInfo.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
91	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-subtarget \
92		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
93		-o ${.TARGET} ${.ALLSRC}
94
95MipsGenExegesis.inc: ${LLVM_SRCS}/lib/Target/Mips/Mips.td
96	${.OBJDIR}/../../../llvm-tblgen/llvm-tblgen -gen-exegesis \
97		-I${LLVM_SRCS}/include -I${LLVM_SRCS}/lib/Target/Mips \
98		-o ${.TARGET} ${.ALLSRC}
99
100.include <bsd.obj.mk>
101