1/* This file contains the definitions and documentation for the 2 Register Transfer Expressions (rtx's) that make up the 3 Register Transfer Language (rtl) used in the Back End of the GNU compiler. 4 Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999, 2000 5 Free Software Foundation, Inc. 6 7This file is part of GCC. 8 9GCC is free software; you can redistribute it and/or modify it under 10the terms of the GNU General Public License as published by the Free 11Software Foundation; either version 2, or (at your option) any later 12version. 13 14GCC is distributed in the hope that it will be useful, but WITHOUT ANY 15WARRANTY; without even the implied warranty of MERCHANTABILITY or 16FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17for more details. 18 19You should have received a copy of the GNU General Public License 20along with GCC; see the file COPYING. If not, write to the Free 21Software Foundation, 59 Temple Place - Suite 330, Boston, MA 2202111-1307, USA. */ 23 24 25/* Expression definitions and descriptions for all targets are in this file. 26 Some will not be used for some targets. 27 28 The fields in the cpp macro call "DEF_RTL_EXPR()" 29 are used to create declarations in the C source of the compiler. 30 31 The fields are: 32 33 1. The internal name of the rtx used in the C source. 34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h". 35 By convention these are in UPPER_CASE. 36 37 2. The name of the rtx in the external ASCII format read by 38 read_rtx(), and printed by print_rtx(). 39 These names are stored in rtx_name[]. 40 By convention these are the internal (field 1) names in lower_case. 41 42 3. The print format, and type of each rtx->fld[] (field) in this rtx. 43 These formats are stored in rtx_format[]. 44 The meaning of the formats is documented in front of this array in rtl.c 45 46 4. The class of the rtx. These are stored in rtx_class and are accessed 47 via the GET_RTX_CLASS macro. They are defined as follows: 48 49 "o" an rtx code that can be used to represent an object (e.g, REG, MEM) 50 "<" an rtx code for a comparison (e.g, EQ, NE, LT) 51 "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT) 52 "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT) 53 "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE) 54 "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV) 55 "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT) 56 "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) 57 "m" an rtx code for something that matches in insns (e.g, MATCH_DUP) 58 "g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL) 59 "a" an rtx code for autoincrement addressing modes (e.g. POST_DEC) 60 "x" everything else 61 62 */ 63 64/* --------------------------------------------------------------------- 65 Expressions (and "meta" expressions) used for structuring the 66 rtl representation of a program. 67 --------------------------------------------------------------------- */ 68 69/* an expression code name unknown to the reader */ 70DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x') 71 72/* (NIL) is used by rtl reader and printer to represent a null pointer. */ 73 74DEF_RTL_EXPR(NIL, "nil", "*", 'x') 75 76 77/* include a file */ 78 79DEF_RTL_EXPR(INCLUDE, "include", "s", 'x') 80 81/* --------------------------------------------------------------------- 82 Expressions used in constructing lists. 83 --------------------------------------------------------------------- */ 84 85/* a linked list of expressions */ 86DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x') 87 88/* a linked list of instructions. 89 The insns are represented in print by their uids. */ 90DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x') 91 92/* ---------------------------------------------------------------------- 93 Expression types for machine descriptions. 94 These do not appear in actual rtl code in the compiler. 95 ---------------------------------------------------------------------- */ 96 97/* Appears only in machine descriptions. 98 Means use the function named by the second arg (the string) 99 as a predicate; if matched, store the structure that was matched 100 in the operand table at index specified by the first arg (the integer). 101 If the second arg is the null string, the structure is just stored. 102 103 A third string argument indicates to the register allocator restrictions 104 on where the operand can be allocated. 105 106 If the target needs no restriction on any instruction this field should 107 be the null string. 108 109 The string is prepended by: 110 '=' to indicate the operand is only written to. 111 '+' to indicate the operand is both read and written to. 112 113 Each character in the string represents an allocable class for an operand. 114 'g' indicates the operand can be any valid class. 115 'i' indicates the operand can be immediate (in the instruction) data. 116 'r' indicates the operand can be in a register. 117 'm' indicates the operand can be in memory. 118 'o' a subset of the 'm' class. Those memory addressing modes that 119 can be offset at compile time (have a constant added to them). 120 121 Other characters indicate target dependent operand classes and 122 are described in each target's machine description. 123 124 For instructions with more than one operand, sets of classes can be 125 separated by a comma to indicate the appropriate multi-operand constraints. 126 There must be a 1 to 1 correspondence between these sets of classes in 127 all operands for an instruction. 128 */ 129DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm') 130 131/* Appears only in machine descriptions. 132 Means match a SCRATCH or a register. When used to generate rtl, a 133 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies 134 the desired mode and the first argument is the operand number. 135 The second argument is the constraint. */ 136DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm') 137 138/* Appears only in machine descriptions. 139 Means match only something equal to what is stored in the operand table 140 at the index specified by the argument. */ 141DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm') 142 143/* Appears only in machine descriptions. 144 Means apply a predicate, AND match recursively the operands of the rtx. 145 Operand 0 is the operand-number, as in match_operand. 146 Operand 1 is a predicate to apply (as a string, a function name). 147 Operand 2 is a vector of expressions, each of which must match 148 one subexpression of the rtx this construct is matching. */ 149DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm') 150 151/* Appears only in machine descriptions. 152 Means to match a PARALLEL of arbitrary length. The predicate is applied 153 to the PARALLEL and the initial expressions in the PARALLEL are matched. 154 Operand 0 is the operand-number, as in match_operand. 155 Operand 1 is a predicate to apply to the PARALLEL. 156 Operand 2 is a vector of expressions, each of which must match the 157 corresponding element in the PARALLEL. */ 158DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm') 159 160/* Appears only in machine descriptions. 161 Means match only something equal to what is stored in the operand table 162 at the index specified by the argument. For MATCH_OPERATOR. */ 163DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm') 164 165/* Appears only in machine descriptions. 166 Means match only something equal to what is stored in the operand table 167 at the index specified by the argument. For MATCH_PARALLEL. */ 168DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm') 169 170/* Appears only in machine descriptions. 171 Operand 0 is the operand number, as in match_operand. 172 Operand 1 is the predicate to apply to the insn. */ 173DEF_RTL_EXPR(MATCH_INSN, "match_insn", "is", 'm') 174 175/* Appears only in machine descriptions. 176 Defines the pattern for one kind of instruction. 177 Operand: 178 0: names this instruction. 179 If the name is the null string, the instruction is in the 180 machine description just to be recognized, and will never be emitted by 181 the tree to rtl expander. 182 1: is the pattern. 183 2: is a string which is a C expression 184 giving an additional condition for recognizing this pattern. 185 A null string means no extra condition. 186 3: is the action to execute if this pattern is matched. 187 If this assembler code template starts with a * then it is a fragment of 188 C code to run to decide on a template to use. Otherwise, it is the 189 template to use. 190 4: optionally, a vector of attributes for this insn. 191 */ 192DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", 'x') 193 194/* Definition of a peephole optimization. 195 1st operand: vector of insn patterns to match 196 2nd operand: C expression that must be true 197 3rd operand: template or C code to produce assembler output. 198 4: optionally, a vector of attributes for this insn. 199 */ 200DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", 'x') 201 202/* Definition of a split operation. 203 1st operand: insn pattern to match 204 2nd operand: C expression that must be true 205 3rd operand: vector of insn patterns to place into a SEQUENCE 206 4th operand: optionally, some C code to execute before generating the 207 insns. This might, for example, create some RTX's and store them in 208 elements of `recog_data.operand' for use by the vector of 209 insn-patterns. 210 (`operands' is an alias here for `recog_data.operand'). */ 211DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x') 212 213/* Definition of an insn and associated split. 214 This is the concatenation, with a few modifications, of a define_insn 215 and a define_split which share the same pattern. 216 Operand: 217 0: names this instruction. 218 If the name is the null string, the instruction is in the 219 machine description just to be recognized, and will never be emitted by 220 the tree to rtl expander. 221 1: is the pattern. 222 2: is a string which is a C expression 223 giving an additional condition for recognizing this pattern. 224 A null string means no extra condition. 225 3: is the action to execute if this pattern is matched. 226 If this assembler code template starts with a * then it is a fragment of 227 C code to run to decide on a template to use. Otherwise, it is the 228 template to use. 229 4: C expression that must be true for split. This may start with "&&" 230 in which case the split condition is the logical and of the insn 231 condition and what follows the "&&" of this operand. 232 5: vector of insn patterns to place into a SEQUENCE 233 6: optionally, some C code to execute before generating the 234 insns. This might, for example, create some RTX's and store them in 235 elements of `recog_data.operand' for use by the vector of 236 insn-patterns. 237 (`operands' is an alias here for `recog_data.operand'). 238 7: optionally, a vector of attributes for this insn. */ 239DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", 'x') 240 241/* Definition of an RTL peephole operation. 242 Follows the same arguments as define_split. */ 243DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x') 244 245/* Definition of a combiner pattern. 246 Operands not defined yet. */ 247DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x') 248 249/* Define how to generate multiple insns for a standard insn name. 250 1st operand: the insn name. 251 2nd operand: vector of insn-patterns. 252 Use match_operand to substitute an element of `recog_data.operand'. 253 3rd operand: C expression that must be true for this to be available. 254 This may not test any operands. 255 4th operand: Extra C code to execute before generating the insns. 256 This might, for example, create some RTX's and store them in 257 elements of `recog_data.operand' for use by the vector of 258 insn-patterns. 259 (`operands' is an alias here for `recog_data.operand'). */ 260DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x') 261 262/* Define a requirement for delay slots. 263 1st operand: Condition involving insn attributes that, if true, 264 indicates that the insn requires the number of delay slots 265 shown. 266 2nd operand: Vector whose length is the three times the number of delay 267 slots required. 268 Each entry gives three conditions, each involving attributes. 269 The first must be true for an insn to occupy that delay slot 270 location. The second is true for all insns that can be 271 annulled if the branch is true and the third is true for all 272 insns that can be annulled if the branch is false. 273 274 Multiple DEFINE_DELAYs may be present. They indicate differing 275 requirements for delay slots. */ 276DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x') 277 278/* Define a set of insns that requires a function unit. This means that 279 these insns produce their result after a delay and that there may be 280 restrictions on the number of insns of this type that can be scheduled 281 simultaneously. 282 283 More than one DEFINE_FUNCTION_UNIT can be specified for a function unit. 284 Each gives a set of operations and associated delays. The first three 285 operands must be the same for each operation for the same function unit. 286 287 All delays are specified in cycles. 288 289 1st operand: Name of function unit (mostly for documentation) 290 2nd operand: Number of identical function units in CPU 291 3rd operand: Total number of simultaneous insns that can execute on this 292 function unit; 0 if unlimited. 293 4th operand: Condition involving insn attribute, that, if true, specifies 294 those insns that this expression applies to. 295 5th operand: Constant delay after which insn result will be 296 available. 297 6th operand: Delay until next insn can be scheduled on the function unit 298 executing this operation. The meaning depends on whether or 299 not the next operand is supplied. 300 7th operand: If this operand is not specified, the 6th operand gives the 301 number of cycles after the instruction matching the 4th 302 operand begins using the function unit until a subsequent 303 insn can begin. A value of zero should be used for a 304 unit with no issue constraints. If only one operation can 305 be executed a time and the unit is busy for the entire time, 306 the 3rd operand should be specified as 1, the 6th operand 307 should be specified as 0, and the 7th operand should not 308 be specified. 309 310 If this operand is specified, it is a list of attribute 311 expressions. If an insn for which any of these expressions 312 is true is currently executing on the function unit, the 313 issue delay will be given by the 6th operand. Otherwise, 314 the insn can be immediately scheduled (subject to the limit 315 on the number of simultaneous operations executing on the 316 unit.) */ 317DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x') 318 319/* Define attribute computation for `asm' instructions. */ 320DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' ) 321 322/* Definition of a conditional execution meta operation. Automatically 323 generates new instances of DEFINE_INSN, selected by having attribute 324 "predicable" true. The new pattern will contain a COND_EXEC and the 325 predicate at top-level. 326 327 Operand: 328 0: The predicate pattern. The top-level form should match a 329 relational operator. Operands should have only one alternative. 330 1: A C expression giving an additional condition for recognizing 331 the generated pattern. 332 2: A template or C code to produce assembler output. */ 333DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", 'x') 334 335/* SEQUENCE appears in the result of a `gen_...' function 336 for a DEFINE_EXPAND that wants to make several insns. 337 Its elements are the bodies of the insns that should be made. 338 `emit_insn' takes the SEQUENCE apart and makes separate insns. */ 339DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x') 340 341/* Refers to the address of its argument. This is only used in alias.c. */ 342DEF_RTL_EXPR(ADDRESS, "address", "e", 'm') 343 344/* ---------------------------------------------------------------------- 345 Constructions for CPU pipeline description described by NDFAs. 346 These do not appear in actual rtl code in the compiler. 347 ---------------------------------------------------------------------- */ 348 349/* (define_cpu_unit string [string]) describes cpu functional 350 units (separated by comma). 351 352 1st operand: Names of cpu functional units. 353 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON). 354 355 All define_reservations, define_cpu_units, and 356 define_query_cpu_units should have unique names which may not be 357 "nothing". */ 358DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", 'x') 359 360/* (define_query_cpu_unit string [string]) describes cpu functional 361 units analogously to define_cpu_unit. If we use automaton without 362 minimization, the reservation of such units can be queried for 363 automaton state. */ 364DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", 'x') 365 366/* (exclusion_set string string) means that each CPU functional unit 367 in the first string can not be reserved simultaneously with any 368 unit whose name is in the second string and vise versa. CPU units 369 in the string are separated by commas. For example, it is useful 370 for description CPU with fully pipelined floating point functional 371 unit which can execute simultaneously only single floating point 372 insns or only double floating point insns. All CPU functional 373 units in a set should belong the same automaton. */ 374DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", 'x') 375 376/* (presence_set string string) means that each CPU functional unit in 377 the first string can not be reserved unless at least one of units 378 whose names are in the second string is reserved. This is an 379 asymmetric relation. CPU units in the string are separated by 380 commas. For example, it is useful for description that slot1 is 381 reserved after slot0 reservation for VLIW processor. All CPU 382 functional units in a set should belong the same automaton. */ 383DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", 'x') 384 385/* (absence_set string string) means that each CPU functional unit in 386 the first string can not be reserved only if each unit whose name 387 is in the second string is not reserved. This is an asymmetric 388 relation (actually exclusion set is analogous to this one but it is 389 symmetric). CPU units in the string are separated by commas. For 390 example, it is useful for description that slot0 can not be 391 reserved after slot1 or slot2 reservation for VLIW processor. All 392 CPU functional units in a set should belong the same automaton. */ 393DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", 'x') 394 395/* (define_bypass number out_insn_names in_insn_names) names bypass 396 with given latency (the first number) from insns given by the first 397 string (see define_insn_reservation) into insns given by the second 398 string. Insn names in the strings are separated by commas. The 399 third operand is optional name of function which is additional 400 guard for the bypass. The function will get the two insns as 401 parameters. If the function returns zero the bypass will be 402 ignored for this case. Additional guard is necessary to recognize 403 complicated bypasses, e.g. when consumer is load address. */ 404DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", 'x') 405 406/* (define_automaton string) describes names of automata generated and 407 used for pipeline hazards recognition. The names are separated by 408 comma. Actually it is possibly to generate the single automaton 409 but unfortunately it can be very large. If we use more one 410 automata, the summary size of the automata usually is less than the 411 single one. The automaton name is used in define_cpu_unit and 412 define_query_cpu_unit. All automata should have unique names. */ 413DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", 'x') 414 415/* (automata_option string) describes option for generation of 416 automata. Currently there are the following options: 417 418 o "no-minimization" which makes no minimization of automata. This 419 is only worth to do when we are going to query CPU functional 420 unit reservations in an automaton state. 421 422 o "time" which means printing additional time statistics about 423 generation of automata. 424 425 o "v" which means generation of file describing the result 426 automata. The file has suffix `.dfa' and can be used for the 427 description verification and debugging. 428 429 o "w" which means generation of warning instead of error for 430 non-critical errors. 431 432 o "ndfa" which makes nondeterministic finite state automata. */ 433DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", 'x') 434 435/* (define_reservation string string) names reservation (the first 436 string) of cpu functional units (the 2nd string). Sometimes unit 437 reservations for different insns contain common parts. In such 438 case, you can describe common part and use its name (the 1st 439 parameter) in regular expression in define_insn_reservation. All 440 define_reservations, define_cpu_units, and define_query_cpu_units 441 should have unique names which may not be "nothing". */ 442DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", 'x') 443 444/* (define_insn_reservation name default_latency condition regexpr) 445 describes reservation of cpu functional units (the 3nd operand) for 446 instruction which is selected by the condition (the 2nd parameter). 447 The first parameter is used for output of debugging information. 448 The reservations are described by a regular expression according 449 the following syntax: 450 451 regexp = regexp "," oneof 452 | oneof 453 454 oneof = oneof "|" allof 455 | allof 456 457 allof = allof "+" repeat 458 | repeat 459 460 repeat = element "*" number 461 | element 462 463 element = cpu_function_unit_name 464 | reservation_name 465 | result_name 466 | "nothing" 467 | "(" regexp ")" 468 469 1. "," is used for describing start of the next cycle in 470 reservation. 471 472 2. "|" is used for describing the reservation described by the 473 first regular expression *or* the reservation described by the 474 second regular expression *or* etc. 475 476 3. "+" is used for describing the reservation described by the 477 first regular expression *and* the reservation described by the 478 second regular expression *and* etc. 479 480 4. "*" is used for convinience and simply means sequence in 481 which the regular expression are repeated NUMBER times with 482 cycle advancing (see ","). 483 484 5. cpu functional unit name which means its reservation. 485 486 6. reservation name -- see define_reservation. 487 488 7. string "nothing" means no units reservation. */ 489 490DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", 'x') 491 492/* ---------------------------------------------------------------------- 493 Expressions used for insn attributes. These also do not appear in 494 actual rtl code in the compiler. 495 ---------------------------------------------------------------------- */ 496 497/* Definition of an insn attribute. 498 1st operand: name of the attribute 499 2nd operand: comma-separated list of possible attribute values 500 3rd operand: expression for the default value of the attribute. */ 501DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x') 502 503/* Marker for the name of an attribute. */ 504DEF_RTL_EXPR(ATTR, "attr", "s", 'x') 505 506/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and 507 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that 508 pattern. 509 510 (set_attr "name" "value") is equivalent to 511 (set (attr "name") (const_string "value")) */ 512DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x') 513 514/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to 515 specify that attribute values are to be assigned according to the 516 alternative matched. 517 518 The following three expressions are equivalent: 519 520 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") 521 (eq_attrq "alternative" "2") (const_string "a2")] 522 (const_string "a3"))) 523 (set_attr_alternative "att" [(const_string "a1") (const_string "a2") 524 (const_string "a3")]) 525 (set_attr "att" "a1,a2,a3") 526 */ 527DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x') 528 529/* A conditional expression true if the value of the specified attribute of 530 the current insn equals the specified value. The first operand is the 531 attribute name and the second is the comparison value. */ 532DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x') 533 534/* A conditional expression which is true if the specified flag is 535 true for the insn being scheduled in reorg. 536 537 genattr.c defines the following flags which can be tested by 538 (attr_flag "foo") expressions in eligible_for_delay. 539 540 forward, backward, very_likely, likely, very_unlikely, and unlikely. */ 541 542DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x') 543 544/* ---------------------------------------------------------------------- 545 Expression types used for things in the instruction chain. 546 547 All formats must start with "iuu" to handle the chain. 548 Each insn expression holds an rtl instruction and its semantics 549 during back-end processing. 550 See macros's in "rtl.h" for the meaning of each rtx->fld[]. 551 552 ---------------------------------------------------------------------- */ 553 554/* An instruction that cannot jump. */ 555DEF_RTL_EXPR(INSN, "insn", "iuuBteiee", 'i') 556 557/* An instruction that can possibly jump. 558 Fields ( rtx->fld[] ) have exact same meaning as INSN's. */ 559DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBteiee0", 'i') 560 561/* An instruction that can possibly call a subroutine 562 but which will not change which instruction comes next 563 in the current function. 564 Field ( rtx->fld[9] ) is CALL_INSN_FUNCTION_USAGE. 565 All other fields ( rtx->fld[] ) have exact same meaning as INSN's. */ 566DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBteieee", 'i') 567 568/* A marker that indicates that control will not flow through. */ 569DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", 'x') 570 571/* Holds a label that is followed by instructions. 572 Operand: 573 5: is used in jump.c for the use-count of the label. 574 6: is used in flow.c to point to the chain of label_ref's to this label. 575 7: is a number that is unique in the entire compilation. 576 8: is the user-given name of the label, if any. */ 577DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", 'x') 578 579/* Say where in the code a source line starts, for symbol table's sake. 580 Operand: 581 5: filename, if line number > 0, note-specific data otherwise. 582 6: line number if > 0, enum note_insn otherwise. 583 7: unique number if line number == note_insn_deleted_label. 584 8-9: padding so that notes and insns are the same size, and thus 585 allocated from the same page ordering. */ 586DEF_RTL_EXPR(NOTE, "note", "iuuB0ni00", 'x') 587 588/* ---------------------------------------------------------------------- 589 Top level constituents of INSN, JUMP_INSN and CALL_INSN. 590 ---------------------------------------------------------------------- */ 591 592/* Conditionally execute code. 593 Operand 0 is the condition that if true, the code is executed. 594 Operand 1 is the code to be executed (typically a SET). 595 596 Semantics are that there are no side effects if the condition 597 is false. This pattern is created automatically by the if_convert 598 pass run after reload or by target-specific splitters. */ 599DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", 'x') 600 601/* Several operations to be done in parallel (perhaps under COND_EXEC). */ 602DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x') 603 604/* A string that is passed through to the assembler as input. 605 One can obviously pass comments through by using the 606 assembler comment syntax. 607 These occur in an insn all by themselves as the PATTERN. 608 They also appear inside an ASM_OPERANDS 609 as a convenient way to hold a string. */ 610DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x') 611 612/* An assembler instruction with operands. 613 1st operand is the instruction template. 614 2nd operand is the constraint for the output. 615 3rd operand is the number of the output this expression refers to. 616 When an insn stores more than one value, a separate ASM_OPERANDS 617 is made for each output; this integer distinguishes them. 618 4th is a vector of values of input operands. 619 5th is a vector of modes and constraints for the input operands. 620 Each element is an ASM_INPUT containing a constraint string 621 and whose mode indicates the mode of the input operand. 622 6th is the name of the containing source file. 623 7th is the source line number. */ 624DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x') 625 626/* A machine-specific operation. 627 1st operand is a vector of operands being used by the operation so that 628 any needed reloads can be done. 629 2nd operand is a unique value saying which of a number of machine-specific 630 operations is to be performed. 631 (Note that the vector must be the first operand because of the way that 632 genrecog.c record positions within an insn.) 633 This can occur all by itself in a PATTERN, as a component of a PARALLEL, 634 or inside an expression. */ 635DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x') 636 637/* Similar, but a volatile operation and one which may trap. */ 638DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x') 639 640/* Vector of addresses, stored as full words. */ 641/* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ 642DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x') 643 644/* Vector of address differences X0 - BASE, X1 - BASE, ... 645 First operand is BASE; the vector contains the X's. 646 The machine mode of this rtx says how much space to leave 647 for each difference and is adjusted by branch shortening if 648 CASE_VECTOR_SHORTEN_MODE is defined. 649 The third and fourth operands store the target labels with the 650 minimum and maximum addresses respectively. 651 The fifth operand stores flags for use by branch shortening. 652 Set at the start of shorten_branches: 653 min_align: the minimum alignment for any of the target labels. 654 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC. 655 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC. 656 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC. 657 min_after_base: true iff minimum address target label is after BASE. 658 max_after_base: true iff maximum address target label is after BASE. 659 Set by the actual branch shortening process: 660 offset_unsigned: true iff offsets have to be treated as unsigned. 661 scale: scaling that is necessary to make offsets fit into the mode. 662 663 The third, fourth and fifth operands are only valid when 664 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing 665 compilations. */ 666 667DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x') 668 669/* Memory prefetch, with attributes supported on some targets. 670 Operand 1 is the address of the memory to fetch. 671 Operand 2 is 1 for a write access, 0 otherwise. 672 Operand 3 is the level of temporal locality; 0 means there is no 673 temporal locality and 1, 2, and 3 are for increasing levels of temporal 674 locality. 675 676 The attributes specified by operands 2 and 3 are ignored for targets 677 whose prefetch instructions do not support them. */ 678DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", 'x') 679 680/* ---------------------------------------------------------------------- 681 At the top level of an instruction (perhaps under PARALLEL). 682 ---------------------------------------------------------------------- */ 683 684/* Assignment. 685 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. 686 Operand 2 is the value stored there. 687 ALL assignment must use SET. 688 Instructions that do multiple assignments must use multiple SET, 689 under PARALLEL. */ 690DEF_RTL_EXPR(SET, "set", "ee", 'x') 691 692/* Indicate something is used in a way that we don't want to explain. 693 For example, subroutine calls will use the register 694 in which the static chain is passed. */ 695DEF_RTL_EXPR(USE, "use", "e", 'x') 696 697/* Indicate something is clobbered in a way that we don't want to explain. 698 For example, subroutine calls will clobber some physical registers 699 (the ones that are by convention not saved). */ 700DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x') 701 702/* Call a subroutine. 703 Operand 1 is the address to call. 704 Operand 2 is the number of arguments. */ 705 706DEF_RTL_EXPR(CALL, "call", "ee", 'x') 707 708/* Return from a subroutine. */ 709 710DEF_RTL_EXPR(RETURN, "return", "", 'x') 711 712/* Conditional trap. 713 Operand 1 is the condition. 714 Operand 2 is the trap code. 715 For an unconditional trap, make the condition (const_int 1). */ 716DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x') 717 718/* Placeholder for _Unwind_Resume before we know if a function call 719 or a branch is needed. Operand 1 is the exception region from 720 which control is flowing. */ 721DEF_RTL_EXPR(RESX, "resx", "i", 'x') 722 723/* ---------------------------------------------------------------------- 724 Primitive values for use in expressions. 725 ---------------------------------------------------------------------- */ 726 727/* numeric integer constant */ 728DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o') 729 730/* numeric floating point constant. 731 Operands hold the value. They are all 'w' and there may be from 2 to 6; 732 see real.h. */ 733DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o') 734 735/* Describes a vector constant. */ 736DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", 'x') 737 738/* String constant. Used only for attributes right now. */ 739DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o') 740 741/* This is used to encapsulate an expression whose value is constant 742 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be 743 recognized as a constant operand rather than by arithmetic instructions. */ 744 745DEF_RTL_EXPR(CONST, "const", "e", 'o') 746 747/* program counter. Ordinary jumps are represented 748 by a SET whose first operand is (PC). */ 749DEF_RTL_EXPR(PC, "pc", "", 'o') 750 751/* Used in the cselib routines to describe a value. */ 752DEF_RTL_EXPR(VALUE, "value", "0", 'o') 753 754/* A register. The "operand" is the register number, accessed with 755 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER 756 than a hardware register is being referred to. The second operand 757 holds the original register number - this will be different for a 758 pseudo register that got turned into a hard register. 759 This rtx needs to have as many (or more) fields as a MEM, since we 760 can change REG rtx's into MEMs during reload. */ 761DEF_RTL_EXPR(REG, "reg", "i0", 'o') 762 763/* A scratch register. This represents a register used only within a 764 single insn. It will be turned into a REG during register allocation 765 or reload unless the constraint indicates that the register won't be 766 needed, in which case it can remain a SCRATCH. This code is 767 marked as having one operand so it can be turned into a REG. */ 768DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o') 769 770/* One word of a multi-word value. 771 The first operand is the complete value; the second says which word. 772 The WORDS_BIG_ENDIAN flag controls whether word number 0 773 (as numbered in a SUBREG) is the most or least significant word. 774 775 This is also used to refer to a value in a different machine mode. 776 For example, it can be used to refer to a SImode value as if it were 777 Qimode, or vice versa. Then the word number is always 0. */ 778DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x') 779 780/* This one-argument rtx is used for move instructions 781 that are guaranteed to alter only the low part of a destination. 782 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) 783 has an unspecified effect on the high part of REG, 784 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...)) 785 is guaranteed to alter only the bits of REG that are in HImode. 786 787 The actual instruction used is probably the same in both cases, 788 but the register constraints may be tighter when STRICT_LOW_PART 789 is in use. */ 790 791DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x') 792 793/* (CONCAT a b) represents the virtual concatenation of a and b 794 to make a value that has as many bits as a and b put together. 795 This is used for complex values. Normally it appears only 796 in DECL_RTLs and during RTL generation, but not in the insn chain. */ 797DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o') 798 799/* A memory location; operand is the address. The second operand is the 800 alias set to which this MEM belongs. We use `0' instead of `w' for this 801 field so that the field need not be specified in machine descriptions. */ 802DEF_RTL_EXPR(MEM, "mem", "e0", 'o') 803 804/* Reference to an assembler label in the code for this function. 805 The operand is a CODE_LABEL found in the insn chain. 806 The unprinted fields 1 and 2 are used in flow.c for the 807 LABEL_NEXTREF and CONTAINING_INSN. */ 808DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o') 809 810/* Reference to a named label: the string that is the first operand, 811 with `_' added implicitly in front. 812 Exception: if the first character explicitly given is `*', 813 to give it to the assembler, remove the `*' and do not add `_'. */ 814DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o') 815 816/* The condition code register is represented, in our imagination, 817 as a register holding a value that can be compared to zero. 818 In fact, the machine has already compared them and recorded the 819 results; but instructions that look at the condition code 820 pretend to be looking at the entire value and comparing it. */ 821DEF_RTL_EXPR(CC0, "cc0", "", 'o') 822 823/* Reference to the address of a register. Removed by purge_addressof after 824 CSE has elided as many as possible. 825 1st operand: the register we may need the address of. 826 2nd operand: the original pseudo regno we were generated for. 827 3rd operand: the decl for the object in the register, for 828 put_reg_in_stack. */ 829 830DEF_RTL_EXPR(ADDRESSOF, "addressof", "eit", 'o') 831 832/* ===================================================================== 833 A QUEUED expression really points to a member of the queue of instructions 834 to be output later for postincrement/postdecrement. 835 QUEUED expressions never become part of instructions. 836 When a QUEUED expression would be put into an instruction, 837 instead either the incremented variable or a copy of its previous 838 value is used. 839 840 Operands are: 841 0. the variable to be incremented (a REG rtx). 842 1. the incrementing instruction, or 0 if it hasn't been output yet. 843 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet. 844 3. the body to use for the incrementing instruction 845 4. the next QUEUED expression in the queue. 846 ====================================================================== */ 847 848DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x') 849 850/* ---------------------------------------------------------------------- 851 Expressions for operators in an rtl pattern 852 ---------------------------------------------------------------------- */ 853 854/* if_then_else. This is used in representing ordinary 855 conditional jump instructions. 856 Operand: 857 0: condition 858 1: then expr 859 2: else expr */ 860DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3') 861 862/* General conditional. The first operand is a vector composed of pairs of 863 expressions. The first element of each pair is evaluated, in turn. 864 The value of the conditional is the second expression of the first pair 865 whose first expression evaluates nonzero. If none of the expressions is 866 true, the second operand will be used as the value of the conditional. 867 868 This should be replaced with use of IF_THEN_ELSE. */ 869DEF_RTL_EXPR(COND, "cond", "Ee", 'x') 870 871/* Comparison, produces a condition code result. */ 872DEF_RTL_EXPR(COMPARE, "compare", "ee", '2') 873 874/* plus */ 875DEF_RTL_EXPR(PLUS, "plus", "ee", 'c') 876 877/* Operand 0 minus operand 1. */ 878DEF_RTL_EXPR(MINUS, "minus", "ee", '2') 879 880/* Minus operand 0. */ 881DEF_RTL_EXPR(NEG, "neg", "e", '1') 882 883DEF_RTL_EXPR(MULT, "mult", "ee", 'c') 884 885/* Operand 0 divided by operand 1. */ 886DEF_RTL_EXPR(DIV, "div", "ee", '2') 887/* Remainder of operand 0 divided by operand 1. */ 888DEF_RTL_EXPR(MOD, "mod", "ee", '2') 889 890/* Unsigned divide and remainder. */ 891DEF_RTL_EXPR(UDIV, "udiv", "ee", '2') 892DEF_RTL_EXPR(UMOD, "umod", "ee", '2') 893 894/* Bitwise operations. */ 895DEF_RTL_EXPR(AND, "and", "ee", 'c') 896 897DEF_RTL_EXPR(IOR, "ior", "ee", 'c') 898 899DEF_RTL_EXPR(XOR, "xor", "ee", 'c') 900 901DEF_RTL_EXPR(NOT, "not", "e", '1') 902 903/* Operand: 904 0: value to be shifted. 905 1: number of bits. */ 906DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') /* shift left */ 907DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') /* rotate left */ 908DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') /* arithmetic shift right */ 909DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') /* logical shift right */ 910DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') /* rotate right */ 911 912/* Minimum and maximum values of two operands. We need both signed and 913 unsigned forms. (We cannot use MIN for SMIN because it conflicts 914 with a macro of the same name.) */ 915 916DEF_RTL_EXPR(SMIN, "smin", "ee", 'c') 917DEF_RTL_EXPR(SMAX, "smax", "ee", 'c') 918DEF_RTL_EXPR(UMIN, "umin", "ee", 'c') 919DEF_RTL_EXPR(UMAX, "umax", "ee", 'c') 920 921/* These unary operations are used to represent incrementation 922 and decrementation as they occur in memory addresses. 923 The amount of increment or decrement are not represented 924 because they can be understood from the machine-mode of the 925 containing MEM. These operations exist in only two cases: 926 1. pushes onto the stack. 927 2. created automatically by the life_analysis pass in flow.c. */ 928DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'a') 929DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'a') 930DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'a') 931DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'a') 932 933/* These binary operations are used to represent generic address 934 side-effects in memory addresses, except for simple incrementation 935 or decrementation which use the above operations. They are 936 created automatically by the life_analysis pass in flow.c. 937 The first operand is a REG which is used as the address. 938 The second operand is an expression that is assigned to the 939 register, either before (PRE_MODIFY) or after (POST_MODIFY) 940 evaluating the address. 941 Currently, the compiler can only handle second operands of the 942 form (plus (reg) (reg)) and (plus (reg) (const_int)), where 943 the first operand of the PLUS has to be the same register as 944 the first operand of the *_MODIFY. */ 945DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'a') 946DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'a') 947 948/* Comparison operations. The ordered comparisons exist in two 949 flavors, signed and unsigned. */ 950DEF_RTL_EXPR(NE, "ne", "ee", '<') 951DEF_RTL_EXPR(EQ, "eq", "ee", '<') 952DEF_RTL_EXPR(GE, "ge", "ee", '<') 953DEF_RTL_EXPR(GT, "gt", "ee", '<') 954DEF_RTL_EXPR(LE, "le", "ee", '<') 955DEF_RTL_EXPR(LT, "lt", "ee", '<') 956DEF_RTL_EXPR(GEU, "geu", "ee", '<') 957DEF_RTL_EXPR(GTU, "gtu", "ee", '<') 958DEF_RTL_EXPR(LEU, "leu", "ee", '<') 959DEF_RTL_EXPR(LTU, "ltu", "ee", '<') 960 961/* Additional floating point unordered comparision flavors. */ 962DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<') 963DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<') 964 965/* These are equivalent to unordered or ... */ 966DEF_RTL_EXPR(UNEQ, "uneq", "ee", '<') 967DEF_RTL_EXPR(UNGE, "unge", "ee", '<') 968DEF_RTL_EXPR(UNGT, "ungt", "ee", '<') 969DEF_RTL_EXPR(UNLE, "unle", "ee", '<') 970DEF_RTL_EXPR(UNLT, "unlt", "ee", '<') 971 972/* This is an ordered NE, ie !UNEQ, ie false for NaN. */ 973DEF_RTL_EXPR(LTGT, "ltgt", "ee", '<') 974 975/* Represents the result of sign-extending the sole operand. 976 The machine modes of the operand and of the SIGN_EXTEND expression 977 determine how much sign-extension is going on. */ 978DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1') 979 980/* Similar for zero-extension (such as unsigned short to int). */ 981DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1') 982 983/* Similar but here the operand has a wider mode. */ 984DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1') 985 986/* Similar for extending floating-point values (such as SFmode to DFmode). */ 987DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1') 988DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1') 989 990/* Conversion of fixed point operand to floating point value. */ 991DEF_RTL_EXPR(FLOAT, "float", "e", '1') 992 993/* With fixed-point machine mode: 994 Conversion of floating point operand to fixed point value. 995 Value is defined only when the operand's value is an integer. 996 With floating-point machine mode (and operand with same mode): 997 Operand is rounded toward zero to produce an integer value 998 represented in floating point. */ 999DEF_RTL_EXPR(FIX, "fix", "e", '1') 1000 1001/* Conversion of unsigned fixed point operand to floating point value. */ 1002DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1') 1003 1004/* With fixed-point machine mode: 1005 Conversion of floating point operand to *unsigned* fixed point value. 1006 Value is defined only when the operand's value is an integer. */ 1007DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1') 1008 1009/* Absolute value */ 1010DEF_RTL_EXPR(ABS, "abs", "e", '1') 1011 1012/* Square root */ 1013DEF_RTL_EXPR(SQRT, "sqrt", "e", '1') 1014 1015/* Find first bit that is set. 1016 Value is 1 + number of trailing zeros in the arg., 1017 or 0 if arg is 0. */ 1018DEF_RTL_EXPR(FFS, "ffs", "e", '1') 1019 1020/* Reference to a signed bit-field of specified size and position. 1021 Operand 0 is the memory unit (usually SImode or QImode) which 1022 contains the field's first bit. Operand 1 is the width, in bits. 1023 Operand 2 is the number of bits in the memory unit before the 1024 first bit of this field. 1025 If BITS_BIG_ENDIAN is defined, the first bit is the msb and 1026 operand 2 counts from the msb of the memory unit. 1027 Otherwise, the first bit is the lsb and operand 2 counts from 1028 the lsb of the memory unit. */ 1029DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b') 1030 1031/* Similar for unsigned bit-field. */ 1032DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b') 1033 1034/* For RISC machines. These save memory when splitting insns. */ 1035 1036/* HIGH are the high-order bits of a constant expression. */ 1037DEF_RTL_EXPR(HIGH, "high", "e", 'o') 1038 1039/* LO_SUM is the sum of a register and the low-order bits 1040 of a constant expression. */ 1041DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o') 1042 1043/* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn. 1044 Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of 1045 the registers that can be substituted within this range. Operand 3 is the 1046 number of calls in the range. Operand 4 is the number of insns in the 1047 range. Operand 5 is the unique range number for this range. Operand 6 is 1048 the basic block # of the start of the live range. Operand 7 is the basic 1049 block # of the end of the live range. Operand 8 is the loop depth. Operand 1050 9 is a bitmap of the registers live at the start of the range. Operand 10 1051 is a bitmap of the registers live at the end of the range. Operand 11 is 1052 marker number for the start of the range. Operand 12 is the marker number 1053 for the end of the range. */ 1054DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", 'x') 1055 1056/* Registers that can be substituted within the range. Operand 0 is the 1057 original pseudo register number. Operand 1 will be filled in with the 1058 pseudo register the value is copied for the duration of the range. Operand 1059 2 is the number of references within the range to the register. Operand 3 1060 is the number of sets or clobbers of the register in the range. Operand 4 1061 is the number of deaths the register has. Operand 5 is the copy flags that 1062 give the status of whether a copy is needed from the original register to 1063 the new register at the beginning of the range, or whether a copy from the 1064 new register back to the original at the end of the range. Operand 6 is the 1065 live length. Operand 7 is the number of calls that this register is live 1066 across. Operand 8 is the symbol node of the variable if the register is a 1067 user variable. Operand 9 is the block node that the variable is declared 1068 in if the register is a user variable. */ 1069DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x') 1070 1071/* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of 1072 the different ranges a variable is in where it is copied to a different 1073 pseudo register. Operand 1 is the block that the variable is declared in. 1074 Operand 2 is the number of distinct ranges. */ 1075DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", 'x') 1076 1077/* Information about the registers that are live at the current point. Operand 1078 0 is the live bitmap. Operand 1 is the original block number. */ 1079DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x') 1080 1081/* A unary `__builtin_constant_p' expression. These are only emitted 1082 during RTL generation, and then only if optimize > 0. They are 1083 eliminated by the first CSE pass. */ 1084DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x') 1085 1086/* A placeholder for a CALL_INSN which may be turned into a normal call, 1087 a sibling (tail) call or tail recursion. 1088 1089 Immediately after RTL generation, this placeholder will be replaced 1090 by the insns to perform the call, sibcall or tail recursion. 1091 1092 This RTX has 4 operands. The first three are lists of instructions to 1093 perform the call as a normal call, sibling call and tail recursion 1094 respectively. The latter two lists may be NULL, the first may never 1095 be NULL. 1096 1097 The last operand is the tail recursion CODE_LABEL, which may be NULL if no 1098 potential tail recursive calls were found. 1099 1100 The tail recursion label is needed so that we can clear LABEL_PRESERVE_P 1101 after we select a call method. 1102 1103 This method of tail-call elimination is intended to be replaced by 1104 tree-based optimizations once front-end conversions are complete. */ 1105DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x') 1106 1107/* Describes a merge operation between two vector values. 1108 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask 1109 that specifies where the parts of the result are taken from. Set bits 1110 indicate operand 0, clear bits indicate operand 1. The parts are defined 1111 by the mode of the vectors. */ 1112DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", '3') 1113 1114/* Describes an operation that selects parts of a vector. 1115 Operands 0 is the source vector, operand 1 is a PARALLEL that contains 1116 a CONST_INT for each of the subparts of the result vector, giving the 1117 number of the source subpart that should be stored into it. */ 1118DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", '2') 1119 1120/* Describes a vector concat operation. Operands 0 and 1 are the source 1121 vectors, the result is a vector that is as long as operands 0 and 1 1122 combined and is the concatenation of the two source vectors. */ 1123DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", '2') 1124 1125/* Describes an operation that converts a small vector into a larger one by 1126 duplicating the input values. The output vector mode must have the same 1127 submodes as the input vector mode, and the number of output parts must be 1128 an integer multiple of the number of input parts. */ 1129DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", '1') 1130 1131/* Addition with signed saturation */ 1132DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c') 1133 1134/* Addition with unsigned saturation */ 1135DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", 'c') 1136 1137/* Operand 0 minus operand 1, with signed saturation. */ 1138DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", '2') 1139 1140/* Operand 0 minus operand 1, with unsigned saturation. */ 1141DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", '2') 1142 1143/* Signed saturating truncate. */ 1144DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", '1') 1145 1146/* Unsigned saturating truncate. */ 1147DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", '1') 1148 1149/* The SSA phi operator. 1150 1151 The argument is a vector of 2N rtxes. Element 2N+1 is a CONST_INT 1152 containing the block number of the predecessor through which control 1153 has passed when the register at element 2N is used. 1154 1155 Note that PHI may only appear at the beginning of a basic block. 1156 1157 ??? There may be multiple PHI insns, but they are all evaluated 1158 in parallel. This probably ought to be changed to use a real 1159 PARALLEL, as that would be less confusing and more in the spirit 1160 of canonical RTL. It is, however, easier to manipulate this way. */ 1161DEF_RTL_EXPR(PHI, "phi", "E", 'x') 1162 1163 1164/* 1165Local variables: 1166mode:c 1167End: 1168*/ 1169