1.\" $OpenBSD: arm_sync_icache.2,v 1.4 2013/08/14 06:32:26 jmc Exp $ 2.\" $NetBSD: arm_sync_icache.2,v 1.5 2004/02/13 09:56:47 wiz Exp $ 3.\" 4.\" Copyright (c) 1996 Mark Brinicombe 5.\" All rights reserved. 6.\" 7.\" Redistribution and use in source and binary forms, with or without 8.\" modification, are permitted provided that the following conditions 9.\" are met: 10.\" 1. Redistributions of source code must retain the above copyright 11.\" notice, this list of conditions and the following disclaimer. 12.\" 2. Redistributions in binary form must reproduce the above copyright 13.\" notice, this list of conditions and the following disclaimer in the 14.\" documentation and/or other materials provided with the distribution. 15.\" 3. All advertising materials mentioning features or use of this software 16.\" must display the following acknowledgement: 17.\" This product includes software developed by Mark Brinicombe 18.\" 4. Neither the name of the University nor the names of its contributors 19.\" may be used to endorse or promote products derived from this software 20.\" without specific prior written permission. 21.\" 22.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32.\" SUCH DAMAGE. 33.\" 34.Dd $Mdocdate: August 14 2013 $ 35.Dt ARM_SYNC_ICACHE 2 arm 36.Os 37.Sh NAME 38.Nm arm_sync_icache 39.Nd clean the CPU data cache and flush the CPU instruction cache 40.Sh SYNOPSIS 41.In machine/sysarch.h 42.Ft int 43.Fn arm_sync_icache "u_int addr" "int len" 44.Sh DESCRIPTION 45.Fn arm_sync_icache 46will make sure that all the entries in the processor instruction cache 47are synchronized with main memory and that any data in a write back cache 48has been cleaned. 49Some ARM processors (e.g. SA110) have separate instruction and data 50caches, thus any dynamically generated or modified code needs to be 51written back from any data caches to main memory and the instruction 52cache needs to be synchronized with main memory. 53.Pp 54On such processors, 55.Fn arm_sync_icache 56will clean the data cache and invalidate the processor instruction cache 57to force reloading from main memory. 58On processors that have a shared instruction and data cache and have a 59write through cache (e.g. ARM6), no action needs to be taken. 60.Pp 61The routine takes a start address 62.Fa addr 63and a length 64.Fa len 65to describe the area of memory that needs to be cleaned and synchronized. 66.Sh ERRORS 67.Fn arm_sync_icache 68will never fail so will always return 0. 69.Sh REFERENCES 70StrongARM Data Sheet 71