1/* $OpenBSD: _setjmp.S,v 1.4 2005/08/07 16:40:15 espie Exp $ */ 2 3/* 4 * Copyright (c) 2002 Opsycon AB (www.opsycon.se / www.opsycon.com) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of Opsycon AB nor the names of its contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 19 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 22 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32#include <machine/asm.h> 33#include <machine/regnum.h> 34#include <machine/signal.h> 35 36/* 37 * _setjmp, _longjmp (not restoring signal state) 38 * 39 * XXX FPSET should probably be taken from SR setting. hmmm... 40 * GPOFF and FRAMESIZE must be the same for both _setjmp and _longjmp! 41 * 42 */ 43 44FRAMESZ= MKFSIZ(0,4) 45GPOFF= FRAMESZ-2*REGSZ 46 47LEAF(_setjmp, FRAMESZ) 48 PTR_SUBU sp, FRAMESZ 49 SETUP_GP64(GPOFF, _setjmp) 50 .set noreorder 51#if defined(__mips64) 52 dli v0, 0xACEDBADE # sigcontext magic number 53#else 54 li v0, 0xACEDBADE # sigcontext magic number 55#endif 56 REG_S v0, SC_REGS+ZERO*REGSZ(a0) 57 REG_S s0, SC_REGS+S0*REGSZ(a0) 58 REG_S s1, SC_REGS+S1*REGSZ(a0) 59 REG_S s2, SC_REGS+S2*REGSZ(a0) 60 REG_S s3, SC_REGS+S3*REGSZ(a0) 61 REG_S s4, SC_REGS+S4*REGSZ(a0) 62 REG_S s5, SC_REGS+S5*REGSZ(a0) 63 REG_S s6, SC_REGS+S6*REGSZ(a0) 64 REG_S s7, SC_REGS+S7*REGSZ(a0) 65 REG_S s8, SC_REGS+S8*REGSZ(a0) 66 REG_L v0, GPOFF(sp) 67 REG_S v0, SC_REGS+GP*REGSZ(a0) 68 PTR_ADDU v0, sp, FRAMESZ 69 REG_S v0, SC_REGS+SP*REGSZ(a0) 70 REG_S ra, SC_PC(a0) 71 cfc1 v0, $31 72#if _MIPS_FPSET == 32 73 sdc1 $f20, SC_FPREGS+((F20-F0)*REGSZ)(a0) 74 sdc1 $f21, SC_FPREGS+((F21-F0)*REGSZ)(a0) 75 sdc1 $f22, SC_FPREGS+((F22-F0)*REGSZ)(a0) 76 sdc1 $f23, SC_FPREGS+((F23-F0)*REGSZ)(a0) 77 sdc1 $f24, SC_FPREGS+((F24-F0)*REGSZ)(a0) 78 sdc1 $f25, SC_FPREGS+((F25-F0)*REGSZ)(a0) 79 sdc1 $f26, SC_FPREGS+((F26-F0)*REGSZ)(a0) 80 sdc1 $f27, SC_FPREGS+((F27-F0)*REGSZ)(a0) 81 sdc1 $f28, SC_FPREGS+((F28-F0)*REGSZ)(a0) 82 sdc1 $f29, SC_FPREGS+((F29-F0)*REGSZ)(a0) 83 sdc1 $f30, SC_FPREGS+((F30-F0)*REGSZ)(a0) 84 sdc1 $f31, SC_FPREGS+((F31-F0)*REGSZ)(a0) 85#else 86 swc1 $f20, SC_FPREGS+((F20-F0)*REGSZ)(a0) 87 swc1 $f21, SC_FPREGS+((F21-F0)*REGSZ)(a0) 88 swc1 $f22, SC_FPREGS+((F22-F0)*REGSZ)(a0) 89 swc1 $f23, SC_FPREGS+((F23-F0)*REGSZ)(a0) 90 swc1 $f24, SC_FPREGS+((F24-F0)*REGSZ)(a0) 91 swc1 $f25, SC_FPREGS+((F25-F0)*REGSZ)(a0) 92 swc1 $f26, SC_FPREGS+((F26-F0)*REGSZ)(a0) 93 swc1 $f27, SC_FPREGS+((F27-F0)*REGSZ)(a0) 94 swc1 $f28, SC_FPREGS+((F28-F0)*REGSZ)(a0) 95 swc1 $f29, SC_FPREGS+((F29-F0)*REGSZ)(a0) 96 swc1 $f30, SC_FPREGS+((F30-F0)*REGSZ)(a0) 97 swc1 $f31, SC_FPREGS+((F31-F0)*REGSZ)(a0) 98#endif 99 REG_S v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0) 100 RESTORE_GP64 101 PTR_ADDU sp, FRAMESZ 102 j ra 103 move v0, zero 104END(_setjmp) 105 106LEAF(_longjmp, FRAMESZ) 107 PTR_SUBU sp, FRAMESZ 108 SETUP_GP64(GPOFF, _longjmp) 109 .set noreorder 110 REG_L v0, SC_REGS+ZERO*REGSZ(a0) 111 bne v0, 0xACEDBADE, botch # jump if error 112 REG_L ra, SC_PC(a0) 113 REG_L v0, SC_FPREGS+((FSR-F0)*REGSZ)(a0) 114 REG_L s0, SC_REGS+S0*REGSZ(a0) 115 REG_L s1, SC_REGS+S1*REGSZ(a0) 116 REG_L s2, SC_REGS+S2*REGSZ(a0) 117 REG_L s3, SC_REGS+S3*REGSZ(a0) 118 REG_L s4, SC_REGS+S4*REGSZ(a0) 119 REG_L s5, SC_REGS+S5*REGSZ(a0) 120 REG_L s6, SC_REGS+S6*REGSZ(a0) 121 REG_L s7, SC_REGS+S7*REGSZ(a0) 122 REG_L s8, SC_REGS+S8*REGSZ(a0) 123 REG_L gp, SC_REGS+GP*REGSZ(a0) 124 REG_L sp, SC_REGS+SP*REGSZ(a0) 125 ctc1 v0, $31 126#if _MIPS_FPSET == 32 127 ldc1 $f20, SC_FPREGS+((F20-F0)*REGSZ)(a0) 128 ldc1 $f21, SC_FPREGS+((F21-F0)*REGSZ)(a0) 129 ldc1 $f22, SC_FPREGS+((F22-F0)*REGSZ)(a0) 130 ldc1 $f23, SC_FPREGS+((F23-F0)*REGSZ)(a0) 131 ldc1 $f24, SC_FPREGS+((F24-F0)*REGSZ)(a0) 132 ldc1 $f25, SC_FPREGS+((F25-F0)*REGSZ)(a0) 133 ldc1 $f26, SC_FPREGS+((F26-F0)*REGSZ)(a0) 134 ldc1 $f27, SC_FPREGS+((F27-F0)*REGSZ)(a0) 135 ldc1 $f28, SC_FPREGS+((F28-F0)*REGSZ)(a0) 136 ldc1 $f29, SC_FPREGS+((F29-F0)*REGSZ)(a0) 137 ldc1 $f30, SC_FPREGS+((F30-F0)*REGSZ)(a0) 138 ldc1 $f31, SC_FPREGS+((F31-F0)*REGSZ)(a0) 139#else 140 lwc1 $f20, SC_FPREGS+((F20-F0)*REGSZ)(a0) 141 lwc1 $f21, SC_FPREGS+((F21-F0)*REGSZ)(a0) 142 lwc1 $f22, SC_FPREGS+((F22-F0)*REGSZ)(a0) 143 lwc1 $f23, SC_FPREGS+((F23-F0)*REGSZ)(a0) 144 lwc1 $f24, SC_FPREGS+((F24-F0)*REGSZ)(a0) 145 lwc1 $f25, SC_FPREGS+((F25-F0)*REGSZ)(a0) 146 lwc1 $f26, SC_FPREGS+((F26-F0)*REGSZ)(a0) 147 lwc1 $f27, SC_FPREGS+((F27-F0)*REGSZ)(a0) 148 lwc1 $f28, SC_FPREGS+((F28-F0)*REGSZ)(a0) 149 lwc1 $f29, SC_FPREGS+((F29-F0)*REGSZ)(a0) 150 lwc1 $f30, SC_FPREGS+((F30-F0)*REGSZ)(a0) 151 lwc1 $f31, SC_FPREGS+((F31-F0)*REGSZ)(a0) 152#endif 153 beql a1, zero, 1f 154 li a1, 1 # only executed if branch taken. 1551: 156 j ra 157 move v0, a1 158 159botch: 160 jal longjmperror 161 nop 162 jal abort 163 nop 164 RESTORE_GP64 165 PTR_ADDU sp, FRAMESZ 166END(_longjmp) 167 168