1 /* $OpenBSD: fpu_emu.h,v 1.1 2003/07/21 18:41:30 jason Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_emu.h 8.1 (Berkeley) 6/11/93 45 * $NetBSD: fpu_emu.h,v 1.4 2000/08/03 18:32:07 eeh Exp $ 46 * $FreeBSD: src/lib/libc/sparc64/fpu/fpu_emu.h,v 1.4 2002/03/22 23:41:59 obrien Exp $ 47 */ 48 49 /* 50 * Floating point emulator (tailored for SPARC, but structurally 51 * machine-independent). 52 * 53 * Floating point numbers are carried around internally in an `expanded' 54 * or `unpacked' form consisting of: 55 * - sign 56 * - unbiased exponent 57 * - mantissa (`1.' + 112-bit fraction + guard + round) 58 * - sticky bit 59 * Any implied `1' bit is inserted, giving a 113-bit mantissa that is 60 * always nonzero. Additional low-order `guard' and `round' bits are 61 * scrunched in, making the entire mantissa 115 bits long. This is divided 62 * into four 32-bit words, with `spare' bits left over in the upper part 63 * of the top word (the high bits of fp_mant[0]). An internal `exploded' 64 * number is thus kept within the half-open interval [1.0,2.0) (but see 65 * the `number classes' below). This holds even for denormalized numbers: 66 * when we explode an external denorm, we normalize it, introducing low-order 67 * zero bits, so that the rest of the code always sees normalized values. 68 * 69 * Note that a number of our algorithms use the `spare' bits at the top. 70 * The most demanding algorithm---the one for sqrt---depends on two such 71 * bits, so that it can represent values up to (but not including) 8.0, 72 * and then it needs a carry on top of that, so that we need three `spares'. 73 * 74 * The sticky-word is 32 bits so that we can use `OR' operators to goosh 75 * whole words from the mantissa into it. 76 * 77 * All operations are done in this internal extended precision. According 78 * to Hennesey & Patterson, Appendix A, rounding can be repeated---that is, 79 * it is OK to do a+b in extended precision and then round the result to 80 * single precision---provided single, double, and extended precisions are 81 * `far enough apart' (they always are), but we will try to avoid any such 82 * extra work where possible. 83 */ 84 85 #ifndef _SPARC64_FPU_FPU_EMU_H_ 86 #define _SPARC64_FPU_FPU_EMU_H_ 87 88 #include "fpu_reg.h" 89 90 struct fpn { 91 int fp_class; /* see below */ 92 int fp_sign; /* 0 => positive, 1 => negative */ 93 int fp_exp; /* exponent (unbiased) */ 94 int fp_sticky; /* nonzero bits lost at right end */ 95 u_int fp_mant[4]; /* 115-bit mantissa */ 96 }; 97 98 #define FP_NMANT 115 /* total bits in mantissa (incl g,r) */ 99 #define FP_NG 2 /* number of low-order guard bits */ 100 #define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */ 101 #define FP_LG2 ((FP_NMANT - 1) & 63) /* log2(1.0) for fp_mant[0] and fp_mant[1] */ 102 #define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */ 103 #define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */ 104 #define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */ 105 106 /* 107 * Number classes. Since zero, Inf, and NaN cannot be represented using 108 * the above layout, we distinguish these from other numbers via a class. 109 * In addition, to make computation easier and to follow Appendix N of 110 * the SPARC Version 8 standard, we give each kind of NaN a separate class. 111 */ 112 #define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */ 113 #define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */ 114 #define FPC_ZERO 0 /* zero (sign matters) */ 115 #define FPC_NUM 1 /* number (sign matters) */ 116 #define FPC_INF 2 /* infinity (sign matters) */ 117 118 #define ISNAN(fp) ((fp)->fp_class < 0) 119 #define ISZERO(fp) ((fp)->fp_class == 0) 120 #define ISINF(fp) ((fp)->fp_class == FPC_INF) 121 122 /* 123 * ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points 124 * to the `more significant' operand for our purposes. Appendix N says that 125 * the result of a computation involving two numbers are: 126 * 127 * If both are SNaN: operand 2, converted to Quiet 128 * If only one is SNaN: the SNaN operand, converted to Quiet 129 * If both are QNaN: operand 2 130 * If only one is QNaN: the QNaN operand 131 * 132 * In addition, in operations with an Inf operand, the result is usually 133 * Inf. The class numbers are carefully arranged so that if 134 * (unsigned)class(op1) > (unsigned)class(op2) 135 * then op1 is the one we want; otherwise op2 is the one we want. 136 */ 137 #define ORDER(x, y) { \ 138 if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \ 139 SWAP(x, y); \ 140 } 141 #define SWAP(x, y) { \ 142 register struct fpn *swap; \ 143 swap = (x), (x) = (y), (y) = swap; \ 144 } 145 146 /* 147 * Emulator state. 148 */ 149 struct fpemu { 150 u_long fe_fsr; /* fsr copy (modified during op) */ 151 int fe_cx; /* exceptions */ 152 struct fpn fe_f1; /* operand 1 */ 153 struct fpn fe_f2; /* operand 2, if required */ 154 struct fpn fe_f3; /* available storage for result */ 155 }; 156 157 /* 158 * Arithmetic functions. 159 * Each of these may modify its inputs (f1,f2) and/or the temporary. 160 * Each returns a pointer to the result and/or sets exceptions. 161 */ 162 #define __fpu_sub(fe) ((fe)->fe_f2.fp_sign ^= 1, __fpu_add(fe)) 163 164 #ifdef FPU_DEBUG 165 #define FPE_INSN 0x1 166 #define FPE_REG 0x2 167 extern int __fpe_debug; 168 void __fpu_dumpfpn(struct fpn *); 169 #define DPRINTF(x, y) if (__fpe_debug & (x)) printf y 170 #define DUMPFPN(x, f) if (__fpe_debug & (x)) __fpu_dumpfpn((f)) 171 #else 172 #define DPRINTF(x, y) 173 #define DUMPFPN(x, f) 174 #endif 175 176 #define FSR_GET_RD(fsr) (((fsr) >> FSR_RD_SHIFT) & FSR_RD_MASK) 177 #endif /* !_SPARC64_FPU_FPU_EXTERN_H_ */ 178