1 /* $OpenBSD: fpu_explode.c,v 1.7 2012/12/05 23:19:59 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93 45 * $NetBSD: fpu_explode.c,v 1.5 2000/08/03 18:32:08 eeh Exp $ 46 */ 47 48 #if 0 49 __FBSDID("$FreeBSD: src/lib/libc/sparc64/fpu/fpu_explode.c,v 1.5 2002/05/11 21:20:04 jake Exp $"); 50 #endif 51 52 /* 53 * FPU subroutines: `explode' the machine's `packed binary' format numbers 54 * into our internal format. 55 */ 56 57 #include <sys/param.h> 58 59 #include <machine/frame.h> 60 #include <machine/fsr.h> 61 #include <machine/ieee.h> 62 #include <machine/instr.h> 63 64 #include "fpu_arith.h" 65 #include "fpu_emu.h" 66 #include "fpu_extern.h" 67 #include "fpu_reg.h" 68 69 /* 70 * N.B.: in all of the following, we assume the FP format is 71 * 72 * --------------------------- 73 * | s | exponent | fraction | 74 * --------------------------- 75 * 76 * (which represents -1**s * 1.fraction * 2**exponent), so that the 77 * sign bit is way at the top (bit 31), the exponent is next, and 78 * then the remaining bits mark the fraction. A zero exponent means 79 * zero or denormalized (0.fraction rather than 1.fraction), and the 80 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN. 81 * 82 * Since the sign bit is always the topmost bit---this holds even for 83 * integers---we set that outside all the *tof functions. Each function 84 * returns the class code for the new number (but note that we use 85 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate). 86 */ 87 88 /* 89 * int -> fpn. 90 */ 91 int 92 __fpu_itof(fp, i) 93 struct fpn *fp; 94 u_int i; 95 { 96 97 if (i == 0) 98 return (FPC_ZERO); 99 /* 100 * The value FP_1 represents 2^FP_LG, so set the exponent 101 * there and let normalization fix it up. Convert negative 102 * numbers to sign-and-magnitude. Note that this relies on 103 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 104 */ 105 fp->fp_exp = FP_LG; 106 fp->fp_mant[0] = (int)i < 0 ? -i : i; 107 fp->fp_mant[1] = 0; 108 fp->fp_mant[2] = 0; 109 fp->fp_mant[3] = 0; 110 __fpu_norm(fp); 111 return (FPC_NUM); 112 } 113 114 /* 115 * uint -> fpn. 116 */ 117 int 118 __fpu_uitof(fp, i) 119 struct fpn *fp; 120 u_int i; 121 { 122 123 if (i == 0) 124 return (FPC_ZERO); 125 /* 126 * The value FP_1 represents 2^FP_LG, so set the exponent 127 * there and let normalization fix it up. 128 * Note that this relies on fpu_norm()'s handling of 129 * `supernormals'; see fpu_subr.c. 130 */ 131 fp->fp_exp = FP_LG; 132 fp->fp_mant[0] = i; 133 fp->fp_mant[1] = 0; 134 fp->fp_mant[2] = 0; 135 fp->fp_mant[3] = 0; 136 __fpu_norm(fp); 137 return (FPC_NUM); 138 } 139 140 /* 141 * 64-bit int -> fpn. 142 */ 143 int 144 __fpu_xtof(fp, i) 145 struct fpn *fp; 146 u_int64_t i; 147 { 148 149 if (i == 0) 150 return (FPC_ZERO); 151 /* 152 * The value FP_1 represents 2^FP_LG, so set the exponent 153 * there and let normalization fix it up. Convert negative 154 * numbers to sign-and-magnitude. Note that this relies on 155 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c. 156 */ 157 fp->fp_exp = FP_LG2; 158 i = ((int64_t)i < 0) ? -i : i; 159 fp->fp_mant[0] = (i >> 32) & 0xffffffff; 160 fp->fp_mant[1] = (i >> 0) & 0xffffffff; 161 fp->fp_mant[2] = 0; 162 fp->fp_mant[3] = 0; 163 __fpu_norm(fp); 164 return (FPC_NUM); 165 } 166 167 /* 168 * 64-bit uint -> fpn. 169 */ 170 int 171 __fpu_uxtof(fp, i) 172 struct fpn *fp; 173 u_int64_t i; 174 { 175 176 if (i == 0) 177 return (FPC_ZERO); 178 /* 179 * The value FP_1 represents 2^FP_LG, so set the exponent 180 * there and let normalization fix it up. 181 * Note that this relies on fpu_norm()'s handling of 182 * `supernormals'; see fpu_subr.c. 183 */ 184 fp->fp_exp = FP_LG2; 185 fp->fp_mant[0] = (i >> 32) & 0xffffffff; 186 fp->fp_mant[1] = (i >> 0) & 0xffffffff; 187 fp->fp_mant[2] = 0; 188 fp->fp_mant[3] = 0; 189 __fpu_norm(fp); 190 return (FPC_NUM); 191 } 192 193 #define mask(nbits) ((1L << (nbits)) - 1) 194 195 /* 196 * All external floating formats convert to internal in the same manner, 197 * as defined here. Note that only normals get an implied 1.0 inserted. 198 */ 199 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \ 200 if (exp == 0) { \ 201 if (allfrac == 0) \ 202 return (FPC_ZERO); \ 203 fp->fp_exp = 1 - expbias; \ 204 fp->fp_mant[0] = f0; \ 205 fp->fp_mant[1] = f1; \ 206 fp->fp_mant[2] = f2; \ 207 fp->fp_mant[3] = f3; \ 208 __fpu_norm(fp); \ 209 return (FPC_NUM); \ 210 } \ 211 if (exp == (2 * expbias + 1)) { \ 212 if (allfrac == 0) \ 213 return (FPC_INF); \ 214 fp->fp_mant[0] = f0; \ 215 fp->fp_mant[1] = f1; \ 216 fp->fp_mant[2] = f2; \ 217 fp->fp_mant[3] = f3; \ 218 return (FPC_QNAN); \ 219 } \ 220 fp->fp_exp = exp - expbias; \ 221 fp->fp_mant[0] = FP_1 | f0; \ 222 fp->fp_mant[1] = f1; \ 223 fp->fp_mant[2] = f2; \ 224 fp->fp_mant[3] = f3; \ 225 return (FPC_NUM) 226 227 /* 228 * 32-bit single precision -> fpn. 229 * We assume a single occupies at most (64-FP_LG) bits in the internal 230 * format: i.e., needs at most fp_mant[0] and fp_mant[1]. 231 */ 232 int 233 __fpu_stof(fp, i) 234 struct fpn *fp; 235 u_int i; 236 { 237 int exp; 238 u_int frac, f0, f1; 239 #define SNG_SHIFT (SNG_FRACBITS - FP_LG) 240 241 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS); 242 frac = i & mask(SNG_FRACBITS); 243 f0 = frac >> SNG_SHIFT; 244 f1 = frac << (32 - SNG_SHIFT); 245 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0); 246 } 247 248 /* 249 * 64-bit double -> fpn. 250 * We assume this uses at most (96-FP_LG) bits. 251 */ 252 int 253 __fpu_dtof(fp, i, j) 254 struct fpn *fp; 255 u_int i, j; 256 { 257 int exp; 258 u_int frac, f0, f1, f2; 259 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG) 260 261 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS); 262 frac = i & mask(DBL_FRACBITS - 32); 263 f0 = frac >> DBL_SHIFT; 264 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT); 265 f2 = j << (32 - DBL_SHIFT); 266 frac |= j; 267 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0); 268 } 269 270 /* 271 * 128-bit extended -> fpn. 272 */ 273 int 274 __fpu_qtof(fp, i, j, k, l) 275 struct fpn *fp; 276 u_int i, j, k, l; 277 { 278 int exp; 279 u_int frac, f0, f1, f2, f3; 280 #define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG)) /* left shift! */ 281 282 /* 283 * Note that ext and fpn `line up', hence no shifting needed. 284 */ 285 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS); 286 frac = i & mask(EXT_FRACBITS - 3 * 32); 287 f0 = (frac << EXT_SHIFT) | (j >> (32 - EXT_SHIFT)); 288 f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT)); 289 f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT)); 290 f3 = l << EXT_SHIFT; 291 frac |= j | k | l; 292 FP_TOF(exp, EXT_EXP_BIAS, frac, f0, f1, f2, f3); 293 } 294 295 /* 296 * Explode the contents of a / regpair / regquad. 297 * If the input is a signalling NaN, an NV (invalid) exception 298 * will be set. (Note that nothing but NV can occur until ALU 299 * operations are performed.) 300 */ 301 void 302 __fpu_explode(fe, fp, type, reg) 303 struct fpemu *fe; 304 struct fpn *fp; 305 int type, reg; 306 { 307 u_int32_t s = 0/* XXX gcc */, *sp; 308 u_int64_t l[2]; 309 310 if (type == FTYPE_LNG || type == FTYPE_DBL || type == FTYPE_EXT) { 311 l[0] = __fpu_getreg64(reg & ~1); 312 sp = (u_int32_t *)l; 313 fp->fp_sign = sp[0] >> 31; 314 fp->fp_sticky = 0; 315 switch (type) { 316 case FTYPE_LNG: 317 s = __fpu_xtof(fp, l[0]); 318 break; 319 case FTYPE_DBL: 320 s = __fpu_dtof(fp, sp[0], sp[1]); 321 break; 322 case FTYPE_EXT: 323 l[1] = __fpu_getreg64((reg & ~1) + 2); 324 s = __fpu_qtof(fp, sp[0], sp[1], sp[2], sp[3]); 325 break; 326 default: 327 #ifdef DIAGNOSTIC 328 __utrap_panic("fpu_explode"); 329 #endif 330 break; 331 } 332 } else { 333 #ifdef DIAGNOSTIC 334 if (type != FTYPE_SNG) 335 __utrap_panic("fpu_explode"); 336 #endif 337 s = __fpu_getreg32(reg); 338 fp->fp_sign = s >> 31; 339 fp->fp_sticky = 0; 340 s = __fpu_stof(fp, s); 341 } 342 343 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) { 344 /* 345 * Input is a signalling NaN. All operations that return 346 * an input NaN operand put it through a ``NaN conversion'', 347 * which basically just means ``turn on the quiet bit''. 348 * We do this here so that all NaNs internally look quiet 349 * (we can tell signalling ones by their class). 350 */ 351 fp->fp_mant[0] |= FP_QUIETBIT; 352 fe->fe_cx = FSR_NV; /* assert invalid operand */ 353 s = FPC_SNAN; 354 } 355 fp->fp_class = s; 356 DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' : 357 ((type == FTYPE_INT) ? 'i' : 358 ((type == FTYPE_SNG) ? 's' : 359 ((type == FTYPE_DBL) ? 'd' : 360 ((type == FTYPE_EXT) ? 'q' : '?')))), 361 reg)); 362 DUMPFPN(FPE_REG, fp); 363 DPRINTF(FPE_REG, ("\n")); 364 } 365