1#	$OpenBSD: Makefile,v 1.2 2003/07/12 04:23:15 jason Exp $
2
3PROG=badfpreg
4NOMAN=
5SRCS=test.S main.c
6
7REGRESS_TARGETS=							\
8	t_ld_f2_imm t_st_f2_imm t_ld_f2_reg t_st_f2_reg			\
9	t_ld_f6_imm t_st_f6_imm t_ld_f6_reg t_st_f6_reg			\
10	t_ld_f10_imm t_st_f10_imm t_ld_f10_reg t_st_f10_reg		\
11	t_ld_f14_imm t_st_f14_imm t_ld_f14_reg t_st_f14_reg		\
12	t_ld_f18_imm t_st_f18_imm t_ld_f18_reg t_st_f18_reg		\
13	t_ld_f22_imm t_st_f22_imm t_ld_f22_reg t_st_f22_reg		\
14	t_ld_f26_imm t_st_f26_imm t_ld_f26_reg t_st_f26_reg		\
15	t_ld_f30_imm t_st_f30_imm t_ld_f30_reg t_st_f30_reg		\
16	t_ld_f34_imm t_st_f34_imm t_ld_f34_reg t_st_f34_reg		\
17	t_ld_f38_imm t_st_f38_imm t_ld_f38_reg t_st_f38_reg		\
18	t_ld_f42_imm t_st_f42_imm t_ld_f42_reg t_st_f42_reg		\
19	t_ld_f46_imm t_st_f46_imm t_ld_f46_reg t_st_f46_reg		\
20	t_ld_f50_imm t_st_f50_imm t_ld_f50_reg t_st_f50_reg		\
21	t_ld_f54_imm t_st_f54_imm t_ld_f54_reg t_st_f54_reg		\
22	t_ld_f58_imm t_st_f58_imm t_ld_f58_reg t_st_f58_reg		\
23	t_ld_f62_imm t_st_f62_imm t_ld_f62_reg t_st_f62_reg
24
25.include <bsd.regress.mk>
26
27t_ld_f2_imm: ${PROG}
28	${.OBJDIR}/${PROG} 2 ld imm
29
30t_st_f2_imm: ${PROG}
31	${.OBJDIR}/${PROG} 2 st imm
32
33t_ld_f2_reg: ${PROG}
34	${.OBJDIR}/${PROG} 2 ld reg
35
36t_st_f2_reg: ${PROG}
37	${.OBJDIR}/${PROG} 2 st reg
38
39t_ld_f6_imm: ${PROG}
40	${.OBJDIR}/${PROG} 6 ld imm
41
42t_st_f6_imm: ${PROG}
43	${.OBJDIR}/${PROG} 6 st imm
44
45t_ld_f6_reg: ${PROG}
46	${.OBJDIR}/${PROG} 6 ld reg
47
48t_st_f6_reg: ${PROG}
49	${.OBJDIR}/${PROG} 6 st reg
50
51t_ld_f10_imm: ${PROG}
52	${.OBJDIR}/${PROG} 10 ld imm
53
54t_st_f10_imm: ${PROG}
55	${.OBJDIR}/${PROG} 10 st imm
56
57t_ld_f10_reg: ${PROG}
58	${.OBJDIR}/${PROG} 10 ld reg
59
60t_st_f10_reg: ${PROG}
61	${.OBJDIR}/${PROG} 10 st reg
62
63t_ld_f14_imm: ${PROG}
64	${.OBJDIR}/${PROG} 14 ld imm
65
66t_st_f14_imm: ${PROG}
67	${.OBJDIR}/${PROG} 14 st imm
68
69t_ld_f14_reg: ${PROG}
70	${.OBJDIR}/${PROG} 14 ld reg
71
72t_st_f14_reg: ${PROG}
73	${.OBJDIR}/${PROG} 14 st reg
74
75t_ld_f18_imm: ${PROG}
76	${.OBJDIR}/${PROG} 18 ld imm
77
78t_st_f18_imm: ${PROG}
79	${.OBJDIR}/${PROG} 18 st imm
80
81t_ld_f18_reg: ${PROG}
82	${.OBJDIR}/${PROG} 18 ld reg
83
84t_st_f18_reg: ${PROG}
85	${.OBJDIR}/${PROG} 18 st reg
86
87t_ld_f22_imm: ${PROG}
88	${.OBJDIR}/${PROG} 22 ld imm
89
90t_st_f22_imm: ${PROG}
91	${.OBJDIR}/${PROG} 22 st imm
92
93t_ld_f22_reg: ${PROG}
94	${.OBJDIR}/${PROG} 22 ld reg
95
96t_st_f22_reg: ${PROG}
97	${.OBJDIR}/${PROG} 22 st reg
98
99t_ld_f26_imm: ${PROG}
100	${.OBJDIR}/${PROG} 26 ld imm
101
102t_st_f26_imm: ${PROG}
103	${.OBJDIR}/${PROG} 26 st imm
104
105t_ld_f26_reg: ${PROG}
106	${.OBJDIR}/${PROG} 26 ld reg
107
108t_st_f26_reg: ${PROG}
109	${.OBJDIR}/${PROG} 26 st reg
110
111t_ld_f30_imm: ${PROG}
112	${.OBJDIR}/${PROG} 30 ld imm
113
114t_st_f30_imm: ${PROG}
115	${.OBJDIR}/${PROG} 30 st imm
116
117t_ld_f30_reg: ${PROG}
118	${.OBJDIR}/${PROG} 30 ld reg
119
120t_st_f30_reg: ${PROG}
121	${.OBJDIR}/${PROG} 30 st reg
122
123t_ld_f34_imm: ${PROG}
124	${.OBJDIR}/${PROG} 34 ld imm
125
126t_st_f34_imm: ${PROG}
127	${.OBJDIR}/${PROG} 34 st imm
128
129t_ld_f34_reg: ${PROG}
130	${.OBJDIR}/${PROG} 34 ld reg
131
132t_st_f34_reg: ${PROG}
133	${.OBJDIR}/${PROG} 34 st reg
134
135t_ld_f38_imm: ${PROG}
136	${.OBJDIR}/${PROG} 38 ld imm
137
138t_st_f38_imm: ${PROG}
139	${.OBJDIR}/${PROG} 38 st imm
140
141t_ld_f38_reg: ${PROG}
142	${.OBJDIR}/${PROG} 38 ld reg
143
144t_st_f38_reg: ${PROG}
145	${.OBJDIR}/${PROG} 38 st reg
146
147t_ld_f42_imm: ${PROG}
148	${.OBJDIR}/${PROG} 42 ld imm
149
150t_st_f42_imm: ${PROG}
151	${.OBJDIR}/${PROG} 42 st imm
152
153t_ld_f42_reg: ${PROG}
154	${.OBJDIR}/${PROG} 42 ld reg
155
156t_st_f42_reg: ${PROG}
157	${.OBJDIR}/${PROG} 42 st reg
158
159t_ld_f46_imm: ${PROG}
160	${.OBJDIR}/${PROG} 46 ld imm
161
162t_st_f46_imm: ${PROG}
163	${.OBJDIR}/${PROG} 46 st imm
164
165t_ld_f46_reg: ${PROG}
166	${.OBJDIR}/${PROG} 46 ld reg
167
168t_st_f46_reg: ${PROG}
169	${.OBJDIR}/${PROG} 46 st reg
170
171t_ld_f50_imm: ${PROG}
172	${.OBJDIR}/${PROG} 50 ld imm
173
174t_st_f50_imm: ${PROG}
175	${.OBJDIR}/${PROG} 50 st imm
176
177t_ld_f50_reg: ${PROG}
178	${.OBJDIR}/${PROG} 50 ld reg
179
180t_st_f50_reg: ${PROG}
181	${.OBJDIR}/${PROG} 50 st reg
182
183t_ld_f54_imm: ${PROG}
184	${.OBJDIR}/${PROG} 54 ld imm
185
186t_st_f54_imm: ${PROG}
187	${.OBJDIR}/${PROG} 54 st imm
188
189t_ld_f54_reg: ${PROG}
190	${.OBJDIR}/${PROG} 54 ld reg
191
192t_st_f54_reg: ${PROG}
193	${.OBJDIR}/${PROG} 54 st reg
194
195t_ld_f58_imm: ${PROG}
196	${.OBJDIR}/${PROG} 58 ld imm
197
198t_st_f58_imm: ${PROG}
199	${.OBJDIR}/${PROG} 58 st imm
200
201t_ld_f58_reg: ${PROG}
202	${.OBJDIR}/${PROG} 58 ld reg
203
204t_st_f58_reg: ${PROG}
205	${.OBJDIR}/${PROG} 58 st reg
206
207t_ld_f62_imm: ${PROG}
208	${.OBJDIR}/${PROG} 62 ld imm
209
210t_st_f62_imm: ${PROG}
211	${.OBJDIR}/${PROG} 62 st imm
212
213t_ld_f62_reg: ${PROG}
214	${.OBJDIR}/${PROG} 62 ld reg
215
216t_st_f62_reg: ${PROG}
217	${.OBJDIR}/${PROG} 62 st reg
218
219