1 /* $OpenBSD: alpha_cpu.h,v 1.10 2011/03/23 16:54:33 pirofti Exp $ */ 2 /* $NetBSD: alpha_cpu.h,v 1.43 2001/12/18 04:18:22 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1996 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Author: Chris G. Demetriou 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #ifndef _MACHINE_ALPHA_CPU_H_ 32 #define _MACHINE_ALPHA_CPU_H_ 33 34 /* 35 * Alpha CPU + OSF/1 PALcode definitions for use by the kernel. 36 * 37 * Definitions for: 38 * 39 * Process Control Block 40 * Interrupt/Exception/Syscall Stack Frame 41 * Processor Status Register 42 * Machine Check Error Summary Register 43 * Machine Check Logout Area 44 * Per CPU state Management of Machine Check Handling 45 * Virtual Memory Management 46 * Kernel Entry Vectors 47 * MMCSR Fault Type Codes 48 * Translation Buffer Invalidation 49 * 50 * and miscellaneous PALcode operations. 51 */ 52 53 54 /* 55 * Process Control Block definitions [OSF/1 PALcode Specific] 56 */ 57 58 struct alpha_pcb { 59 unsigned long apcb_ksp; /* kernel stack ptr */ 60 unsigned long apcb_usp; /* user stack ptr */ 61 unsigned long apcb_ptbr; /* page table base reg */ 62 unsigned int apcb_cpc; /* charged process cycles */ 63 unsigned int apcb_asn; /* address space number */ 64 unsigned long apcb_unique; /* process unique value */ 65 #define apcb_backup_ksp apcb_unique /* backup kernel stack ptr */ 66 unsigned long apcb_flags; /* flags; see below */ 67 unsigned long apcb_decrsv0; /* DEC reserved */ 68 unsigned long apcb_decrsv1; /* DEC reserved */ 69 }; 70 71 #define ALPHA_PCB_FLAGS_FEN 0x0000000000000001 72 #define ALPHA_PCB_FLAGS_PME 0x4000000000000000 73 74 /* 75 * Interrupt/Exception/Syscall "Hardware" (really PALcode) 76 * Stack Frame definitions 77 * 78 * These are quadword offsets from the sp on kernel entry, i.e. 79 * to get to the value in question you access (sp + (offset * 8)). 80 * 81 * On syscall entry, A0-A2 aren't written to memory but space 82 * _is_ reserved for them. 83 */ 84 85 #define ALPHA_HWFRAME_PS 0 /* processor status register */ 86 #define ALPHA_HWFRAME_PC 1 /* program counter */ 87 #define ALPHA_HWFRAME_GP 2 /* global pointer */ 88 #define ALPHA_HWFRAME_A0 3 /* a0 */ 89 #define ALPHA_HWFRAME_A1 4 /* a1 */ 90 #define ALPHA_HWFRAME_A2 5 /* a2 */ 91 92 #define ALPHA_HWFRAME_SIZE 6 /* 6 8-byte words */ 93 94 /* 95 * Processor Status Register [OSF/1 PALcode Specific] 96 * 97 * Includes user/kernel mode bit, interrupt priority levels, etc. 98 */ 99 100 #define ALPHA_PSL_USERMODE 0x0008 /* set -> user mode */ 101 #define ALPHA_PSL_IPL_MASK 0x0007 /* interrupt level mask */ 102 103 #define ALPHA_PSL_IPL_0 0x0000 /* all interrupts enabled */ 104 #define ALPHA_PSL_IPL_SOFT 0x0001 /* software ints disabled */ 105 #define ALPHA_PSL_IPL_IO 0x0004 /* I/O dev ints disabled */ 106 #define ALPHA_PSL_IPL_CLOCK 0x0005 /* clock ints disabled */ 107 #define ALPHA_PSL_IPL_HIGH 0x0006 /* all but mchecks disabled */ 108 109 #define ALPHA_PSL_MUST_BE_ZERO 0xfffffffffffffff0 110 111 /* Convenience constants: what must be set/clear in user mode */ 112 #define ALPHA_PSL_USERSET ALPHA_PSL_USERMODE 113 #define ALPHA_PSL_USERCLR (ALPHA_PSL_MUST_BE_ZERO | ALPHA_PSL_IPL_MASK) 114 115 /* 116 * Interrupt Type Code Definitions [OSF/1 PALcode Specific] 117 */ 118 119 #define ALPHA_INTR_XPROC 0 /* interprocessor interrupt */ 120 #define ALPHA_INTR_CLOCK 1 /* clock interrupt */ 121 #define ALPHA_INTR_ERROR 2 /* correctable error or mcheck */ 122 #define ALPHA_INTR_DEVICE 3 /* device interrupt */ 123 #define ALPHA_INTR_PERF 4 /* performance counter */ 124 #define ALPHA_INTR_PASSIVE 5 /* passive release */ 125 126 /* 127 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific] 128 * 129 * The following bits are values as read. On write, _PCE, _SCE, and 130 * _MIP are "write 1 to clear." 131 */ 132 133 #define ALPHA_MCES_IMP \ 134 0xffffffff00000000 /* impl. dependent */ 135 #define ALPHA_MCES_RSVD \ 136 0x00000000ffffffe0 /* reserved */ 137 #define ALPHA_MCES_DSC \ 138 0x0000000000000010 /* disable system correctable error reporting */ 139 #define ALPHA_MCES_DPC \ 140 0x0000000000000008 /* disable processor correctable error reporting */ 141 #define ALPHA_MCES_PCE \ 142 0x0000000000000004 /* processor correctable error in progress */ 143 #define ALPHA_MCES_SCE \ 144 0x0000000000000002 /* system correctable error in progress */ 145 #define ALPHA_MCES_MIP \ 146 0x0000000000000001 /* machine check in progress */ 147 148 /* 149 * Machine Check Error Summary Register definitions [OSF/1 PALcode Specific] 150 * 151 * Note that these are *generic* OSF/1 PALcode specific defines. There are 152 * platform variations to these entities. 153 */ 154 155 struct alpha_logout_area { 156 unsigned int la_frame_size; /* frame size */ 157 unsigned int la_flags; /* flags; see below */ 158 unsigned int la_cpu_offset; /* offset to cpu area */ 159 unsigned int la_system_offset; /* offset to system area */ 160 }; 161 162 #define ALPHA_LOGOUT_FLAGS_RETRY 0x80000000 /* OK to continue */ 163 #define ALPHA_LOGOUT_FLAGS_SE 0x40000000 /* second error */ 164 #define ALPHA_LOGOUT_FLAGS_SBZ 0x3fffffff /* should be zero */ 165 166 #define ALPHA_LOGOUT_NOT_BUILT \ 167 (struct alpha_logout_area *)0xffffffffffffffff) 168 169 #define ALPHA_LOGOUT_PAL_AREA(lap) \ 170 (unsigned long *)((unsigned char *)(lap) + 16) 171 #define ALPHA_LOGOUT_PAL_SIZE(lap) \ 172 ((lap)->la_cpu_offset - 16) 173 #define ALPHA_LOGOUT_CPU_AREA(lap) \ 174 (unsigned long *)((unsigned char *)(lap) + (lap)->la_cpu_offset) 175 #define ALPHA_LOGOUT_CPU_SIZE(lap) \ 176 ((lap)->la_system_offset - (lap)->la_cpu_offset) 177 #define ALPHA_LOGOUT_SYSTEM_AREA(lap) \ 178 (unsigned long *)((unsigned char *)(lap) + (lap)->la_system_offset) 179 #define ALPHA_LOGOUT_SYSTEM_SIZE(lap) \ 180 ((lap)->la_frame_size - (lap)->la_system_offset) 181 182 /* types of machine checks */ 183 #define ALPHA_SYS_ERROR 0x620 /* System correctable error */ 184 #define ALPHA_PROC_ERROR 0x630 /* Processor correctable error */ 185 #define ALPHA_SYS_MCHECK 0x660 /* System machine check */ 186 #define ALPHA_PROC_MCHECK 0x670 /* Processor machine check */ 187 #define ALPHA_ENV_MCHECK 0x680 /* Environmental machine check */ 188 189 /* 190 * Virtual Memory Management definitions [OSF/1 PALcode Specific] 191 * 192 * Includes user and kernel space addresses and information, 193 * page table entry definitions, etc. 194 * 195 * NOTE THAT THESE DEFINITIONS MAY CHANGE IN FUTURE ALPHA CPUS! 196 */ 197 198 #define ALPHA_PGSHIFT 13 199 #define ALPHA_PGBYTES (1 << ALPHA_PGSHIFT) 200 201 #define ALPHA_USEG_BASE 0 /* virtual */ 202 #define ALPHA_USEG_END 0x000003ffffffffff 203 204 #define ALPHA_K0SEG_BASE 0xfffffc0000000000 /* direct-mapped */ 205 #define ALPHA_K0SEG_END 0xfffffdffffffffff 206 #define ALPHA_K1SEG_BASE 0xfffffe0000000000 /* virtual */ 207 #define ALPHA_K1SEG_END 0xffffffffffffffff 208 209 #define ALPHA_K0SEG_TO_PHYS(x) ((x) & ~ALPHA_K0SEG_BASE) 210 #define ALPHA_PHYS_TO_K0SEG(x) ((x) | ALPHA_K0SEG_BASE) 211 212 #define ALPHA_PTE_VALID 0x0001UL 213 214 #define ALPHA_PTE_FAULT_ON_READ 0x0002UL 215 #define ALPHA_PTE_FAULT_ON_WRITE 0x0004UL 216 #define ALPHA_PTE_FAULT_ON_EXECUTE 0x0008UL 217 218 #define ALPHA_PTE_ASM 0x0010UL /* addr. space match */ 219 #define ALPHA_PTE_GRANULARITY 0x0060UL /* granularity hint */ 220 221 #define ALPHA_PTE_PROT 0xff00UL 222 #define ALPHA_PTE_KR 0x0100UL 223 #define ALPHA_PTE_UR 0x0200UL 224 #define ALPHA_PTE_KW 0x1000UL 225 #define ALPHA_PTE_UW 0x2000UL 226 227 #define ALPHA_PTE_WRITE (ALPHA_PTE_KW | ALPHA_PTE_UW) 228 229 #define ALPHA_PTE_SOFTWARE 0x00000000ffff0000UL 230 #define ALPHA_PTE_PALCODE (~ALPHA_PTE_SOFTWARE) /* shorthand */ 231 232 #define ALPHA_PTE_PFN 0xffffffff00000000UL 233 234 #define ALPHA_PTE_TO_PFN(pte) ((pte) >> 32) 235 #define ALPHA_PTE_FROM_PFN(pfn) ((pfn) << 32) 236 237 typedef unsigned long alpha_pt_entry_t; 238 239 /* 240 * Kernel Entry Vectors. [OSF/1 PALcode Specific] 241 */ 242 243 #define ALPHA_KENTRY_INT 0 244 #define ALPHA_KENTRY_ARITH 1 245 #define ALPHA_KENTRY_MM 2 246 #define ALPHA_KENTRY_IF 3 247 #define ALPHA_KENTRY_UNA 4 248 #define ALPHA_KENTRY_SYS 5 249 250 /* 251 * MMCSR Fault Type Codes. [OSF/1 PALcode Specific] 252 */ 253 254 #define ALPHA_MMCSR_INVALTRANS 0 255 #define ALPHA_MMCSR_ACCESS 1 256 #define ALPHA_MMCSR_FOR 2 257 #define ALPHA_MMCSR_FOE 3 258 #define ALPHA_MMCSR_FOW 4 259 260 /* 261 * Instruction Fault Type Codes. [OSF/1 PALcode Specific] 262 */ 263 264 #define ALPHA_IF_CODE_BPT 0 265 #define ALPHA_IF_CODE_BUGCHK 1 266 #define ALPHA_IF_CODE_GENTRAP 2 267 #define ALPHA_IF_CODE_FEN 3 268 #define ALPHA_IF_CODE_OPDEC 4 269 270 #ifdef _KERNEL 271 272 /* 273 * Translation Buffer Invalidation definitions [OSF/1 PALcode Specific] 274 */ 275 276 #define ALPHA_TBIA() alpha_pal_tbi(-2, 0) /* all TB entries */ 277 #define ALPHA_TBIAP() alpha_pal_tbi(-1, 0) /* all per-process */ 278 #define ALPHA_TBISI(va) alpha_pal_tbi(1, (va)) /* ITB entry for va */ 279 #define ALPHA_TBISD(va) alpha_pal_tbi(2, (va)) /* DTB entry for va */ 280 #define ALPHA_TBIS(va) alpha_pal_tbi(3, (va)) /* all for va */ 281 282 #endif /* _KERNEL */ 283 284 /* 285 * Bits used in the amask instruction [EV56 and later] 286 */ 287 288 #define ALPHA_AMASK_BWX 0x0001 /* byte/word extension */ 289 #define ALPHA_AMASK_FIX 0x0002 /* floating point conv. ext. */ 290 #define ALPHA_AMASK_CIX 0x0004 /* count extension */ 291 #define ALPHA_AMASK_MVI 0x0100 /* multimedia extension */ 292 #define ALPHA_AMASK_PAT 0x0200 /* precise arith. traps */ 293 294 #define ALPHA_AMASK_ALL (ALPHA_AMASK_BWX|ALPHA_AMASK_FIX| \ 295 ALPHA_AMASK_CIX|ALPHA_AMASK_MVI| \ 296 ALPHA_AMASK_PAT) 297 298 #define ALPHA_AMASK_BITS \ 299 "\20\12PAT\11MVI\3CIX\2FIX\1BWX" 300 301 /* 302 * Chip family IDs returned by implver instruction 303 */ 304 305 #define ALPHA_IMPLVER_EV4 0 /* LCA/EV4/EV45 */ 306 #define ALPHA_IMPLVER_EV5 1 /* EV5/EV56/PCA56 */ 307 #define ALPHA_IMPLVER_EV6 2 /* EV6 */ 308 309 #ifdef _KERNEL 310 311 /* 312 * Maximum processor ID we allow from `whami', and related constants. 313 * 314 * XXX This is not really processor or PALcode specific, but this is 315 * a convenient place to put these definitions. 316 * 317 * XXX This is clipped at 63 so that we can use `long's for proc bitmasks. 318 */ 319 320 #define ALPHA_WHAMI_MAXID 63 321 #define ALPHA_MAXPROCS (ALPHA_WHAMI_MAXID + 1) 322 323 /* 324 * Misc. support routines. 325 */ 326 const char *alpha_dsr_sysname(void); 327 328 /* 329 * Stubs for Alpha instructions normally inaccessible from C. 330 */ 331 unsigned long alpha_amask(unsigned long); 332 unsigned long alpha_implver(void); 333 334 #endif /* _KERNEL */ 335 336 /* XXX Expose the insn wrappers to userspace, for now. */ 337 338 static __inline unsigned long 339 alpha_rpcc(void) 340 { 341 unsigned long v0; 342 343 __asm __volatile("rpcc %0" : "=r" (v0)); 344 return (v0); 345 } 346 347 #define alpha_mb() __asm __volatile("mb" : : : "memory") 348 #define alpha_wmb() __asm __volatile("mb" : : : "memory") /* XXX */ 349 350 #if defined(_KERNEL) || defined(_STANDALONE) 351 352 /* 353 * Stubs for OSF/1 PALcode operations. 354 */ 355 #include <machine/pal.h> 356 357 void alpha_pal_cflush(unsigned long); 358 void alpha_pal_halt(void) __attribute__((__noreturn__)); 359 unsigned long _alpha_pal_swpipl(unsigned long); /* for profiling */ 360 void alpha_pal_wrent(void *, unsigned long); 361 void alpha_pal_wrvptptr(unsigned long); 362 363 #define alpha_pal_draina() __asm __volatile("call_pal %0 # PAL_draina" \ 364 : : "i" (PAL_draina) : "memory") 365 366 #define alpha_pal_imb() __asm __volatile("call_pal %0 # PAL_imb" \ 367 : : "i" (PAL_imb) : "memory") 368 369 static __inline unsigned long 370 alpha_pal_rdmces(void) 371 { 372 register unsigned long v0 __asm("$0"); 373 374 __asm __volatile("call_pal %1 # PAL_OSF1_rdmces" 375 : "=r" (v0) 376 : "i" (PAL_OSF1_rdmces) 377 /* clobbers t0, t8..t11 */ 378 : "$1", "$22", "$23", "$24", "$25"); 379 380 return (v0); 381 } 382 383 static __inline unsigned long 384 alpha_pal_rdps(void) 385 { 386 register unsigned long v0 __asm("$0"); 387 388 __asm __volatile("call_pal %1 # PAL_OSF1_rdps" 389 : "=r" (v0) 390 : "i" (PAL_OSF1_rdps) 391 /* clobbers t0, t8..t11 */ 392 : "$1", "$22", "$23", "$24", "$25"); 393 394 return (v0); 395 } 396 397 static __inline unsigned long 398 alpha_pal_rdusp(void) 399 { 400 register unsigned long v0 __asm("$0"); 401 402 __asm __volatile("call_pal %1 # PAL_OSF1_rdusp" 403 : "=r" (v0) 404 : "i" (PAL_OSF1_rdusp) 405 /* clobbers t0, t8..t11 */ 406 : "$1", "$22", "$23", "$24", "$25"); 407 408 return (v0); 409 } 410 411 static __inline unsigned long 412 alpha_pal_rdval(void) 413 { 414 register unsigned long v0 __asm("$0"); 415 416 __asm __volatile("call_pal %1 # PAL_OSF1_rdval" 417 : "=r" (v0) 418 : "i" (PAL_OSF1_rdval) 419 /* clobbers t0, t8..t11 */ 420 : "$1", "$22", "$23", "$24", "$25"); 421 422 return (v0); 423 } 424 425 static __inline unsigned long 426 alpha_pal_swpctx(unsigned long ctx) 427 { 428 register unsigned long a0 __asm("$16") = ctx; 429 register unsigned long v0 __asm("$0"); 430 431 __asm __volatile("call_pal %2 # PAL_OSF1_swpctx" 432 : "=r" (a0), "=r" (v0) 433 : "i" (PAL_OSF1_swpctx), "0" (a0) 434 /* clobbers t0, t8..t11, a0 (above) */ 435 : "$1", "$22", "$23", "$24", "$25", "memory"); 436 437 return (v0); 438 } 439 440 static __inline unsigned long 441 alpha_pal_swpipl(unsigned long ipl) 442 { 443 register unsigned long a0 __asm("$16") = ipl; 444 register unsigned long v0 __asm("$0"); 445 446 __asm __volatile("call_pal %2 # PAL_OSF1_swpipl" 447 : "=r" (a0), "=r" (v0) 448 : "i" (PAL_OSF1_swpipl), "0" (a0) 449 /* clobbers t0, t8..t11, a0 (above) */ 450 : "$1", "$22", "$23", "$24", "$25", "memory"); 451 452 return (v0); 453 } 454 455 static __inline void 456 alpha_pal_tbi(unsigned long op, vaddr_t va) 457 { 458 register unsigned long a0 __asm("$16") = op; 459 register unsigned long a1 __asm("$17") = va; 460 461 __asm __volatile("call_pal %2 # PAL_OSF1_tbi" 462 : "=r" (a0), "=r" (a1) 463 : "i" (PAL_OSF1_tbi), "0" (a0), "1" (a1) 464 /* clobbers t0, t8..t11, a0 (above), a1 (above) */ 465 : "$1", "$22", "$23", "$24", "$25"); 466 } 467 468 static __inline unsigned long 469 alpha_pal_whami(void) 470 { 471 register unsigned long v0 __asm("$0"); 472 473 __asm __volatile("call_pal %1 # PAL_OSF1_whami" 474 : "=r" (v0) 475 : "i" (PAL_OSF1_whami) 476 /* clobbers t0, t8..t11 */ 477 : "$1", "$22", "$23", "$24", "$25"); 478 479 return (v0); 480 } 481 482 static __inline void 483 alpha_pal_wrfen(unsigned long onoff) 484 { 485 register unsigned long a0 __asm("$16") = onoff; 486 487 __asm __volatile("call_pal %1 # PAL_OSF1_wrfen" 488 : "=r" (a0) 489 : "i" (PAL_OSF1_wrfen), "0" (a0) 490 /* clobbers t0, t8..t11, a0 (above) */ 491 : "$1", "$22", "$23", "$24", "$25"); 492 } 493 494 static __inline void 495 alpha_pal_wripir(unsigned long cpu_id) 496 { 497 register unsigned long a0 __asm("$16") = cpu_id; 498 499 __asm __volatile("call_pal %1 # PAL_ipir" 500 : "=r" (a0) 501 : "i" (PAL_ipir), "0" (a0) 502 /* clobbers t0, t8..t11, a0 (above) */ 503 : "$1", "$22", "$23", "$24", "$25"); 504 } 505 506 static __inline void 507 alpha_pal_wrusp(unsigned long usp) 508 { 509 register unsigned long a0 __asm("$16") = usp; 510 511 __asm __volatile("call_pal %1 # PAL_OSF1_wrusp" 512 : "=r" (a0) 513 : "i" (PAL_OSF1_wrusp), "0" (a0) 514 /* clobbers t0, t8..t11, a0 (above) */ 515 : "$1", "$22", "$23", "$24", "$25"); 516 } 517 518 static __inline void 519 alpha_pal_wrmces(unsigned long mces) 520 { 521 register unsigned long a0 __asm("$16") = mces; 522 523 __asm __volatile("call_pal %1 # PAL_OSF1_wrmces" 524 : "=r" (a0) 525 : "i" (PAL_OSF1_wrmces), "0" (a0) 526 /* clobbers t0, t8..t11 */ 527 : "$1", "$22", "$23", "$24", "$25"); 528 } 529 530 static __inline void 531 alpha_pal_wrval(unsigned long val) 532 { 533 register unsigned long a0 __asm("$16") = val; 534 535 __asm __volatile("call_pal %1 # PAL_OSF1_wrval" 536 : "=r" (a0) 537 : "i" (PAL_OSF1_wrval), "0" (a0) 538 /* clobbers t0, t8..t11, a0 (above) */ 539 : "$1", "$22", "$23", "$24", "$25"); 540 } 541 542 #endif /* _KERNEL */ 543 544 #endif /* _MACHINE_ALPHA_CPU_H_ */ 545