1 /* $OpenBSD: pci_2100_a50.c,v 1.23 2015/07/26 05:09:44 miod Exp $ */ 2 /* $NetBSD: pci_2100_a50.c,v 1.12 1996/11/13 21:13:29 cgd Exp $ */ 3 4 /* 5 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Author: Chris G. Demetriou 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #include <sys/types.h> 32 #include <sys/param.h> 33 #include <sys/time.h> 34 #include <sys/systm.h> 35 #include <sys/errno.h> 36 #include <sys/device.h> 37 #include <uvm/uvm_extern.h> 38 39 #include <machine/autoconf.h> 40 #include <machine/bus.h> 41 #include <machine/intr.h> 42 43 #include <dev/isa/isavar.h> 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/ppbreg.h> 47 48 #include <alpha/pci/apecsvar.h> 49 50 #include <alpha/pci/pci_2100_a50.h> 51 #include <alpha/pci/siovar.h> 52 #include <alpha/pci/sioreg.h> 53 54 #include "sio.h" 55 56 int dec_2100_a50_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 57 const char *dec_2100_a50_intr_string(void *, pci_intr_handle_t); 58 int dec_2100_a50_intr_line(void *, pci_intr_handle_t); 59 void *dec_2100_a50_intr_establish(void *, pci_intr_handle_t, 60 int, int (*func)(void *), void *, const char *); 61 void dec_2100_a50_intr_disestablish(void *, void *); 62 63 #define APECS_SIO_DEVICE 7 /* XXX */ 64 65 void 66 pci_2100_a50_pickintr(acp) 67 struct apecs_config *acp; 68 { 69 bus_space_tag_t iot = &acp->ac_iot; 70 pci_chipset_tag_t pc = &acp->ac_pc; 71 pcireg_t sioclass; 72 int sioII; 73 74 /* XXX MAGIC NUMBER */ 75 sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, 7, 0), PCI_CLASS_REG); 76 sioII = (sioclass & 0xff) >= 3; 77 78 if (!sioII) 79 printf("WARNING: SIO NOT SIO II... NO BETS...\n"); 80 81 pc->pc_intr_v = acp; 82 pc->pc_intr_map = dec_2100_a50_intr_map; 83 pc->pc_intr_string = dec_2100_a50_intr_string; 84 pc->pc_intr_line = dec_2100_a50_intr_line; 85 pc->pc_intr_establish = dec_2100_a50_intr_establish; 86 pc->pc_intr_disestablish = dec_2100_a50_intr_disestablish; 87 88 /* Not supported on 2100 A50. */ 89 pc->pc_pciide_compat_intr_establish = NULL; 90 pc->pc_pciide_compat_intr_disestablish = NULL; 91 92 #if NSIO 93 sio_intr_setup(pc, iot); 94 #else 95 panic("pci_2100_a50_pickintr: no I/O interrupt handler (no sio)"); 96 #endif 97 } 98 99 int 100 dec_2100_a50_intr_map(pa, ihp) 101 struct pci_attach_args *pa; 102 pci_intr_handle_t *ihp; 103 { 104 pcitag_t bustag = pa->pa_intrtag; 105 pci_chipset_tag_t pc = pa->pa_pc; 106 int buspin, device, pirq; 107 pcireg_t pirqreg; 108 u_int8_t pirqline; 109 110 if (pa->pa_bridgetag) { 111 buspin = PPB_INTERRUPT_SWIZZLE(pa->pa_rawintrpin, 112 pa->pa_device); 113 if (pa->pa_bridgeih[buspin - 1] != 0) { 114 *ihp = pa->pa_bridgeih[buspin - 1]; 115 return 0; 116 } 117 118 return 1; 119 } 120 121 buspin = pa->pa_intrpin; 122 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 123 124 switch (device) { 125 case 6: /* NCR SCSI */ 126 pirq = 3; 127 break; 128 129 case 11: /* slot 1 */ 130 case 14: /* slot 3 */ 131 switch (buspin) { 132 default: 133 case PCI_INTERRUPT_PIN_A: 134 case PCI_INTERRUPT_PIN_D: 135 pirq = 0; 136 break; 137 case PCI_INTERRUPT_PIN_B: 138 pirq = 2; 139 break; 140 case PCI_INTERRUPT_PIN_C: 141 pirq = 1; 142 break; 143 }; 144 break; 145 146 case 12: /* slot 2 */ 147 switch (buspin) { 148 default: 149 case PCI_INTERRUPT_PIN_A: 150 case PCI_INTERRUPT_PIN_D: 151 pirq = 1; 152 break; 153 case PCI_INTERRUPT_PIN_B: 154 pirq = 0; 155 break; 156 case PCI_INTERRUPT_PIN_C: 157 pirq = 2; 158 break; 159 }; 160 break; 161 162 case 13: /* slot 3 */ 163 switch (buspin) { 164 default: 165 case PCI_INTERRUPT_PIN_A: 166 case PCI_INTERRUPT_PIN_D: 167 pirq = 2; 168 break; 169 case PCI_INTERRUPT_PIN_B: 170 pirq = 1; 171 break; 172 case PCI_INTERRUPT_PIN_C: 173 pirq = 0; 174 break; 175 }; 176 break; 177 178 default: 179 printf("dec_2100_a50_intr_map: don't know how to setup %d/%d/%d\n", 180 pa->pa_bus, pa->pa_device, pa->pa_function); 181 return 1; 182 } 183 184 pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, APECS_SIO_DEVICE, 0), 185 SIO_PCIREG_PIRQ_RTCTRL); 186 pirqline = (pirqreg >> (pirq * 8)) & 0xff; 187 if ((pirqline & 0x80) != 0) 188 return 1; 189 pirqline &= 0xf; 190 191 *ihp = pirqline; 192 return 0; 193 } 194 195 const char * 196 dec_2100_a50_intr_string(acv, ih) 197 void *acv; 198 pci_intr_handle_t ih; 199 { 200 return sio_intr_string(NULL /*XXX*/, ih); 201 } 202 203 int 204 dec_2100_a50_intr_line(acv, ih) 205 void *acv; 206 pci_intr_handle_t ih; 207 { 208 return sio_intr_line(NULL /*XXX*/, ih); 209 } 210 211 void * 212 dec_2100_a50_intr_establish(acv, ih, level, func, arg, name) 213 void *acv, *arg; 214 pci_intr_handle_t ih; 215 int level; 216 int (*func)(void *); 217 const char *name; 218 { 219 return sio_intr_establish(NULL /*XXX*/, ih, IST_LEVEL, level, func, 220 arg, name); 221 } 222 223 void 224 dec_2100_a50_intr_disestablish(acv, cookie) 225 void *acv, *cookie; 226 { 227 sio_intr_disestablish(NULL /*XXX*/, cookie); 228 } 229