1 /* $OpenBSD: pci_550.c,v 1.22 2010/08/07 03:50:01 krw Exp $ */ 2 /* $NetBSD: pci_550.c,v 1.18 2000/06/29 08:58:48 mrg Exp $ */ 3 4 /*- 5 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center, and by Andrew Gallatin. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 36 * All rights reserved. 37 * 38 * Author: Chris G. Demetriou 39 * 40 * Permission to use, copy, modify and distribute this software and 41 * its documentation is hereby granted, provided that both the copyright 42 * notice and this permission notice appear in all copies of the 43 * software, derivative works or modified versions, and any portions 44 * thereof, and that both notices appear in supporting documentation. 45 * 46 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 47 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 48 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 49 * 50 * Carnegie Mellon requests users of this software to return to 51 * 52 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 53 * School of Computer Science 54 * Carnegie Mellon University 55 * Pittsburgh PA 15213-3890 56 * 57 * any improvements or extensions that they make and grant Carnegie the 58 * rights to redistribute these changes. 59 */ 60 61 #include <sys/types.h> 62 #include <sys/param.h> 63 #include <sys/time.h> 64 #include <sys/systm.h> 65 #include <sys/errno.h> 66 #include <sys/malloc.h> 67 #include <sys/device.h> 68 #include <sys/syslog.h> 69 70 #include <uvm/uvm_extern.h> 71 72 #include <machine/autoconf.h> 73 #include <machine/rpb.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pciidereg.h> 78 #include <dev/pci/pciidevar.h> 79 80 #include <alpha/pci/ciareg.h> 81 #include <alpha/pci/ciavar.h> 82 83 #include <alpha/pci/pci_550.h> 84 85 #include "sio.h" 86 #if NSIO 87 #include <alpha/pci/siovar.h> 88 #endif 89 90 int dec_550_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 91 const char *dec_550_intr_string(void *, pci_intr_handle_t); 92 int dec_550_intr_line(void *, pci_intr_handle_t); 93 void *dec_550_intr_establish(void *, pci_intr_handle_t, 94 int, int (*func)(void *), void *, const char *); 95 void dec_550_intr_disestablish(void *, void *); 96 97 void *dec_550_pciide_compat_intr_establish(void *, struct device *, 98 struct pci_attach_args *, int, int (*)(void *), void *); 99 void dec_550_pciide_compat_intr_disestablish(void *, void *); 100 101 #define DEC_550_PCI_IRQ_BEGIN 8 102 #define DEC_550_MAX_IRQ (64 - DEC_550_PCI_IRQ_BEGIN) 103 104 /* 105 * The Miata has a Pyxis, which seems to have problems with stray 106 * interrupts. Work around this by just ignoring strays. 107 */ 108 #define PCI_STRAY_MAX 0 109 110 /* 111 * Some Miata models, notably models with a Cypress PCI-ISA bridge, have 112 * a PCI device (the OHCI USB controller) with interrupts tied to ISA IRQ 113 * lines. This IRQ is encoded as: line = FLAG | isa_irq. Usually FLAG 114 * is 0xe0, however it can be 0xf0. We don't allow 0xf0 | irq15. 115 */ 116 #define DEC_550_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xfe) 117 #define DEC_550_LINE_ISA_IRQ(line) ((line) & 0x0f) 118 119 struct alpha_shared_intr *dec_550_pci_intr; 120 121 void dec_550_iointr(void *arg, unsigned long vec); 122 void dec_550_intr_enable(int irq); 123 void dec_550_intr_disable(int irq); 124 125 void 126 pci_550_pickintr(ccp) 127 struct cia_config *ccp; 128 { 129 bus_space_tag_t iot = &ccp->cc_iot; 130 pci_chipset_tag_t pc = &ccp->cc_pc; 131 #if 0 132 char *cp; 133 #endif 134 int i; 135 136 pc->pc_intr_v = ccp; 137 pc->pc_intr_map = dec_550_intr_map; 138 pc->pc_intr_string = dec_550_intr_string; 139 pc->pc_intr_line = dec_550_intr_line; 140 pc->pc_intr_establish = dec_550_intr_establish; 141 pc->pc_intr_disestablish = dec_550_intr_disestablish; 142 143 pc->pc_pciide_compat_intr_establish = 144 dec_550_pciide_compat_intr_establish; 145 pc->pc_pciide_compat_intr_disestablish = 146 dec_550_pciide_compat_intr_disestablish; 147 148 /* 149 * DEC 550's interrupts are enabled via the Pyxis interrupt 150 * mask register. Nothing to map. 151 */ 152 153 for (i = 0; i < DEC_550_MAX_IRQ; i++) 154 dec_550_intr_disable(i); 155 156 dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ); 157 for (i = 0; i < DEC_550_MAX_IRQ; i++) { 158 alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i, 159 PCI_STRAY_MAX); 160 alpha_shared_intr_set_private(dec_550_pci_intr, i, ccp); 161 } 162 163 #if NSIO 164 sio_intr_setup(pc, iot); 165 #endif 166 } 167 168 int 169 dec_550_intr_map(pa, ihp) 170 struct pci_attach_args *pa; 171 pci_intr_handle_t *ihp; 172 { 173 pcitag_t bustag = pa->pa_intrtag; 174 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 175 pci_chipset_tag_t pc = pa->pa_pc; 176 int bus, device, function; 177 178 if (buspin == 0) { 179 /* No IRQ used. */ 180 return 1; 181 } 182 if (buspin > 4) { 183 printf("dec_550_intr_map: bad interrupt pin %d\n", buspin); 184 return 1; 185 } 186 187 pci_decompose_tag(pc, bustag, &bus, &device, &function); 188 189 /* 190 * There are two main variants of Miata: Miata 1 (Intel SIO) 191 * and Miata {1.5,2} (Cypress). 192 * 193 * The Miata 1 has a CMD PCI IDE wired to compatibility mode at 194 * device 4 of bus 0. This variant apparently also has the 195 * Pyxis DMA bug. 196 * 197 * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives 198 * on device 7 of bus 0. This device has PCI IDE wired to 199 * compatibility mode on functions 1 and 2. 200 * 201 * There will be no interrupt mapping for these devices, so just 202 * bail out now. 203 */ 204 if (bus == 0) { 205 if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 206 /* Miata 1 */ 207 if (device == 7) 208 panic("dec_550_intr_map: SIO device"); 209 else if (device == 4) 210 return (1); 211 } else { 212 /* Miata 1.5 or Miata 2 */ 213 if (device == 7) { 214 if (function == 0) 215 panic("dec_550_intr_map: SIO device"); 216 if (function == 1 || function == 2) 217 return (1); 218 } 219 } 220 } 221 222 /* 223 * The console places the interrupt mapping in the "line" value. 224 * A value of (char)-1 indicates there is no mapping. 225 */ 226 if (line == 0xff) { 227 printf("dec_550_intr_map: no mapping for %d/%d/%d\n", 228 bus, device, function); 229 return (1); 230 } 231 232 #if NSIO == 0 233 if (DEC_550_LINE_IS_ISA(line)) { 234 printf("dec_550_intr_map: ISA IRQ %d for %d/%d/%d\n", 235 DEC_550_LINE_ISA_IRQ(line), bus, device, function); 236 return (1); 237 } 238 #endif 239 240 if (DEC_550_LINE_IS_ISA(line) == 0 && line >= DEC_550_MAX_IRQ) { 241 printf("dec_550_intr_map: dec 550 irq too large (%d)", 242 line); 243 return (1); 244 } 245 246 *ihp = line; 247 return (0); 248 } 249 250 const char * 251 dec_550_intr_string(ccv, ih) 252 void *ccv; 253 pci_intr_handle_t ih; 254 { 255 #if 0 256 struct cia_config *ccp = ccv; 257 #endif 258 static char irqstr[16]; /* 12 + 2 + NULL + sanity */ 259 260 #if NSIO 261 if (DEC_550_LINE_IS_ISA(ih)) 262 return (sio_intr_string(NULL /*XXX*/, 263 DEC_550_LINE_ISA_IRQ(ih))); 264 #endif 265 266 if (ih >= DEC_550_MAX_IRQ) 267 panic("dec_550_intr_string: bogus 550 IRQ 0x%lx", ih); 268 snprintf(irqstr, sizeof irqstr, "dec 550 irq %ld", ih); 269 return (irqstr); 270 } 271 272 int 273 dec_550_intr_line(ccv, ih) 274 void *ccv; 275 pci_intr_handle_t ih; 276 { 277 #if NSIO 278 if (DEC_550_LINE_IS_ISA(ih)) 279 return (sio_intr_line(NULL /*XXX*/, DEC_550_LINE_ISA_IRQ(ih))); 280 #endif 281 282 return (ih); 283 } 284 285 void * 286 dec_550_intr_establish(ccv, ih, level, func, arg, name) 287 void *ccv, *arg; 288 pci_intr_handle_t ih; 289 int level; 290 int (*func)(void *); 291 const char *name; 292 { 293 #if 0 294 struct cia_config *ccp = ccv; 295 #endif 296 void *cookie; 297 298 #if NSIO 299 if (DEC_550_LINE_IS_ISA(ih)) 300 return (sio_intr_establish(NULL /*XXX*/, 301 DEC_550_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg, 302 name)); 303 #endif 304 305 if (ih >= DEC_550_MAX_IRQ) 306 panic("dec_550_intr_establish: bogus dec 550 IRQ 0x%lx", ih); 307 308 cookie = alpha_shared_intr_establish(dec_550_pci_intr, ih, IST_LEVEL, 309 level, func, arg, name); 310 311 if (cookie != NULL && 312 alpha_shared_intr_firstactive(dec_550_pci_intr, ih)) { 313 scb_set(0x900 + SCB_IDXTOVEC(ih), dec_550_iointr, NULL); 314 dec_550_intr_enable(ih); 315 } 316 return (cookie); 317 } 318 319 void 320 dec_550_intr_disestablish(ccv, cookie) 321 void *ccv, *cookie; 322 { 323 struct cia_config *ccp = ccv; 324 struct alpha_shared_intrhand *ih = cookie; 325 unsigned int irq = ih->ih_num; 326 int s; 327 328 #if NSIO 329 /* 330 * We have to determine if this is an ISA IRQ or not! We do this 331 * by checking to see if the intrhand points back to an intrhead 332 * that points to our cia_config. If not, it's an ISA IRQ. Pretty 333 * disgusting, eh? 334 */ 335 if (ih->ih_intrhead->intr_private != ccp) { 336 sio_intr_disestablish(NULL /*XXX*/, cookie); 337 return; 338 } 339 #endif 340 341 s = splhigh(); 342 343 alpha_shared_intr_disestablish(dec_550_pci_intr, cookie); 344 if (alpha_shared_intr_isactive(dec_550_pci_intr, irq) == 0) { 345 dec_550_intr_disable(irq); 346 alpha_shared_intr_set_dfltsharetype(dec_550_pci_intr, irq, 347 IST_NONE); 348 scb_free(0x900 + SCB_IDXTOVEC(irq)); 349 } 350 351 splx(s); 352 } 353 354 void * 355 dec_550_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 356 void *v; 357 struct device *dev; 358 struct pci_attach_args *pa; 359 int chan; 360 int (*func)(void *); 361 void *arg; 362 { 363 pci_chipset_tag_t pc = pa->pa_pc; 364 void *cookie = NULL; 365 int bus, irq; 366 367 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 368 369 /* 370 * If this isn't PCI bus #0, all bets are off. 371 */ 372 if (bus != 0) 373 return (NULL); 374 375 irq = PCIIDE_COMPAT_IRQ(chan); 376 #if NSIO 377 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 378 func, arg, dev->dv_xname); 379 #endif 380 return (cookie); 381 } 382 383 void 384 dec_550_pciide_compat_intr_disestablish(v, cookie) 385 void *v; 386 void *cookie; 387 { 388 sio_intr_disestablish(NULL, cookie); 389 } 390 391 void 392 dec_550_iointr(arg, vec) 393 void *arg; 394 unsigned long vec; 395 { 396 int irq; 397 398 irq = SCB_VECTOIDX(vec - 0x900); 399 400 if (irq >= DEC_550_MAX_IRQ) 401 panic("550_iointr: vec 0x%lx out of range", vec); 402 403 if (!alpha_shared_intr_dispatch(dec_550_pci_intr, irq)) { 404 alpha_shared_intr_stray(dec_550_pci_intr, irq, 405 "dec 550 irq"); 406 if (ALPHA_SHARED_INTR_DISABLE(dec_550_pci_intr, irq)) 407 dec_550_intr_disable(irq); 408 } else 409 alpha_shared_intr_reset_strays(dec_550_pci_intr, irq); 410 } 411 412 void 413 dec_550_intr_enable(irq) 414 int irq; 415 { 416 417 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 1); 418 } 419 420 void 421 dec_550_intr_disable(irq) 422 int irq; 423 { 424 425 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 0); 426 } 427