1 /* $OpenBSD: pci_axppci_33.c,v 1.22 2017/09/08 05:36:51 deraadt Exp $ */ 2 /* $NetBSD: pci_axppci_33.c,v 1.10 1996/11/13 21:13:29 cgd Exp $ */ 3 4 /* 5 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Authors: Jeffrey Hsu and Chris G. Demetriou 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/time.h> 33 #include <sys/systm.h> 34 #include <sys/errno.h> 35 #include <sys/device.h> 36 #include <uvm/uvm_extern.h> 37 38 #include <machine/autoconf.h> 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #include <dev/isa/isavar.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/ppbreg.h> 46 47 #include <alpha/pci/lcavar.h> 48 49 #include <alpha/pci/pci_axppci_33.h> 50 #include <alpha/pci/siovar.h> 51 #include <alpha/pci/sioreg.h> 52 53 #include "sio.h" 54 55 int dec_axppci_33_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 56 const char *dec_axppci_33_intr_string(void *, pci_intr_handle_t); 57 int dec_axppci_33_intr_line(void *, pci_intr_handle_t); 58 void *dec_axppci_33_intr_establish(void *, pci_intr_handle_t, 59 int, int (*func)(void *), void *, const char *); 60 void dec_axppci_33_intr_disestablish(void *, void *); 61 62 #define LCA_SIO_DEVICE 7 /* XXX */ 63 64 void 65 pci_axppci_33_pickintr(lcp) 66 struct lca_config *lcp; 67 { 68 bus_space_tag_t iot = &lcp->lc_iot; 69 pci_chipset_tag_t pc = &lcp->lc_pc; 70 pcireg_t sioclass; 71 int sioII; 72 73 /* XXX MAGIC NUMBER */ 74 sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, LCA_SIO_DEVICE, 0), 75 PCI_CLASS_REG); 76 sioII = (sioclass & 0xff) >= 3; 77 78 if (!sioII) 79 printf("WARNING: SIO NOT SIO II... NO BETS...\n"); 80 81 pc->pc_intr_v = lcp; 82 pc->pc_intr_map = dec_axppci_33_intr_map; 83 pc->pc_intr_string = dec_axppci_33_intr_string; 84 pc->pc_intr_line = dec_axppci_33_intr_line; 85 pc->pc_intr_establish = dec_axppci_33_intr_establish; 86 pc->pc_intr_disestablish = dec_axppci_33_intr_disestablish; 87 88 /* Not supported on AXPpci33. */ 89 pc->pc_pciide_compat_intr_establish = NULL; 90 pc->pc_pciide_compat_intr_disestablish = NULL; 91 92 #if NSIO > 0 93 sio_intr_setup(pc, iot); 94 #else 95 panic("pci_axppci_33_pickintr: no I/O interrupt handler (no sio)"); 96 #endif 97 } 98 99 int 100 dec_axppci_33_intr_map(pa, ihp) 101 struct pci_attach_args *pa; 102 pci_intr_handle_t *ihp; 103 { 104 pcitag_t bustag = pa->pa_intrtag; 105 pci_chipset_tag_t pc = pa->pa_pc; 106 int buspin, device, pirq; 107 pcireg_t pirqreg; 108 u_int8_t pirqline; 109 110 if (pa->pa_bridgetag) { 111 buspin = PPB_INTERRUPT_SWIZZLE(pa->pa_rawintrpin, 112 pa->pa_device); 113 if (pa->pa_bridgeih[buspin - 1] != 0) { 114 *ihp = pa->pa_bridgeih[buspin - 1]; 115 return 0; 116 } 117 118 return 1; 119 } 120 121 buspin = pa->pa_intrpin; 122 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 123 124 switch (device) { 125 case 6: /* NCR SCSI */ 126 pirq = 3; 127 break; 128 129 case 11: /* slot 1 */ 130 switch (buspin) { 131 default: 132 case PCI_INTERRUPT_PIN_A: 133 case PCI_INTERRUPT_PIN_D: 134 pirq = 0; 135 break; 136 case PCI_INTERRUPT_PIN_B: 137 pirq = 2; 138 break; 139 case PCI_INTERRUPT_PIN_C: 140 pirq = 1; 141 break; 142 }; 143 break; 144 145 case 12: /* slot 2 */ 146 switch (buspin) { 147 default: 148 case PCI_INTERRUPT_PIN_A: 149 case PCI_INTERRUPT_PIN_D: 150 pirq = 1; 151 break; 152 case PCI_INTERRUPT_PIN_B: 153 pirq = 0; 154 break; 155 case PCI_INTERRUPT_PIN_C: 156 pirq = 2; 157 break; 158 }; 159 break; 160 161 case 8: /* slot 3 */ 162 switch (buspin) { 163 default: 164 case PCI_INTERRUPT_PIN_A: 165 case PCI_INTERRUPT_PIN_D: 166 pirq = 2; 167 break; 168 case PCI_INTERRUPT_PIN_B: 169 pirq = 1; 170 break; 171 case PCI_INTERRUPT_PIN_C: 172 pirq = 0; 173 break; 174 }; 175 break; 176 177 default: 178 return 1; 179 } 180 181 pirqreg = pci_conf_read(pc, pci_make_tag(pc, 0, LCA_SIO_DEVICE, 0), 182 SIO_PCIREG_PIRQ_RTCTRL); 183 184 pirqline = (pirqreg >> (pirq * 8)) & 0xff; 185 if ((pirqline & 0x80) != 0) 186 return 1; /* not routed? */ 187 pirqline &= 0xf; 188 189 *ihp = pirqline; 190 return (0); 191 } 192 193 const char * 194 dec_axppci_33_intr_string(lcv, ih) 195 void *lcv; 196 pci_intr_handle_t ih; 197 { 198 return sio_intr_string(NULL /*XXX*/, ih); 199 } 200 201 int 202 dec_axppci_33_intr_line(lcv, ih) 203 void *lcv; 204 pci_intr_handle_t ih; 205 { 206 return sio_intr_line(NULL /*XXX*/, ih); 207 } 208 209 void * 210 dec_axppci_33_intr_establish(lcv, ih, level, func, arg, name) 211 void *lcv, *arg; 212 pci_intr_handle_t ih; 213 int level; 214 int (*func)(void *); 215 const char *name; 216 { 217 return sio_intr_establish(NULL /*XXX*/, ih, IST_LEVEL, level, func, 218 arg, name); 219 } 220 221 void 222 dec_axppci_33_intr_disestablish(lcv, cookie) 223 void *lcv, *cookie; 224 { 225 sio_intr_disestablish(NULL /*XXX*/, cookie); 226 } 227