1 /* $OpenBSD: pci_eb164.c,v 1.25 2009/09/30 20:18:06 miod Exp $ */ 2 /* $NetBSD: pci_eb164.c,v 1.27 2000/06/06 00:50:15 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 36 * All rights reserved. 37 * 38 * Author: Chris G. Demetriou 39 * 40 * Permission to use, copy, modify and distribute this software and 41 * its documentation is hereby granted, provided that both the copyright 42 * notice and this permission notice appear in all copies of the 43 * software, derivative works or modified versions, and any portions 44 * thereof, and that both notices appear in supporting documentation. 45 * 46 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 47 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 48 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 49 * 50 * Carnegie Mellon requests users of this software to return to 51 * 52 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 53 * School of Computer Science 54 * Carnegie Mellon University 55 * Pittsburgh PA 15213-3890 56 * 57 * any improvements or extensions that they make and grant Carnegie the 58 * rights to redistribute these changes. 59 */ 60 61 #include <sys/types.h> 62 #include <sys/param.h> 63 #include <sys/time.h> 64 #include <sys/systm.h> 65 #include <sys/errno.h> 66 #include <sys/malloc.h> 67 #include <sys/device.h> 68 #include <sys/syslog.h> 69 70 #include <uvm/uvm.h> 71 72 #include <machine/autoconf.h> 73 #include <machine/rpb.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pciidereg.h> 78 #include <dev/pci/pciidevar.h> 79 80 #include <alpha/pci/ciareg.h> 81 #include <alpha/pci/ciavar.h> 82 83 #include <alpha/pci/pci_eb164.h> 84 85 #include "sio.h" 86 #if NSIO 87 #include <alpha/pci/siovar.h> 88 #endif 89 90 int dec_eb164_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 91 const char *dec_eb164_intr_string(void *, pci_intr_handle_t); 92 int dec_eb164_intr_line(void *, pci_intr_handle_t); 93 void *dec_eb164_intr_establish(void *, pci_intr_handle_t, 94 int, int (*func)(void *), void *, const char *); 95 void dec_eb164_intr_disestablish(void *, void *); 96 97 void *dec_eb164_pciide_compat_intr_establish(void *, struct device *, 98 struct pci_attach_args *, int, int (*)(void *), void *); 99 void dec_eb164_pciide_compat_intr_disestablish(void *, void *); 100 101 #define EB164_SIO_IRQ 4 102 #define EB164_MAX_IRQ 24 103 #define PCI_STRAY_MAX 5 104 105 struct alpha_shared_intr *eb164_pci_intr; 106 107 bus_space_tag_t eb164_intrgate_iot; 108 bus_space_handle_t eb164_intrgate_ioh; 109 110 void eb164_iointr(void *arg, unsigned long vec); 111 extern void eb164_intr_enable(int irq); /* pci_eb164_intr.S */ 112 extern void eb164_intr_disable(int irq); /* pci_eb164_intr.S */ 113 114 void 115 pci_eb164_pickintr(ccp) 116 struct cia_config *ccp; 117 { 118 bus_space_tag_t iot = &ccp->cc_iot; 119 pci_chipset_tag_t pc = &ccp->cc_pc; 120 int i; 121 122 pc->pc_intr_v = ccp; 123 pc->pc_intr_map = dec_eb164_intr_map; 124 pc->pc_intr_string = dec_eb164_intr_string; 125 pc->pc_intr_line = dec_eb164_intr_line; 126 pc->pc_intr_establish = dec_eb164_intr_establish; 127 pc->pc_intr_disestablish = dec_eb164_intr_disestablish; 128 129 pc->pc_pciide_compat_intr_establish = 130 dec_eb164_pciide_compat_intr_establish; 131 pc->pc_pciide_compat_intr_disestablish = 132 dec_eb164_pciide_compat_intr_disestablish; 133 134 eb164_intrgate_iot = iot; 135 if (bus_space_map(eb164_intrgate_iot, 0x804, 3, 0, 136 &eb164_intrgate_ioh) != 0) 137 panic("pci_eb164_pickintr: couldn't map interrupt PLD"); 138 for (i = 0; i < EB164_MAX_IRQ; i++) 139 eb164_intr_disable(i); 140 141 eb164_pci_intr = alpha_shared_intr_alloc(EB164_MAX_IRQ); 142 for (i = 0; i < EB164_MAX_IRQ; i++) { 143 /* 144 * Systems with a Pyxis seem to have problems with 145 * stray interrupts, so just ignore them. Sigh, 146 * I hate buggy hardware. 147 */ 148 alpha_shared_intr_set_maxstrays(eb164_pci_intr, i, 149 (ccp->cc_flags & CCF_ISPYXIS) ? 0 : PCI_STRAY_MAX); 150 } 151 152 #if NSIO 153 sio_intr_setup(pc, iot); 154 eb164_intr_enable(EB164_SIO_IRQ); 155 #endif 156 } 157 158 int 159 dec_eb164_intr_map(pa, ihp) 160 struct pci_attach_args *pa; 161 pci_intr_handle_t *ihp; 162 { 163 pcitag_t bustag = pa->pa_intrtag; 164 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 165 pci_chipset_tag_t pc = pa->pa_pc; 166 int bus, device, function; 167 u_int64_t variation; 168 169 if (buspin == 0) { 170 /* No IRQ used. */ 171 return 1; 172 } 173 if (buspin > 4) { 174 printf("dec_eb164_intr_map: bad interrupt pin %d\n", buspin); 175 return 1; 176 } 177 178 pci_decompose_tag(pc, bustag, &bus, &device, &function); 179 180 variation = hwrpb->rpb_variation & SV_ST_MASK; 181 182 /* 183 * 184 * The AlphaPC 164 and AlphaPC 164LX have a CMD PCI IDE controller 185 * at bus 0 device 11. These are wired to compatibility mode, 186 * so do not map their interrupts. 187 * 188 * The AlphaPC 164SX has PCI IDE on functions 1 and 2 of the 189 * Cypress PCI-ISA bridge at bus 0 device 8. These, too, are 190 * wired to compatibility mode. 191 * 192 * Real EB164s have ISA IDE on the Super I/O chip. 193 */ 194 if (bus == 0) { 195 if (variation >= SV_ST_ALPHAPC164_366 && 196 variation <= SV_ST_ALPHAPC164LX_600) { 197 if (device == 8) 198 panic("dec_eb164_intr_map: SIO device"); 199 if (device == 11) 200 return (1); 201 } else if (variation >= SV_ST_ALPHAPC164SX_400 && 202 variation <= SV_ST_ALPHAPC164SX_600) { 203 if (device == 8) { 204 if (function == 0) 205 panic("dec_eb164_intr_map: SIO device"); 206 return (1); 207 } 208 } else { 209 if (device == 8) 210 panic("dec_eb164_intr_map: SIO device"); 211 } 212 } 213 214 /* 215 * The console places the interrupt mapping in the "line" value. 216 * A value of (char)-1 indicates there is no mapping. 217 */ 218 if (line == 0xff) { 219 printf("dec_eb164_intr_map: no mapping for %d/%d/%d\n", 220 bus, device, function); 221 return (1); 222 } 223 224 if (line > EB164_MAX_IRQ) 225 panic("dec_eb164_intr_map: eb164 irq too large (%d)", 226 line); 227 228 *ihp = line; 229 return (0); 230 } 231 232 const char * 233 dec_eb164_intr_string(ccv, ih) 234 void *ccv; 235 pci_intr_handle_t ih; 236 { 237 #if 0 238 struct cia_config *ccp = ccv; 239 #endif 240 static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 241 242 if (ih >= EB164_MAX_IRQ) 243 panic("dec_eb164_intr_string: bogus eb164 IRQ 0x%lx", ih); 244 snprintf(irqstr, sizeof irqstr, "eb164 irq %ld", ih); 245 return (irqstr); 246 } 247 248 int 249 dec_eb164_intr_line(ccv, ih) 250 void *ccv; 251 pci_intr_handle_t ih; 252 { 253 return (ih); 254 } 255 256 void * 257 dec_eb164_intr_establish(ccv, ih, level, func, arg, name) 258 void *ccv, *arg; 259 pci_intr_handle_t ih; 260 int level; 261 int (*func)(void *); 262 const char *name; 263 { 264 #if 0 265 struct cia_config *ccp = ccv; 266 #endif 267 void *cookie; 268 269 if (ih >= EB164_MAX_IRQ) 270 panic("dec_eb164_intr_establish: bogus eb164 IRQ 0x%lx", ih); 271 272 cookie = alpha_shared_intr_establish(eb164_pci_intr, ih, IST_LEVEL, 273 level, func, arg, name); 274 275 if (cookie != NULL && 276 alpha_shared_intr_firstactive(eb164_pci_intr, ih)) { 277 scb_set(0x900 + SCB_IDXTOVEC(ih), eb164_iointr, NULL); 278 eb164_intr_enable(ih); 279 } 280 return (cookie); 281 } 282 283 void 284 dec_eb164_intr_disestablish(ccv, cookie) 285 void *ccv, *cookie; 286 { 287 #if 0 288 struct cia_config *ccp = ccv; 289 #endif 290 struct alpha_shared_intrhand *ih = cookie; 291 unsigned int irq = ih->ih_num; 292 int s; 293 294 s = splhigh(); 295 296 alpha_shared_intr_disestablish(eb164_pci_intr, cookie); 297 if (alpha_shared_intr_isactive(eb164_pci_intr, irq) == 0) { 298 eb164_intr_disable(irq); 299 alpha_shared_intr_set_dfltsharetype(eb164_pci_intr, irq, 300 IST_NONE); 301 scb_free(0x900 + SCB_IDXTOVEC(irq)); 302 } 303 304 splx(s); 305 } 306 307 void * 308 dec_eb164_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 309 void *v; 310 struct device *dev; 311 struct pci_attach_args *pa; 312 int chan; 313 int (*func)(void *); 314 void *arg; 315 { 316 pci_chipset_tag_t pc = pa->pa_pc; 317 void *cookie = NULL; 318 int bus, irq; 319 320 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 321 322 /* 323 * If this isn't PCI bus #0, all bets are off. 324 */ 325 if (bus != 0) 326 return (NULL); 327 328 irq = PCIIDE_COMPAT_IRQ(chan); 329 #if NSIO 330 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 331 func, arg, dev->dv_xname); 332 if (cookie == NULL) 333 return (NULL); 334 #endif 335 return (cookie); 336 } 337 338 void 339 dec_eb164_pciide_compat_intr_disestablish(void *v, void *cookie) 340 { 341 sio_intr_disestablish(NULL, cookie); 342 } 343 344 void 345 eb164_iointr(arg, vec) 346 void *arg; 347 unsigned long vec; 348 { 349 int irq; 350 351 irq = SCB_VECTOIDX(vec - 0x900); 352 353 if (!alpha_shared_intr_dispatch(eb164_pci_intr, irq)) { 354 alpha_shared_intr_stray(eb164_pci_intr, irq, 355 "eb164 irq"); 356 if (ALPHA_SHARED_INTR_DISABLE(eb164_pci_intr, irq)) 357 eb164_intr_disable(irq); 358 } else 359 alpha_shared_intr_reset_strays(eb164_pci_intr, irq); 360 } 361 362 #if 0 /* THIS DOES NOT WORK! see pci_eb164_intr.S. */ 363 u_int8_t eb164_intr_mask[3] = { 0xff, 0xff, 0xff }; 364 365 void 366 eb164_intr_enable(irq) 367 int irq; 368 { 369 int byte = (irq / 8), bit = (irq % 8); 370 371 #if 1 372 printf("eb164_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 373 #endif 374 eb164_intr_mask[byte] &= ~(1 << bit); 375 376 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 377 eb164_intr_mask[byte]); 378 } 379 380 void 381 eb164_intr_disable(irq) 382 int irq; 383 { 384 int byte = (irq / 8), bit = (irq % 8); 385 386 #if 1 387 printf("eb164_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 388 #endif 389 eb164_intr_mask[byte] |= (1 << bit); 390 391 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 392 eb164_intr_mask[byte]); 393 } 394 #endif 395