1 /* $OpenBSD: pci_swiz_bus_io_chipdep.c,v 1.9 2009/12/25 20:52:34 miod Exp $ */ 2 /* $NetBSD: pcs_bus_io_common.c,v 1.14 1996/12/02 22:19:35 cgd Exp $ */ 3 4 /* 5 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Author: Chris G. Demetriou 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 /* 32 * Common PCI Chipset "bus I/O" functions, for chipsets which have to 33 * deal with only a single PCI interface chip in a machine. 34 * 35 * uses: 36 * CHIP name of the 'chip' it's being compiled for. 37 * CHIP_IO_BASE Sparse I/O space base to use. 38 */ 39 40 #include <sys/extent.h> 41 42 #define __C(A,B) __CONCAT(A,B) 43 #define __S(S) __STRING(S) 44 45 #ifndef CHIP_EXTENT_NAME 46 #define CHIP_EXTENT_NAME(v) __S(__C(CHIP,_bus_io)) 47 #endif 48 49 #ifndef CHIP_EXTENT_STORAGE 50 #define CHIP_EXTENT_STORAGE(v) __C(CHIP,_io_ex_storage) 51 static long 52 __C(CHIP,_io_ex_storage)[EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long)]; 53 #endif 54 55 /* mapping/unmapping */ 56 int __C(CHIP,_io_map)(void *, bus_addr_t, bus_size_t, int, 57 bus_space_handle_t *); 58 void __C(CHIP,_io_unmap)(void *, bus_space_handle_t, 59 bus_size_t); 60 int __C(CHIP,_io_subregion)(void *, bus_space_handle_t, 61 bus_size_t, bus_size_t, bus_space_handle_t *); 62 63 /* allocation/deallocation */ 64 int __C(CHIP,_io_alloc)(void *, bus_addr_t, bus_addr_t, 65 bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *, 66 bus_space_handle_t *); 67 void __C(CHIP,_io_free)(void *, bus_space_handle_t, 68 bus_size_t); 69 70 /* get kernel virtual address */ 71 void * __C(CHIP,_io_vaddr)(void *, bus_space_handle_t); 72 73 /* barrier */ 74 inline void __C(CHIP,_io_barrier)(void *, bus_space_handle_t, 75 bus_size_t, bus_size_t, int); 76 77 /* read (single) */ 78 inline u_int8_t __C(CHIP,_io_read_1)(void *, bus_space_handle_t, 79 bus_size_t); 80 inline u_int16_t __C(CHIP,_io_read_2)(void *, bus_space_handle_t, 81 bus_size_t); 82 inline u_int32_t __C(CHIP,_io_read_4)(void *, bus_space_handle_t, 83 bus_size_t); 84 inline u_int64_t __C(CHIP,_io_read_8)(void *, bus_space_handle_t, 85 bus_size_t); 86 87 /* read multiple */ 88 void __C(CHIP,_io_read_multi_1)(void *, bus_space_handle_t, 89 bus_size_t, u_int8_t *, bus_size_t); 90 void __C(CHIP,_io_read_multi_2)(void *, bus_space_handle_t, 91 bus_size_t, u_int16_t *, bus_size_t); 92 void __C(CHIP,_io_read_multi_4)(void *, bus_space_handle_t, 93 bus_size_t, u_int32_t *, bus_size_t); 94 void __C(CHIP,_io_read_multi_8)(void *, bus_space_handle_t, 95 bus_size_t, u_int64_t *, bus_size_t); 96 97 /* read region */ 98 void __C(CHIP,_io_read_region_1)(void *, bus_space_handle_t, 99 bus_size_t, u_int8_t *, bus_size_t); 100 void __C(CHIP,_io_read_region_2)(void *, bus_space_handle_t, 101 bus_size_t, u_int16_t *, bus_size_t); 102 void __C(CHIP,_io_read_region_4)(void *, bus_space_handle_t, 103 bus_size_t, u_int32_t *, bus_size_t); 104 void __C(CHIP,_io_read_region_8)(void *, bus_space_handle_t, 105 bus_size_t, u_int64_t *, bus_size_t); 106 107 /* write (single) */ 108 inline void __C(CHIP,_io_write_1)(void *, bus_space_handle_t, 109 bus_size_t, u_int8_t); 110 inline void __C(CHIP,_io_write_2)(void *, bus_space_handle_t, 111 bus_size_t, u_int16_t); 112 inline void __C(CHIP,_io_write_4)(void *, bus_space_handle_t, 113 bus_size_t, u_int32_t); 114 inline void __C(CHIP,_io_write_8)(void *, bus_space_handle_t, 115 bus_size_t, u_int64_t); 116 117 /* write multiple */ 118 void __C(CHIP,_io_write_multi_1)(void *, bus_space_handle_t, 119 bus_size_t, const u_int8_t *, bus_size_t); 120 void __C(CHIP,_io_write_multi_2)(void *, bus_space_handle_t, 121 bus_size_t, const u_int16_t *, bus_size_t); 122 void __C(CHIP,_io_write_multi_4)(void *, bus_space_handle_t, 123 bus_size_t, const u_int32_t *, bus_size_t); 124 void __C(CHIP,_io_write_multi_8)(void *, bus_space_handle_t, 125 bus_size_t, const u_int64_t *, bus_size_t); 126 127 /* write region */ 128 void __C(CHIP,_io_write_region_1)(void *, bus_space_handle_t, 129 bus_size_t, const u_int8_t *, bus_size_t); 130 void __C(CHIP,_io_write_region_2)(void *, bus_space_handle_t, 131 bus_size_t, const u_int16_t *, bus_size_t); 132 void __C(CHIP,_io_write_region_4)(void *, bus_space_handle_t, 133 bus_size_t, const u_int32_t *, bus_size_t); 134 void __C(CHIP,_io_write_region_8)(void *, bus_space_handle_t, 135 bus_size_t, const u_int64_t *, bus_size_t); 136 137 /* set multiple */ 138 void __C(CHIP,_io_set_multi_1)(void *, bus_space_handle_t, 139 bus_size_t, u_int8_t, bus_size_t); 140 void __C(CHIP,_io_set_multi_2)(void *, bus_space_handle_t, 141 bus_size_t, u_int16_t, bus_size_t); 142 void __C(CHIP,_io_set_multi_4)(void *, bus_space_handle_t, 143 bus_size_t, u_int32_t, bus_size_t); 144 void __C(CHIP,_io_set_multi_8)(void *, bus_space_handle_t, 145 bus_size_t, u_int64_t, bus_size_t); 146 147 /* set region */ 148 void __C(CHIP,_io_set_region_1)(void *, bus_space_handle_t, 149 bus_size_t, u_int8_t, bus_size_t); 150 void __C(CHIP,_io_set_region_2)(void *, bus_space_handle_t, 151 bus_size_t, u_int16_t, bus_size_t); 152 void __C(CHIP,_io_set_region_4)(void *, bus_space_handle_t, 153 bus_size_t, u_int32_t, bus_size_t); 154 void __C(CHIP,_io_set_region_8)(void *, bus_space_handle_t, 155 bus_size_t, u_int64_t, bus_size_t); 156 157 /* copy */ 158 void __C(CHIP,_io_copy_1)(void *, bus_space_handle_t, 159 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 160 void __C(CHIP,_io_copy_2)(void *, bus_space_handle_t, 161 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 162 void __C(CHIP,_io_copy_4)(void *, bus_space_handle_t, 163 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 164 void __C(CHIP,_io_copy_8)(void *, bus_space_handle_t, 165 bus_size_t, bus_space_handle_t, bus_size_t, bus_size_t); 166 167 /* read multiple raw */ 168 void __C(CHIP,_io_read_raw_multi_2)(void *, bus_space_handle_t, 169 bus_size_t, u_int8_t *, bus_size_t); 170 void __C(CHIP,_io_read_raw_multi_4)(void *, bus_space_handle_t, 171 bus_size_t, u_int8_t *, bus_size_t); 172 void __C(CHIP,_io_read_raw_multi_8)(void *, bus_space_handle_t, 173 bus_size_t, u_int8_t *, bus_size_t); 174 175 /* write multiple raw */ 176 void __C(CHIP,_io_write_raw_multi_2)(void *, 177 bus_space_handle_t, bus_size_t, const u_int8_t *, 178 bus_size_t); 179 void __C(CHIP,_io_write_raw_multi_4)(void *, 180 bus_space_handle_t, bus_size_t, const u_int8_t *, 181 bus_size_t); 182 void __C(CHIP,_io_write_raw_multi_8)(void *, 183 bus_space_handle_t, bus_size_t, const u_int8_t *, 184 bus_size_t); 185 186 void 187 __C(CHIP,_bus_io_init)(t, v) 188 bus_space_tag_t t; 189 void *v; 190 { 191 struct extent *ex; 192 193 /* 194 * Initialize the bus space tag. 195 */ 196 197 /* cookie */ 198 t->abs_cookie = v; 199 200 /* mapping/unmapping */ 201 t->abs_map = __C(CHIP,_io_map); 202 t->abs_unmap = __C(CHIP,_io_unmap); 203 t->abs_subregion = __C(CHIP,_io_subregion); 204 205 /* allocation/deallocation */ 206 t->abs_alloc = __C(CHIP,_io_alloc); 207 t->abs_free = __C(CHIP,_io_free); 208 209 /* get kernel virtual address */ 210 t->abs_vaddr = __C(CHIP,_io_vaddr); 211 212 /* barrier */ 213 t->abs_barrier = __C(CHIP,_io_barrier); 214 215 /* read (single) */ 216 t->abs_r_1 = __C(CHIP,_io_read_1); 217 t->abs_r_2 = __C(CHIP,_io_read_2); 218 t->abs_r_4 = __C(CHIP,_io_read_4); 219 t->abs_r_8 = __C(CHIP,_io_read_8); 220 221 /* read multiple */ 222 t->abs_rm_1 = __C(CHIP,_io_read_multi_1); 223 t->abs_rm_2 = __C(CHIP,_io_read_multi_2); 224 t->abs_rm_4 = __C(CHIP,_io_read_multi_4); 225 t->abs_rm_8 = __C(CHIP,_io_read_multi_8); 226 227 /* read region */ 228 t->abs_rr_1 = __C(CHIP,_io_read_region_1); 229 t->abs_rr_2 = __C(CHIP,_io_read_region_2); 230 t->abs_rr_4 = __C(CHIP,_io_read_region_4); 231 t->abs_rr_8 = __C(CHIP,_io_read_region_8); 232 233 /* write (single) */ 234 t->abs_w_1 = __C(CHIP,_io_write_1); 235 t->abs_w_2 = __C(CHIP,_io_write_2); 236 t->abs_w_4 = __C(CHIP,_io_write_4); 237 t->abs_w_8 = __C(CHIP,_io_write_8); 238 239 /* write multiple */ 240 t->abs_wm_1 = __C(CHIP,_io_write_multi_1); 241 t->abs_wm_2 = __C(CHIP,_io_write_multi_2); 242 t->abs_wm_4 = __C(CHIP,_io_write_multi_4); 243 t->abs_wm_8 = __C(CHIP,_io_write_multi_8); 244 245 /* write region */ 246 t->abs_wr_1 = __C(CHIP,_io_write_region_1); 247 t->abs_wr_2 = __C(CHIP,_io_write_region_2); 248 t->abs_wr_4 = __C(CHIP,_io_write_region_4); 249 t->abs_wr_8 = __C(CHIP,_io_write_region_8); 250 251 /* set multiple */ 252 t->abs_sm_1 = __C(CHIP,_io_set_multi_1); 253 t->abs_sm_2 = __C(CHIP,_io_set_multi_2); 254 t->abs_sm_4 = __C(CHIP,_io_set_multi_4); 255 t->abs_sm_8 = __C(CHIP,_io_set_multi_8); 256 257 /* set region */ 258 t->abs_sr_1 = __C(CHIP,_io_set_region_1); 259 t->abs_sr_2 = __C(CHIP,_io_set_region_2); 260 t->abs_sr_4 = __C(CHIP,_io_set_region_4); 261 t->abs_sr_8 = __C(CHIP,_io_set_region_8); 262 263 /* copy */ 264 t->abs_c_1 = __C(CHIP,_io_copy_1); 265 t->abs_c_2 = __C(CHIP,_io_copy_2); 266 t->abs_c_4 = __C(CHIP,_io_copy_4); 267 t->abs_c_8 = __C(CHIP,_io_copy_8); 268 269 /* read multiple raw */ 270 t->abs_rrm_2 = __C(CHIP,_io_read_raw_multi_2); 271 t->abs_rrm_4 = __C(CHIP,_io_read_raw_multi_4); 272 t->abs_rrm_8 = __C(CHIP,_io_read_raw_multi_8); 273 274 /* write multiple raw*/ 275 t->abs_wrm_2 = __C(CHIP,_io_write_raw_multi_2); 276 t->abs_wrm_4 = __C(CHIP,_io_write_raw_multi_4) ; 277 t->abs_wrm_8 = __C(CHIP,_io_write_raw_multi_8); 278 279 280 /* XXX WE WANT EXTENT_NOCOALESCE, BUT WE CAN'T USE IT. XXX */ 281 ex = extent_create(CHIP_EXTENT_NAME(v), 0x0UL, 0xffffffffUL, 282 M_DEVBUF, (caddr_t)CHIP_EXTENT_STORAGE(v), 283 sizeof(CHIP_EXTENT_STORAGE(v)), EX_NOWAIT); 284 extent_alloc_region(ex, 0, 0xffffffffUL, EX_NOWAIT); 285 286 #ifdef CHIP_IO_W1_BUS_START 287 #ifdef EXTENT_DEBUG 288 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W1_BUS_START(v), 289 CHIP_IO_W1_BUS_END(v)); 290 #endif 291 extent_free(ex, CHIP_IO_W1_BUS_START(v), 292 CHIP_IO_W1_BUS_END(v) - CHIP_IO_W1_BUS_START(v) + 1, EX_NOWAIT); 293 #endif 294 #ifdef CHIP_IO_W2_BUS_START 295 #ifdef EXTENT_DEBUG 296 printf("io: freeing from 0x%lx to 0x%lx\n", CHIP_IO_W2_BUS_START(v), 297 CHIP_IO_W2_BUS_END(v)); 298 #endif 299 extent_free(ex, CHIP_IO_W2_BUS_START(v), 300 CHIP_IO_W2_BUS_END(v) - CHIP_IO_W2_BUS_START(v) + 1, EX_NOWAIT); 301 #endif 302 303 #ifdef EXTENT_DEBUG 304 extent_print(ex); 305 #endif 306 CHIP_IO_EXTENT(v) = ex; 307 } 308 309 int 310 __C(CHIP,_io_map)(v, ioaddr, iosize, flags, iohp) 311 void *v; 312 bus_addr_t ioaddr; 313 bus_size_t iosize; 314 int flags; 315 bus_space_handle_t *iohp; 316 { 317 bus_addr_t ioend = ioaddr + (iosize - 1); 318 int error; 319 320 /* 321 * Can't map i/o space linearly. 322 */ 323 if (flags & BUS_SPACE_MAP_LINEAR) 324 return (EOPNOTSUPP); 325 326 #ifdef EXTENT_DEBUG 327 printf("io: allocating 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 328 #endif 329 error = extent_alloc_region(CHIP_IO_EXTENT(v), ioaddr, iosize, 330 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 331 if (error) { 332 #ifdef EXTENT_DEBUG 333 printf("io: allocation failed (%d)\n", error); 334 extent_print(CHIP_IO_EXTENT(v)); 335 #endif 336 return (error); 337 } 338 339 #ifdef CHIP_IO_W1_BUS_START 340 if (ioaddr >= CHIP_IO_W1_BUS_START(v) && 341 ioend <= CHIP_IO_W1_BUS_END(v)) { 342 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W1_SYS_START(v)) >> 5) + 343 (ioaddr - CHIP_IO_W1_BUS_START(v)); 344 } else 345 #endif 346 #ifdef CHIP_IO_W2_BUS_START 347 if (ioaddr >= CHIP_IO_W2_BUS_START(v) && 348 ioend <= CHIP_IO_W2_BUS_END(v)) { 349 *iohp = (ALPHA_PHYS_TO_K0SEG(CHIP_IO_W2_SYS_START(v)) >> 5) + 350 (ioaddr - CHIP_IO_W2_BUS_START(v)); 351 } else 352 #endif 353 { 354 #ifdef EXTENT_DEBUG 355 printf("\n"); 356 #ifdef CHIP_IO_W1_BUS_START 357 printf("%s: window[1]=0x%lx-0x%lx\n", 358 __S(__C(CHIP,_io_map)), CHIP_IO_W1_BUS_START(v), 359 CHIP_IO_W1_BUS_END(v)); 360 #endif 361 #ifdef CHIP_IO_W2_BUS_START 362 printf("%s: window[2]=0x%lx-0x%lx\n", 363 __S(__C(CHIP,_io_map)), CHIP_IO_W2_BUS_START(v), 364 CHIP_IO_W2_BUS_END(v)); 365 #endif 366 panic("%s: don't know how to map %lx", 367 __S(__C(CHIP,_io_map)), ioaddr); 368 #endif 369 return (EINVAL); 370 } 371 372 return (0); 373 } 374 375 void 376 __C(CHIP,_io_unmap)(v, ioh, iosize) 377 void *v; 378 bus_space_handle_t ioh; 379 bus_size_t iosize; 380 { 381 bus_addr_t ioaddr; 382 int error; 383 384 #ifdef EXTENT_DEBUG 385 printf("io: freeing handle 0x%lx for 0x%lx\n", ioh, iosize); 386 #endif 387 388 ioh = ALPHA_K0SEG_TO_PHYS(ioh << 5) >> 5; 389 390 #ifdef CHIP_IO_W1_BUS_START 391 if ((ioh << 5) >= CHIP_IO_W1_SYS_START(v) && 392 (ioh << 5) <= CHIP_IO_W1_SYS_END(v)) { 393 ioaddr = CHIP_IO_W1_BUS_START(v) + 394 (ioh - (CHIP_IO_W1_SYS_START(v) >> 5)); 395 } else 396 #endif 397 #ifdef CHIP_IO_W2_BUS_START 398 if ((ioh << 5) >= CHIP_IO_W2_SYS_START(v) && 399 (ioh << 5) <= CHIP_IO_W2_SYS_END(v)) { 400 ioaddr = CHIP_IO_W2_BUS_START(v) + 401 (ioh - (CHIP_IO_W2_SYS_START(v) >> 5)); 402 } else 403 #endif 404 { 405 printf("\n"); 406 #ifdef CHIP_IO_W1_BUS_START 407 printf("%s: sys window[1]=0x%lx-0x%lx\n", 408 __S(__C(CHIP,_io_map)), CHIP_IO_W1_SYS_START(v), 409 CHIP_IO_W1_SYS_END(v)); 410 #endif 411 #ifdef CHIP_IO_W2_BUS_START 412 printf("%s: sys window[2]=0x%lx-0x%lx\n", 413 __S(__C(CHIP,_io_map)), CHIP_IO_W2_SYS_START(v), 414 CHIP_IO_W2_SYS_END(v)); 415 #endif 416 panic("%s: don't know how to unmap %lx", 417 __S(__C(CHIP,_io_unmap)), (ioh << 5)); 418 } 419 420 #ifdef EXTENT_DEBUG 421 printf("io: freeing 0x%lx to 0x%lx\n", ioaddr, ioaddr + iosize - 1); 422 #endif 423 error = extent_free(CHIP_IO_EXTENT(v), ioaddr, iosize, 424 EX_NOWAIT | (CHIP_EX_MALLOC_SAFE(v) ? EX_MALLOCOK : 0)); 425 if (error) { 426 printf("%s: WARNING: could not unmap 0x%lx-0x%lx (error %d)\n", 427 __S(__C(CHIP,_io_unmap)), ioaddr, ioaddr + iosize - 1, 428 error); 429 #ifdef EXTENT_DEBUG 430 extent_print(CHIP_IO_EXTENT(v)); 431 #endif 432 } 433 } 434 435 int 436 __C(CHIP,_io_subregion)(v, ioh, offset, size, nioh) 437 void *v; 438 bus_space_handle_t ioh, *nioh; 439 bus_size_t offset, size; 440 { 441 442 *nioh = ioh + offset; 443 return (0); 444 } 445 446 int 447 __C(CHIP,_io_alloc)(v, rstart, rend, size, align, boundary, flags, 448 addrp, bshp) 449 void *v; 450 bus_addr_t rstart, rend, *addrp; 451 bus_size_t size, align, boundary; 452 int flags; 453 bus_space_handle_t *bshp; 454 { 455 456 /* XXX XXX XXX XXX XXX XXX */ 457 panic("%s not implemented", __S(__C(CHIP,_io_alloc))); 458 } 459 460 void 461 __C(CHIP,_io_free)(v, bsh, size) 462 void *v; 463 bus_space_handle_t bsh; 464 bus_size_t size; 465 { 466 467 /* XXX XXX XXX XXX XXX XXX */ 468 panic("%s not implemented", __S(__C(CHIP,_io_free))); 469 } 470 471 void * 472 __C(CHIP,_io_vaddr)(v, bsh) 473 void *v; 474 bus_space_handle_t bsh; 475 { 476 /* 477 * _io_map() catches BUS_SPACE_MAP_LINEAR, 478 * so we shouldn't get here 479 */ 480 panic("_io_vaddr"); 481 } 482 483 inline void 484 __C(CHIP,_io_barrier)(v, h, o, l, f) 485 void *v; 486 bus_space_handle_t h; 487 bus_size_t o, l; 488 int f; 489 { 490 491 if ((f & BUS_SPACE_BARRIER_READ) != 0) 492 alpha_mb(); 493 else if ((f & BUS_SPACE_BARRIER_WRITE) != 0) 494 alpha_wmb(); 495 } 496 497 inline u_int8_t 498 __C(CHIP,_io_read_1)(v, ioh, off) 499 void *v; 500 bus_space_handle_t ioh; 501 bus_size_t off; 502 { 503 register bus_space_handle_t tmpioh; 504 register u_int32_t *port, val; 505 register u_int8_t rval; 506 register int offset; 507 508 alpha_mb(); 509 510 tmpioh = ioh + off; 511 offset = tmpioh & 3; 512 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 513 val = *port; 514 rval = ((val) >> (8 * offset)) & 0xff; 515 516 return rval; 517 } 518 519 inline u_int16_t 520 __C(CHIP,_io_read_2)(v, ioh, off) 521 void *v; 522 bus_space_handle_t ioh; 523 bus_size_t off; 524 { 525 register bus_space_handle_t tmpioh; 526 register u_int32_t *port, val; 527 register u_int16_t rval; 528 register int offset; 529 530 alpha_mb(); 531 532 tmpioh = ioh + off; 533 offset = tmpioh & 3; 534 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 535 val = *port; 536 rval = ((val) >> (8 * offset)) & 0xffff; 537 538 return rval; 539 } 540 541 inline u_int32_t 542 __C(CHIP,_io_read_4)(v, ioh, off) 543 void *v; 544 bus_space_handle_t ioh; 545 bus_size_t off; 546 { 547 register bus_space_handle_t tmpioh; 548 register u_int32_t *port, val; 549 register u_int32_t rval; 550 register int offset; 551 552 alpha_mb(); 553 554 tmpioh = ioh + off; 555 offset = tmpioh & 3; 556 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 557 val = *port; 558 #if 0 559 rval = ((val) >> (8 * offset)) & 0xffffffff; 560 #else 561 rval = val; 562 #endif 563 564 return rval; 565 } 566 567 inline u_int64_t 568 __C(CHIP,_io_read_8)(v, ioh, off) 569 void *v; 570 bus_space_handle_t ioh; 571 bus_size_t off; 572 { 573 574 /* XXX XXX XXX */ 575 panic("%s not implemented", __S(__C(CHIP,_io_read_8))); 576 } 577 578 #define CHIP_io_read_multi_N(BYTES,TYPE) \ 579 void \ 580 __C(__C(CHIP,_io_read_multi_),BYTES)(v, h, o, a, c) \ 581 void *v; \ 582 bus_space_handle_t h; \ 583 bus_size_t o, c; \ 584 TYPE *a; \ 585 { \ 586 \ 587 while (c-- > 0) { \ 588 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 589 BUS_SPACE_BARRIER_READ); \ 590 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 591 } \ 592 } 593 CHIP_io_read_multi_N(1,u_int8_t) 594 CHIP_io_read_multi_N(2,u_int16_t) 595 CHIP_io_read_multi_N(4,u_int32_t) 596 CHIP_io_read_multi_N(8,u_int64_t) 597 598 #define CHIP_io_read_region_N(BYTES,TYPE) \ 599 void \ 600 __C(__C(CHIP,_io_read_region_),BYTES)(v, h, o, a, c) \ 601 void *v; \ 602 bus_space_handle_t h; \ 603 bus_size_t o, c; \ 604 TYPE *a; \ 605 { \ 606 \ 607 while (c-- > 0) { \ 608 *a++ = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 609 o += sizeof *a; \ 610 } \ 611 } 612 CHIP_io_read_region_N(1,u_int8_t) 613 CHIP_io_read_region_N(2,u_int16_t) 614 CHIP_io_read_region_N(4,u_int32_t) 615 CHIP_io_read_region_N(8,u_int64_t) 616 617 inline void 618 __C(CHIP,_io_write_1)(v, ioh, off, val) 619 void *v; 620 bus_space_handle_t ioh; 621 bus_size_t off; 622 u_int8_t val; 623 { 624 register bus_space_handle_t tmpioh; 625 register u_int32_t *port, nval; 626 register int offset; 627 628 tmpioh = ioh + off; 629 offset = tmpioh & 3; 630 nval = val << (8 * offset); 631 port = (u_int32_t *)((tmpioh << 5) | (0 << 3)); 632 *port = nval; 633 alpha_mb(); 634 } 635 636 inline void 637 __C(CHIP,_io_write_2)(v, ioh, off, val) 638 void *v; 639 bus_space_handle_t ioh; 640 bus_size_t off; 641 u_int16_t val; 642 { 643 register bus_space_handle_t tmpioh; 644 register u_int32_t *port, nval; 645 register int offset; 646 647 tmpioh = ioh + off; 648 offset = tmpioh & 3; 649 nval = val << (8 * offset); 650 port = (u_int32_t *)((tmpioh << 5) | (1 << 3)); 651 *port = nval; 652 alpha_mb(); 653 } 654 655 inline void 656 __C(CHIP,_io_write_4)(v, ioh, off, val) 657 void *v; 658 bus_space_handle_t ioh; 659 bus_size_t off; 660 u_int32_t val; 661 { 662 register bus_space_handle_t tmpioh; 663 register u_int32_t *port, nval; 664 register int offset; 665 666 tmpioh = ioh + off; 667 offset = tmpioh & 3; 668 nval = val /*<< (8 * offset)*/; 669 port = (u_int32_t *)((tmpioh << 5) | (3 << 3)); 670 *port = nval; 671 alpha_mb(); 672 } 673 674 inline void 675 __C(CHIP,_io_write_8)(v, ioh, off, val) 676 void *v; 677 bus_space_handle_t ioh; 678 bus_size_t off; 679 u_int64_t val; 680 { 681 682 /* XXX XXX XXX */ 683 panic("%s not implemented", __S(__C(CHIP,_io_write_8))); 684 alpha_mb(); 685 } 686 687 #define CHIP_io_write_multi_N(BYTES,TYPE) \ 688 void \ 689 __C(__C(CHIP,_io_write_multi_),BYTES)(v, h, o, a, c) \ 690 void *v; \ 691 bus_space_handle_t h; \ 692 bus_size_t o, c; \ 693 const TYPE *a; \ 694 { \ 695 \ 696 while (c-- > 0) { \ 697 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 698 __C(CHIP,_io_barrier)(v, h, o, sizeof *a, \ 699 BUS_SPACE_BARRIER_WRITE); \ 700 } \ 701 } 702 CHIP_io_write_multi_N(1,u_int8_t) 703 CHIP_io_write_multi_N(2,u_int16_t) 704 CHIP_io_write_multi_N(4,u_int32_t) 705 CHIP_io_write_multi_N(8,u_int64_t) 706 707 #define CHIP_io_write_region_N(BYTES,TYPE) \ 708 void \ 709 __C(__C(CHIP,_io_write_region_),BYTES)(v, h, o, a, c) \ 710 void *v; \ 711 bus_space_handle_t h; \ 712 bus_size_t o, c; \ 713 const TYPE *a; \ 714 { \ 715 \ 716 while (c-- > 0) { \ 717 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, *a++); \ 718 o += sizeof *a; \ 719 } \ 720 } 721 CHIP_io_write_region_N(1,u_int8_t) 722 CHIP_io_write_region_N(2,u_int16_t) 723 CHIP_io_write_region_N(4,u_int32_t) 724 CHIP_io_write_region_N(8,u_int64_t) 725 726 #define CHIP_io_set_multi_N(BYTES,TYPE) \ 727 void \ 728 __C(__C(CHIP,_io_set_multi_),BYTES)(v, h, o, val, c) \ 729 void *v; \ 730 bus_space_handle_t h; \ 731 bus_size_t o, c; \ 732 TYPE val; \ 733 { \ 734 \ 735 while (c-- > 0) { \ 736 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 737 __C(CHIP,_io_barrier)(v, h, o, sizeof val, \ 738 BUS_SPACE_BARRIER_WRITE); \ 739 } \ 740 } 741 CHIP_io_set_multi_N(1,u_int8_t) 742 CHIP_io_set_multi_N(2,u_int16_t) 743 CHIP_io_set_multi_N(4,u_int32_t) 744 CHIP_io_set_multi_N(8,u_int64_t) 745 746 #define CHIP_io_set_region_N(BYTES,TYPE) \ 747 void \ 748 __C(__C(CHIP,_io_set_region_),BYTES)(v, h, o, val, c) \ 749 void *v; \ 750 bus_space_handle_t h; \ 751 bus_size_t o, c; \ 752 TYPE val; \ 753 { \ 754 \ 755 while (c-- > 0) { \ 756 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, val); \ 757 o += sizeof val; \ 758 } \ 759 } 760 CHIP_io_set_region_N(1,u_int8_t) 761 CHIP_io_set_region_N(2,u_int16_t) 762 CHIP_io_set_region_N(4,u_int32_t) 763 CHIP_io_set_region_N(8,u_int64_t) 764 765 #define CHIP_io_copy_N(BYTES) \ 766 void \ 767 __C(__C(CHIP,_io_copy_),BYTES)(v, h1, o1, h2, o2, c) \ 768 void *v; \ 769 bus_space_handle_t h1, h2; \ 770 bus_size_t o1, o2, c; \ 771 { \ 772 bus_size_t i, o; \ 773 \ 774 for (i = 0, o = 0; i < c; i++, o += BYTES) \ 775 __C(__C(CHIP,_io_write_),BYTES)(v, h2, o2 + o, \ 776 __C(__C(CHIP,_io_read_),BYTES)(v, h1, o1 + o)); \ 777 } 778 CHIP_io_copy_N(1) 779 CHIP_io_copy_N(2) 780 CHIP_io_copy_N(4) 781 CHIP_io_copy_N(8) 782 783 #define CHIP_io_read_raw_multi_N(BYTES,TYPE) \ 784 void \ 785 __C(__C(CHIP,_io_read_raw_multi_),BYTES)(v, h, o, a, c) \ 786 void *v; \ 787 bus_space_handle_t h; \ 788 bus_size_t o, c; \ 789 u_int8_t *a; \ 790 { \ 791 TYPE temp; \ 792 int i; \ 793 \ 794 while (c > 0) { \ 795 __C(CHIP,_io_barrier)(v, h, o, BYTES, \ 796 BUS_SPACE_BARRIER_READ); \ 797 temp = __C(__C(CHIP,_io_read_),BYTES)(v, h, o); \ 798 i = MIN(c, BYTES); \ 799 c -= i; \ 800 while (i--) { \ 801 *a++ = temp & 0xff; \ 802 temp >>= 8; \ 803 } \ 804 } \ 805 } 806 CHIP_io_read_raw_multi_N(2,u_int16_t) 807 CHIP_io_read_raw_multi_N(4,u_int32_t) 808 CHIP_io_read_raw_multi_N(8,u_int64_t) 809 810 #define CHIP_io_write_raw_multi_N(BYTES,TYPE) \ 811 void \ 812 __C(__C(CHIP,_io_write_raw_multi_),BYTES)(v, h, o, a, c) \ 813 void *v; \ 814 bus_space_handle_t h; \ 815 bus_size_t o, c; \ 816 const u_int8_t *a; \ 817 { \ 818 TYPE temp; \ 819 int i; \ 820 \ 821 while (c > 0) { \ 822 temp = 0; \ 823 for (i = BYTES - 1; i >= 0; i--) { \ 824 temp <<= 8; \ 825 if (i < c) \ 826 temp |= *(a + i); \ 827 } \ 828 __C(__C(CHIP,_io_write_),BYTES)(v, h, o, temp); \ 829 __C(CHIP,_io_barrier)(v, h, o, BYTES, \ 830 BUS_SPACE_BARRIER_WRITE); \ 831 i = MIN(c, BYTES); \ 832 c -= i; \ 833 a += i; \ 834 } \ 835 } 836 CHIP_io_write_raw_multi_N(2,u_int16_t) 837 CHIP_io_write_raw_multi_N(4,u_int32_t) 838 CHIP_io_write_raw_multi_N(8,u_int64_t) 839