1 /* $OpenBSD: sio_pic.c,v 1.19 2001/10/26 01:28:06 nate Exp $ */ 2 /* $NetBSD: sio_pic.c,v 1.28 2000/06/06 03:10:13 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 43 * All rights reserved. 44 * 45 * Author: Chris G. Demetriou 46 * 47 * Permission to use, copy, modify and distribute this software and 48 * its documentation is hereby granted, provided that both the copyright 49 * notice and this permission notice appear in all copies of the 50 * software, derivative works or modified versions, and any portions 51 * thereof, and that both notices appear in supporting documentation. 52 * 53 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 54 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 55 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 56 * 57 * Carnegie Mellon requests users of this software to return to 58 * 59 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 60 * School of Computer Science 61 * Carnegie Mellon University 62 * Pittsburgh PA 15213-3890 63 * 64 * any improvements or extensions that they make and grant Carnegie the 65 * rights to redistribute these changes. 66 */ 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/device.h> 71 #include <sys/malloc.h> 72 #include <sys/syslog.h> 73 74 #include <machine/intr.h> 75 #include <machine/bus.h> 76 77 #include <dev/pci/pcireg.h> 78 #include <dev/pci/pcivar.h> 79 #include <dev/pci/pcidevs.h> 80 81 #include <dev/pci/cy82c693reg.h> 82 #include <dev/pci/cy82c693var.h> 83 84 #include <dev/isa/isareg.h> 85 #include <dev/isa/isavar.h> 86 #include <alpha/pci/siovar.h> 87 88 #include "sio.h" 89 90 /* 91 * To add to the long history of wonderful PROM console traits, 92 * AlphaStation PROMs don't reset themselves completely on boot! 93 * Therefore, if an interrupt was turned on when the kernel was 94 * started, we're not going to EVER turn it off... I don't know 95 * what will happen if new interrupts (that the PROM console doesn't 96 * want) are turned on. I'll burn that bridge when I come to it. 97 */ 98 #define BROKEN_PROM_CONSOLE 99 100 /* 101 * Private functions and variables. 102 */ 103 104 bus_space_tag_t sio_iot; 105 pci_chipset_tag_t sio_pc; 106 bus_space_handle_t sio_ioh_icu1, sio_ioh_icu2; 107 108 #define ICU_LEN 16 /* number of ISA IRQs */ 109 110 static struct alpha_shared_intr *sio_intr; 111 112 #ifndef STRAY_MAX 113 #define STRAY_MAX 5 114 #endif 115 116 #ifdef BROKEN_PROM_CONSOLE 117 /* 118 * If prom console is broken, must remember the initial interrupt 119 * settings and enforce them. WHEE! 120 */ 121 u_int8_t initial_ocw1[2]; 122 u_int8_t initial_elcr[2]; 123 #endif 124 125 void sio_setirqstat __P((int, int, int)); 126 int sio_intr_alloc __P((void *, int, int, int *)); 127 128 u_int8_t (*sio_read_elcr) __P((int)); 129 void (*sio_write_elcr) __P((int, u_int8_t)); 130 static void specific_eoi __P((int)); 131 #ifdef BROKEN_PROM_CONSOLE 132 void sio_intr_shutdown __P((void *)); 133 #endif 134 135 /******************** i82378 SIO ELCR functions ********************/ 136 137 int i82378_setup_elcr __P((void)); 138 u_int8_t i82378_read_elcr __P((int)); 139 void i82378_write_elcr __P((int, u_int8_t)); 140 141 bus_space_handle_t sio_ioh_elcr; 142 143 int 144 i82378_setup_elcr() 145 { 146 int rv; 147 148 /* 149 * We could probe configuration space to see that there's 150 * actually an SIO present, but we are using this as a 151 * fall-back in case nothing else matches. 152 */ 153 154 rv = bus_space_map(sio_iot, 0x4d0, 2, 0, &sio_ioh_elcr); 155 156 if (rv == 0) { 157 sio_read_elcr = i82378_read_elcr; 158 sio_write_elcr = i82378_write_elcr; 159 } 160 161 return (rv); 162 } 163 164 u_int8_t 165 i82378_read_elcr(elcr) 166 int elcr; 167 { 168 169 return (bus_space_read_1(sio_iot, sio_ioh_elcr, elcr)); 170 } 171 172 void 173 i82378_write_elcr(elcr, val) 174 int elcr; 175 u_int8_t val; 176 { 177 178 bus_space_write_1(sio_iot, sio_ioh_elcr, elcr, val); 179 } 180 181 /******************** Cypress CY82C693 ELCR functions ********************/ 182 183 int cy82c693_setup_elcr __P((void)); 184 u_int8_t cy82c693_read_elcr __P((int)); 185 void cy82c693_write_elcr __P((int, u_int8_t)); 186 187 const struct cy82c693_handle *sio_cy82c693_handle; 188 189 int 190 cy82c693_setup_elcr() 191 { 192 int device, maxndevs; 193 pcitag_t tag; 194 pcireg_t id; 195 196 /* 197 * Search PCI configuration space for a Cypress CY82C693. 198 * 199 * Note we can make some assumptions about our bus number 200 * here, because: 201 * 202 * (1) there can be at most one ISA/EISA bridge per PCI bus, and 203 * 204 * (2) any ISA/EISA bridges must be attached to primary PCI 205 * busses (i.e. bus zero). 206 */ 207 208 maxndevs = pci_bus_maxdevs(sio_pc, 0); 209 210 for (device = 0; device < maxndevs; device++) { 211 tag = pci_make_tag(sio_pc, 0, device, 0); 212 id = pci_conf_read(sio_pc, tag, PCI_ID_REG); 213 214 /* Invalid vendor ID value? */ 215 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 216 continue; 217 /* XXX Not invalid, but we've done this ~forever. */ 218 if (PCI_VENDOR(id) == 0) 219 continue; 220 221 if (PCI_VENDOR(id) != PCI_VENDOR_CONTAQ || 222 PCI_PRODUCT(id) != PCI_PRODUCT_CONTAQ_82C693) 223 continue; 224 225 /* 226 * Found one! 227 */ 228 229 #if 0 230 printf("cy82c693_setup_elcr: found 82C693 at device %d\n", 231 device); 232 #endif 233 234 sio_cy82c693_handle = cy82c693_init(sio_iot); 235 sio_read_elcr = cy82c693_read_elcr; 236 sio_write_elcr = cy82c693_write_elcr; 237 238 return (0); 239 } 240 241 /* 242 * Didn't find a CY82C693. 243 */ 244 return (ENODEV); 245 } 246 247 u_int8_t 248 cy82c693_read_elcr(elcr) 249 int elcr; 250 { 251 252 return (cy82c693_read(sio_cy82c693_handle, CONFIG_ELCR1 + elcr)); 253 } 254 255 void 256 cy82c693_write_elcr(elcr, val) 257 int elcr; 258 u_int8_t val; 259 { 260 261 cy82c693_write(sio_cy82c693_handle, CONFIG_ELCR1 + elcr, val); 262 } 263 264 /******************** ELCR access function configuration ********************/ 265 266 /* 267 * Put the Intel SIO at the end, so we fall back on it if we don't 268 * find anything else. If any of the non-Intel functions find a 269 * matching device, but are unable to map it for whatever reason, 270 * they should panic. 271 */ 272 273 int (*sio_elcr_setup_funcs[]) __P((void)) = { 274 cy82c693_setup_elcr, 275 i82378_setup_elcr, 276 NULL, 277 }; 278 279 /******************** Shared SIO/Cypress functions ********************/ 280 281 void 282 sio_setirqstat(irq, enabled, type) 283 int irq, enabled; 284 int type; 285 { 286 u_int8_t ocw1[2], elcr[2]; 287 int icu, bit; 288 289 #if 0 290 printf("sio_setirqstat: irq %d: %s, %s\n", irq, 291 enabled ? "enabled" : "disabled", isa_intr_typename(type)); 292 #endif 293 294 icu = irq / 8; 295 bit = irq % 8; 296 297 ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); 298 ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); 299 elcr[0] = (*sio_read_elcr)(0); /* XXX */ 300 elcr[1] = (*sio_read_elcr)(1); /* XXX */ 301 302 /* 303 * interrupt enable: set bit to mask (disable) interrupt. 304 */ 305 if (enabled) 306 ocw1[icu] &= ~(1 << bit); 307 else 308 ocw1[icu] |= 1 << bit; 309 310 /* 311 * interrupt type select: set bit to get level-triggered. 312 */ 313 if (type == IST_LEVEL) 314 elcr[icu] |= 1 << bit; 315 else 316 elcr[icu] &= ~(1 << bit); 317 318 #ifdef not_here 319 /* see the init function... */ 320 ocw1[0] &= ~0x04; /* always enable IRQ2 on first PIC */ 321 elcr[0] &= ~0x07; /* IRQ[0-2] must be edge-triggered */ 322 elcr[1] &= ~0x21; /* IRQ[13,8] must be edge-triggered */ 323 #endif 324 325 bus_space_write_1(sio_iot, sio_ioh_icu1, 1, ocw1[0]); 326 bus_space_write_1(sio_iot, sio_ioh_icu2, 1, ocw1[1]); 327 (*sio_write_elcr)(0, elcr[0]); /* XXX */ 328 (*sio_write_elcr)(1, elcr[1]); /* XXX */ 329 } 330 331 void 332 sio_intr_setup(pc, iot) 333 pci_chipset_tag_t pc; 334 bus_space_tag_t iot; 335 { 336 #ifdef notyet 337 char *cp; 338 #endif 339 int i; 340 341 sio_iot = iot; 342 sio_pc = pc; 343 344 if (bus_space_map(sio_iot, IO_ICU1, 2, 0, &sio_ioh_icu1) || 345 bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2)) 346 panic("sio_intr_setup: can't map ICU I/O ports"); 347 348 for (i = 0; sio_elcr_setup_funcs[i] != NULL; i++) 349 if ((*sio_elcr_setup_funcs[i])() == 0) 350 break; 351 if (sio_elcr_setup_funcs[i] == NULL) 352 panic("sio_intr_setup: can't map ELCR"); 353 354 #ifdef BROKEN_PROM_CONSOLE 355 /* 356 * Remember the initial values, so we can restore them later. 357 */ 358 initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1); 359 initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1); 360 initial_elcr[0] = (*sio_read_elcr)(0); /* XXX */ 361 initial_elcr[1] = (*sio_read_elcr)(1); /* XXX */ 362 shutdownhook_establish(sio_intr_shutdown, 0); 363 #endif 364 365 sio_intr = alpha_shared_intr_alloc(ICU_LEN); 366 367 /* 368 * set up initial values for interrupt enables. 369 */ 370 for (i = 0; i < ICU_LEN; i++) { 371 alpha_shared_intr_set_maxstrays(sio_intr, i, STRAY_MAX); 372 373 #ifdef notyet 374 cp = alpha_shared_intr_string(sio_intr, i); 375 sprintf(cp, "irq %d", i); 376 evcnt_attach_dynamic(alpha_shared_intr_evcnt(sio_intr, i), 377 EVCNT_TYPE_INTR, NULL, "isa", cp); 378 #endif 379 380 switch (i) { 381 case 0: 382 case 1: 383 case 8: 384 case 13: 385 /* 386 * IRQs 0, 1, 8, and 13 must always be 387 * edge-triggered. 388 */ 389 sio_setirqstat(i, 0, IST_EDGE); 390 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 391 IST_EDGE); 392 specific_eoi(i); 393 break; 394 395 case 2: 396 /* 397 * IRQ 2 must be edge-triggered, and should be 398 * enabled (otherwise IRQs 8-15 are ignored). 399 */ 400 sio_setirqstat(i, 1, IST_EDGE); 401 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 402 IST_UNUSABLE); 403 break; 404 405 default: 406 /* 407 * Otherwise, disable the IRQ and set its 408 * type to (effectively) "unknown." 409 */ 410 sio_setirqstat(i, 0, IST_NONE); 411 alpha_shared_intr_set_dfltsharetype(sio_intr, i, 412 IST_NONE); 413 specific_eoi(i); 414 break; 415 } 416 } 417 } 418 419 #ifdef BROKEN_PROM_CONSOLE 420 void 421 sio_intr_shutdown(arg) 422 void *arg; 423 { 424 /* 425 * Restore the initial values, to make the PROM happy. 426 */ 427 bus_space_write_1(sio_iot, sio_ioh_icu1, 1, initial_ocw1[0]); 428 bus_space_write_1(sio_iot, sio_ioh_icu2, 1, initial_ocw1[1]); 429 (*sio_write_elcr)(0, initial_elcr[0]); /* XXX */ 430 (*sio_write_elcr)(1, initial_elcr[1]); /* XXX */ 431 } 432 #endif 433 434 const char * 435 sio_intr_string(v, irq) 436 void *v; 437 int irq; 438 { 439 static char irqstr[12]; /* 8 + 2 + NULL + sanity */ 440 441 if (irq == 0 || irq >= ICU_LEN || irq == 2) 442 panic("sio_intr_string: bogus isa irq 0x%x\n", irq); 443 444 sprintf(irqstr, "isa irq %d", irq); 445 return (irqstr); 446 } 447 448 int 449 sio_intr_line(v, irq) 450 void *v; 451 int irq; 452 { 453 return (irq); 454 } 455 456 #ifdef notyet 457 const struct evcnt * 458 sio_intr_evcnt(v, irq) 459 void *v; 460 int irq; 461 { 462 463 if (irq == 0 || irq >= ICU_LEN || irq == 2) 464 panic("sio_intr_evcnt: bogus isa irq 0x%x\n", irq); 465 466 return (alpha_shared_intr_evcnt(sio_intr, irq)); 467 } 468 #endif 469 470 void * 471 sio_intr_establish(v, irq, type, level, fn, arg, name) 472 void *v, *arg; 473 int irq; 474 int type; 475 int level; 476 int (*fn)(void *); 477 char *name; 478 { 479 void *cookie; 480 481 if (irq > ICU_LEN || type == IST_NONE) 482 panic("sio_intr_establish: bogus irq or type"); 483 484 cookie = alpha_shared_intr_establish(sio_intr, irq, type, level, fn, 485 arg, name); 486 487 if (cookie) 488 sio_setirqstat(irq, alpha_shared_intr_isactive(sio_intr, irq), 489 alpha_shared_intr_get_sharetype(sio_intr, irq)); 490 491 return (cookie); 492 } 493 494 void 495 sio_intr_disestablish(v, cookie) 496 void *v; 497 void *cookie; 498 { 499 struct alpha_shared_intrhand *ih = cookie; 500 int s, ist, irq = ih->ih_num; 501 502 s = splhigh(); 503 504 /* Remove it from the link. */ 505 alpha_shared_intr_disestablish(sio_intr, cookie, "isa irq"); 506 507 /* 508 * Decide if we should disable the interrupt. We must ensure 509 * that: 510 * 511 * - An initially-enabled interrupt is never disabled. 512 * - An initially-LT interrupt is never untyped. 513 */ 514 if (alpha_shared_intr_isactive(sio_intr, irq) == 0) { 515 /* 516 * IRQs 0, 1, 8, and 13 must always be edge-triggered 517 * (see setup). 518 */ 519 switch (irq) { 520 case 0: 521 case 1: 522 case 8: 523 case 13: 524 /* 525 * If the interrupt was initially level-triggered 526 * a warning was printed in setup. 527 */ 528 ist = IST_EDGE; 529 break; 530 531 default: 532 ist = IST_NONE; 533 break; 534 } 535 sio_setirqstat(irq, 0, ist); 536 alpha_shared_intr_set_dfltsharetype(sio_intr, irq, ist); 537 } 538 539 splx(s); 540 } 541 542 void 543 sio_iointr(framep, vec) 544 void *framep; 545 unsigned long vec; 546 { 547 int irq; 548 549 irq = (vec - 0x800) >> 4; 550 #ifdef DIAGNOSTIC 551 if (irq > ICU_LEN || irq < 0) 552 panic("sio_iointr: irq out of range (%d)", irq); 553 #endif 554 555 if (!alpha_shared_intr_dispatch(sio_intr, irq)) 556 alpha_shared_intr_stray(sio_intr, irq, "isa irq"); 557 558 /* 559 * Some versions of the machines which use the SIO 560 * (or is it some PALcode revisions on those machines?) 561 * require the non-specific EOI to be fed to the PIC(s) 562 * by the interrupt handler. 563 */ 564 specific_eoi(irq); 565 } 566 567 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 568 569 int 570 sio_intr_alloc(v, mask, type, irq) 571 void *v; 572 int mask; 573 int type; 574 int *irq; 575 { 576 int i, tmp, bestirq, count; 577 struct alpha_shared_intrhand **p, *q; 578 579 if (type == IST_NONE) 580 panic("intr_alloc: bogus type"); 581 582 bestirq = -1; 583 count = -1; 584 585 /* some interrupts should never be dynamically allocated */ 586 mask &= 0xdef8; 587 588 /* 589 * XXX some interrupts will be used later (6 for fdc, 12 for pms). 590 * the right answer is to do "breadth-first" searching of devices. 591 */ 592 mask &= 0xefbf; 593 594 for (i = 0; i < ICU_LEN; i++) { 595 if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0) 596 continue; 597 598 switch(sio_intr[i].intr_sharetype) { 599 case IST_NONE: 600 /* 601 * if nothing's using the irq, just return it 602 */ 603 *irq = i; 604 return (0); 605 606 case IST_EDGE: 607 case IST_LEVEL: 608 if (type != sio_intr[i].intr_sharetype) 609 continue; 610 /* 611 * if the irq is shareable, count the number of other 612 * handlers, and if it's smaller than the last irq like 613 * this, remember it 614 * 615 * XXX We should probably also consider the 616 * interrupt level and stick IPL_TTY with other 617 * IPL_TTY, etc. 618 */ 619 for (p = &TAILQ_FIRST(&sio_intr[i].intr_q), tmp = 0; 620 (q = *p) != NULL; p = &TAILQ_NEXT(q, ih_q), tmp++) 621 ; 622 if ((bestirq == -1) || (count > tmp)) { 623 bestirq = i; 624 count = tmp; 625 } 626 break; 627 628 case IST_PULSE: 629 /* this just isn't shareable */ 630 continue; 631 } 632 } 633 634 if (bestirq == -1) 635 return (1); 636 637 *irq = bestirq; 638 639 return (0); 640 } 641 642 static void 643 specific_eoi(irq) 644 int irq; 645 { 646 if (irq > 7) 647 bus_space_write_1(sio_iot, 648 sio_ioh_icu2, 0, 0x20 | (irq & 0x07)); /* XXX */ 649 bus_space_write_1(sio_iot, sio_ioh_icu1, 0, 0x20 | (irq > 7 ? 2 : irq)); 650 } 651