1/* $OpenBSD: prom_swpal.S,v 1.3 1996/10/30 22:40:45 niklas Exp $ */ 2/* $NetBSD: prom_swpal.S,v 1.4 1996/10/17 02:50:41 cgd Exp $ */ 3 4/* 5 * Copyright (c) 1994, 1995 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Author: Keith Bostic 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31#include "../../include/asm.h" 32#include "../../include/prom.h" 33#include "../../include/rpb.h" 34 35/* Offsets from base of HWRPB. */ 36#define RPB_SELFREF 0x00 37#define RPB_SLOTSIZE 0x98 38#define RPB_PERCPU_OFF 0xA0 39 40/* Offsets in a boot PCB. */ 41#define PCB_KSP 0x00 42#define PCB_PTBR 0x10 43#define PCB_ASN 0x1c 44#define PCB_FEN 0x28 45 46/* Pal values. */ 47#define PAL_RESERVED 0 /* Reserved to Digital. */ 48#define PAL_VMS 1 /* VMS */ 49#define PAL_OSF 2 /* OSF */ 50 51/* 52 * PAL code switch routine. 53 */ 54#define D_RA (7*8) 55#define D_S0 (8*8) 56#define D_S1 (9*8) 57#define D_S2 (10*8) 58#define D_S3 (11*8) 59#define D_S4 (12*8) 60#define D_S5 (13*8) 61#define PALSW_FRAME_SIZE (14*8) 62#define PALSW_REGS IM_RA|IM_S0|IM_S1|IM_S2|IM_S3|IM_S4|IM_S5 63 64 .comm ptbr_save,8 65 66 .text 67 .align 4 68 69NESTED(switch_palcode, 0, PALSW_FRAME_SIZE, ra, PALSW_REGS, 0) 70 LDGP(pv) 71/* ldgp gp, 0(pv)*/ 72 73 lda sp, -PALSW_FRAME_SIZE(sp) 74 stq ra, D_RA(sp) 75 stq s0, D_S0(sp) 76 stq s1, D_S1(sp) 77 stq s2, D_S2(sp) 78 stq s3, D_S3(sp) 79 stq s4, D_S4(sp) 80 stq s5, D_S5(sp) 81 82 stq pv, 0(sp) 83 stq gp, 8(sp) 84 85 ldiq s0, HWRPB_ADDR /* s0 HWRPB_ADDR */ 86 ldq s1, RPB_SLOTSIZE(s0) 87 call_pal PAL_VMS_mfpr_whami 88 mulq s1, v0, s1 /* s1 per_cpu offset from base */ 89 ldq s2, RPB_PERCPU_OFF(s0) 90 addq s0, s2, s2 91 addq s2, s1, s2 /* s2 PCB (virtual) */ 92 93 call_pal PAL_VMS_mfpr_ptbr 94 stq v0, PCB_PTBR(s2) 95 stq v0, ptbr_save /* save PTBR for the kernel */ 96 stl zero, PCB_ASN(s2) 97 stq zero, PCB_FEN(s2) 98 stq sp, PCB_KSP(s2) 99 100 ldq t0, RPB_SELFREF(s0) /* HWRBP base (physical) */ 101 ldq t1, RPB_PERCPU_OFF(s0) 102 addq t0, t1, t0 103 addq t0, s1, t0 /* PCB base (phys) */ 104 stq t0, 16(sp) 105 106 call_pal PAL_VMS_mfpr_vptb 107 mov v0, a3 108 ldiq a0, PAL_OSF 109 lda a1, contin 110 ldq a2, 16(sp) 111 112 call_pal PAL_swppal /* a0, a1, a2, a3 */ 113 114contin: ldq pv, 0(sp) 115 ldq gp, 8(sp) 116 117 ldq ra, D_RA(sp) 118 ldq s0, D_S0(sp) 119 ldq s1, D_S1(sp) 120 ldq s2, D_S2(sp) 121 ldq s3, D_S3(sp) 122 ldq s4, D_S4(sp) 123 ldq s5, D_S5(sp) 124 lda sp, PALSW_FRAME_SIZE(sp) 125 RET 126END(switch_palcode) 127 128#undef D_RA 129#undef D_S0 130#undef D_S1 131#undef D_S2 132#undef D_S3 133#undef D_S4 134#undef D_S5 135#undef PALSW_FRAME_SIZE 136#undef PALSW_REGS 137