1 /* $OpenBSD: tc_3000_500.c,v 1.19 2015/05/19 20:28:14 miod Exp $ */ 2 /* $NetBSD: tc_3000_500.c,v 1.24 2001/07/27 00:25:21 thorpej Exp $ */ 3 4 /* 5 * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. 6 * All rights reserved. 7 * 8 * Author: Chris G. Demetriou 9 * 10 * Permission to use, copy, modify and distribute this software and 11 * its documentation is hereby granted, provided that both the copyright 12 * notice and this permission notice appear in all copies of the 13 * software, derivative works or modified versions, and any portions 14 * thereof, and that both notices appear in supporting documentation. 15 * 16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 18 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 19 * 20 * Carnegie Mellon requests users of this software to return to 21 * 22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 23 * School of Computer Science 24 * Carnegie Mellon University 25 * Pittsburgh PA 15213-3890 26 * 27 * any improvements or extensions that they make and grant Carnegie the 28 * rights to redistribute these changes. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 #include <sys/malloc.h> 35 36 #include <machine/autoconf.h> 37 #include <machine/pte.h> 38 #include <machine/rpb.h> 39 40 #include <dev/tc/tcvar.h> 41 #include <alpha/tc/tc_conf.h> 42 #include <alpha/tc/tc_3000_500.h> 43 44 #include "wsdisplay.h" 45 #include "sfb.h" 46 47 #if NSFB > 0 48 extern int sfb_cnattach(tc_addr_t); 49 #endif 50 51 int tc_3000_500_intrnull(void *); 52 int tc_3000_500_fb_cnattach(u_int64_t); 53 54 #define C(x) ((void *)(u_long)x) 55 #define KV(x) (ALPHA_PHYS_TO_K0SEG(x)) 56 57 struct tc_slotdesc tc_3000_500_slots[] = { 58 { KV(0x100000000), C(TC_3000_500_DEV_OPT0), }, /* 0 - opt slot 0 */ 59 { KV(0x120000000), C(TC_3000_500_DEV_OPT1), }, /* 1 - opt slot 1 */ 60 { KV(0x140000000), C(TC_3000_500_DEV_OPT2), }, /* 2 - opt slot 2 */ 61 { KV(0x160000000), C(TC_3000_500_DEV_OPT3), }, /* 3 - opt slot 3 */ 62 { KV(0x180000000), C(TC_3000_500_DEV_OPT4), }, /* 4 - opt slot 4 */ 63 { KV(0x1a0000000), C(TC_3000_500_DEV_OPT5), }, /* 5 - opt slot 5 */ 64 { KV(0x1c0000000), C(TC_3000_500_DEV_BOGUS), }, /* 6 - TCDS ASIC */ 65 { KV(0x1e0000000), C(TC_3000_500_DEV_BOGUS), }, /* 7 - IOCTL ASIC */ 66 }; 67 int tc_3000_500_nslots = 68 sizeof(tc_3000_500_slots) / sizeof(tc_3000_500_slots[0]); 69 70 struct tc_builtin tc_3000_500_graphics_builtins[] = { 71 { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), }, 72 { "PMAGB-BA", 7, 0x02000000, C(TC_3000_500_DEV_CXTURBO), }, 73 { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), }, 74 }; 75 int tc_3000_500_graphics_nbuiltins = sizeof(tc_3000_500_graphics_builtins) / 76 sizeof(tc_3000_500_graphics_builtins[0]); 77 78 struct tc_builtin tc_3000_500_nographics_builtins[] = { 79 { "FLAMG-IO", 7, 0x00000000, C(TC_3000_500_DEV_IOASIC), }, 80 { "PMAZ-DS ", 6, 0x00000000, C(TC_3000_500_DEV_TCDS), }, 81 }; 82 int tc_3000_500_nographics_nbuiltins = sizeof(tc_3000_500_nographics_builtins) / 83 sizeof(tc_3000_500_nographics_builtins[0]); 84 85 u_int32_t tc_3000_500_intrbits[TC_3000_500_NCOOKIES] = { 86 TC_3000_500_IR_OPT0, 87 TC_3000_500_IR_OPT1, 88 TC_3000_500_IR_OPT2, 89 TC_3000_500_IR_OPT3, 90 TC_3000_500_IR_OPT4, 91 TC_3000_500_IR_OPT5, 92 TC_3000_500_IR_TCDS, 93 TC_3000_500_IR_IOASIC, 94 TC_3000_500_IR_CXTURBO, 95 }; 96 97 struct tcintr { 98 int (*tci_func)(void *); 99 void *tci_arg; 100 int tci_level; 101 struct evcount tci_count; 102 } tc_3000_500_intr[TC_3000_500_NCOOKIES]; 103 104 u_int32_t tc_3000_500_imask; /* intrs we want to ignore; mirrors IMR. */ 105 106 void 107 tc_3000_500_intr_setup() 108 { 109 u_long i; 110 111 /* 112 * Disable all slot interrupts. Note that this cannot 113 * actually disable CXTurbo, TCDS, and IOASIC interrupts. 114 */ 115 tc_3000_500_imask = *(volatile u_int32_t *)TC_3000_500_IMR_READ; 116 for (i = 0; i < TC_3000_500_NCOOKIES; i++) 117 tc_3000_500_imask |= tc_3000_500_intrbits[i]; 118 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 119 tc_mb(); 120 121 /* 122 * Set up interrupt handlers. 123 */ 124 for (i = 0; i < TC_3000_500_NCOOKIES; i++) { 125 tc_3000_500_intr[i].tci_func = tc_3000_500_intrnull; 126 tc_3000_500_intr[i].tci_arg = (void *)i; 127 tc_3000_500_intr[i].tci_level = IPL_HIGH; 128 } 129 } 130 131 void 132 tc_3000_500_intr_establish(tcadev, cookie, level, func, arg, name) 133 struct device *tcadev; 134 void *cookie, *arg; 135 int level; 136 int (*func)(void *); 137 const char *name; 138 { 139 u_long dev = (u_long)cookie; 140 141 #ifdef DIAGNOSTIC 142 /* XXX bounds-check cookie. */ 143 #endif 144 145 if (tc_3000_500_intr[dev].tci_func != tc_3000_500_intrnull) 146 panic("tc_3000_500_intr_establish: cookie %lu twice", dev); 147 148 tc_3000_500_intr[dev].tci_func = func; 149 tc_3000_500_intr[dev].tci_arg = arg; 150 tc_3000_500_intr[dev].tci_level = level; 151 if (name != NULL) 152 evcount_attach(&tc_3000_500_intr[dev].tci_count, name, NULL); 153 154 tc_3000_500_imask &= ~tc_3000_500_intrbits[dev]; 155 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 156 tc_mb(); 157 } 158 159 void 160 tc_3000_500_intr_disestablish(tcadev, cookie, name) 161 struct device *tcadev; 162 void *cookie; 163 const char *name; 164 { 165 u_long dev = (u_long)cookie; 166 167 #ifdef DIAGNOSTIC 168 /* XXX bounds-check cookie. */ 169 #endif 170 171 if (tc_3000_500_intr[dev].tci_func == tc_3000_500_intrnull) 172 panic("tc_3000_500_intr_disestablish: cookie %lu bad intr", 173 dev); 174 175 tc_3000_500_imask |= tc_3000_500_intrbits[dev]; 176 *(volatile u_int32_t *)TC_3000_500_IMR_WRITE = tc_3000_500_imask; 177 tc_mb(); 178 179 tc_3000_500_intr[dev].tci_func = tc_3000_500_intrnull; 180 tc_3000_500_intr[dev].tci_arg = (void *)dev; 181 tc_3000_500_intr[dev].tci_level = IPL_HIGH; 182 if (name != NULL) 183 evcount_detach(&tc_3000_500_intr[dev].tci_count); 184 } 185 186 int 187 tc_3000_500_intrnull(val) 188 void *val; 189 { 190 191 panic("tc_3000_500_intrnull: uncaught TC intr for cookie %ld", 192 (u_long)val); 193 } 194 195 void 196 tc_3000_500_iointr(arg, vec) 197 void *arg; 198 unsigned long vec; 199 { 200 u_int32_t ir; 201 int ifound; 202 203 do { 204 tc_syncbus(); 205 ir = *(volatile u_int32_t *)TC_3000_500_IR_CLEAR; 206 207 /* Ignore interrupts that we haven't enabled. */ 208 ir &= ~(tc_3000_500_imask & 0x1ff); 209 210 ifound = 0; 211 212 #ifdef MULTIPROCESSOR 213 #define INTRLOCK(slot) \ 214 if (tc_3000_500_intr[slot].tci_level < IPL_CLOCK) \ 215 __mp_lock(&kernel_lock) 216 #define INTRUNLOCK(slot) \ 217 if (tc_3000_500_intr[slot].tci_level < IPL_CLOCK) \ 218 __mp_unlock(&kernel_lock) 219 #else 220 #define INTRLOCK(slot) do { } while (0) 221 #define INTRUNLOCK(slot) do { } while (0) 222 #endif 223 #define CHECKINTR(slot) \ 224 if (ir & tc_3000_500_intrbits[slot]) { \ 225 ifound = 1; \ 226 INTRLOCK(slot); \ 227 (*tc_3000_500_intr[slot].tci_func) \ 228 (tc_3000_500_intr[slot].tci_arg); \ 229 tc_3000_500_intr[slot].tci_count.ec_count++; \ 230 INTRUNLOCK(slot); \ 231 } 232 233 /* Do them in order of priority; highest slot # first. */ 234 CHECKINTR(TC_3000_500_DEV_CXTURBO); 235 CHECKINTR(TC_3000_500_DEV_IOASIC); 236 CHECKINTR(TC_3000_500_DEV_TCDS); 237 CHECKINTR(TC_3000_500_DEV_OPT5); 238 CHECKINTR(TC_3000_500_DEV_OPT4); 239 CHECKINTR(TC_3000_500_DEV_OPT3); 240 CHECKINTR(TC_3000_500_DEV_OPT2); 241 CHECKINTR(TC_3000_500_DEV_OPT1); 242 CHECKINTR(TC_3000_500_DEV_OPT0); 243 244 #undef INTRUNLOCK 245 #undef INTRLOCK 246 #undef CHECKINTR 247 248 #ifdef DIAGNOSTIC 249 #define PRINTINTR(msg, bits) \ 250 if (ir & bits) \ 251 printf(msg); 252 253 PRINTINTR("Second error occurred\n", TC_3000_500_IR_ERR2); 254 PRINTINTR("DMA buffer error\n", TC_3000_500_IR_DMABE); 255 PRINTINTR("DMA cross 2K boundary\n", TC_3000_500_IR_DMA2K); 256 PRINTINTR("TC reset in progress\n", TC_3000_500_IR_TCRESET); 257 PRINTINTR("TC parity error\n", TC_3000_500_IR_TCPAR); 258 PRINTINTR("DMA tag error\n", TC_3000_500_IR_DMATAG); 259 PRINTINTR("Single-bit error\n", TC_3000_500_IR_DMASBE); 260 PRINTINTR("Double-bit error\n", TC_3000_500_IR_DMADBE); 261 PRINTINTR("TC I/O timeout\n", TC_3000_500_IR_TCTIMEOUT); 262 PRINTINTR("DMA block too long\n", TC_3000_500_IR_DMABLOCK); 263 PRINTINTR("Invalid I/O address\n", TC_3000_500_IR_IOADDR); 264 PRINTINTR("DMA scatter/gather invalid\n", TC_3000_500_IR_DMASG); 265 PRINTINTR("Scatter/gather parity error\n", 266 TC_3000_500_IR_SGPAR); 267 268 #undef PRINTINTR 269 #endif 270 } while (ifound); 271 } 272 273 #if NWSDISPLAY > 0 274 /* 275 * tc_3000_500_fb_cnattach -- 276 * Attempt to map the CTB output device to a slot and attach the 277 * framebuffer as the output side of the console. 278 */ 279 int 280 tc_3000_500_fb_cnattach(turbo_slot) 281 u_int64_t turbo_slot; 282 { 283 u_int32_t output_slot; 284 285 output_slot = turbo_slot & 0xffffffff; 286 287 if (output_slot >= tc_3000_500_nslots) { 288 return EINVAL; 289 } 290 291 if (hwrpb->rpb_variation & SV_GRAPHICS) { 292 if (output_slot == 0) { 293 #if NSFB > 0 294 sfb_cnattach(KV(0x1e0000000) + 0x02000000); 295 return 0; 296 #else 297 return ENXIO; 298 #endif 299 } 300 } else { 301 /* 302 * Slots 0-2 in the tc_3000_500_slots array are only 303 * on the 500 models that also have the CXTurbo 304 * (500/800/900) and a total of 6 TC slots. For the 305 * 400/600/700, slots 0-2 are in table locations 3-5, so 306 * offset the CTB slot by 3 to get the address in our table. 307 */ 308 output_slot += 3; 309 } 310 return tc_fb_cnattach(tc_3000_500_slots[output_slot-1].tcs_addr); 311 } 312 #endif /* NWSDISPLAY */ 313 314 #if 0 315 /* 316 * tc_3000_500_ioslot -- 317 * Set the PBS bits for devices on the TC. 318 */ 319 void 320 tc_3000_500_ioslot(slot, flags, set) 321 u_int32_t slot, flags; 322 int set; 323 { 324 volatile u_int32_t *iosp; 325 u_int32_t ios; 326 int s; 327 328 iosp = (volatile u_int32_t *)TC_3000_500_IOSLOT; 329 ios = *iosp; 330 flags <<= (slot * 3); 331 if (set) 332 ios |= flags; 333 else 334 ios &= ~flags; 335 s = splhigh(); 336 *iosp = ios; 337 tc_mb(); 338 splx(s); 339 } 340 #endif 341