xref: /openbsd/sys/arch/amd64/include/smbiosvar.h (revision f6aab3d8)
1 /*	$OpenBSD: smbiosvar.h,v 1.13 2021/03/11 11:16:55 jsg Exp $	*/
2 /*
3  * Copyright (c) 2006 Gordon Willem Klok <gklok@cogeco.ca>
4  * Copyright (c) 2005 Jordan Hargrave
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR
20  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #ifndef _MACHINE_SMBIOSVAR_
30 #define _MACHINE_SMBIOSVAR_
31 
32 #define SMBIOS_START			0xf0000
33 #define SMBIOS_END			0xfffff
34 
35 #define SMBIOS_UUID_NPRESENT		0x1
36 #define SMBIOS_UUID_NSET		0x2
37 
38 /*
39  * Section 3.5 of "UUIDs and GUIDs" found at
40  * http://www.opengroup.org/dce/info/draft-leach-uuids-guids-01.txt
41  * specifies the string representation of a UUID.
42  */
43 #define SMBIOS_UUID_REP "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x"
44 #define SMBIOS_UUID_REPLEN 37 /* 16 zero padded values, 4 hyphens, 1 null */
45 
46 struct smbios_entry {
47 	uint8_t		mjr;
48 	uint8_t		min;
49 	uint8_t		*addr;
50 	uint16_t	len;
51 	uint16_t	count;
52 };
53 
54 struct smbhdr {
55 	uint32_t	sig;		/* "_SM_" */
56 	uint8_t		checksum;	/* Entry point checksum */
57 	uint8_t		len;		/* Entry point structure length */
58 	uint8_t		majrev;		/* Specification major revision */
59 	uint8_t		minrev;		/* Specification minor revision */
60 	uint16_t	mss;		/* Maximum Structure Size */
61 	uint8_t		epr;		/* Entry Point Revision */
62 	uint8_t		fa[5];		/* value determined by EPR */
63 	uint8_t		sasig[5];	/* Secondary Anchor "_DMI_" */
64 	uint8_t		sachecksum;	/* Secondary Checksum */
65 	uint16_t	size;		/* Length of structure table in bytes */
66 	uint32_t	addr;		/* Structure table address */
67 	uint16_t	count;		/* Number of SMBIOS structures */
68 	uint8_t		rev;		/* BCD revision */
69 } __packed;
70 
71 struct smb3hdr {
72 	uint8_t		sig[5];		/* "_SM3_" */
73 	uint8_t		checksum;	/* Entry point structure checksum */
74 	uint8_t		len;		/* Entry point length */
75 	uint8_t		majrev;		/* SMBIOS major version */
76 	uint8_t		minrev;		/* SMBIOS minor version */
77 	uint8_t		docrev;		/* SMBIOS docrev */
78 	uint8_t		epr;		/* Entry point revision */
79 	uint8_t		reserved;	/* Reserved */
80 	uint32_t	size;		/* Structure table maximum size */
81 	uint64_t	addr;		/* Structure table address */
82 } __packed;
83 
84 struct smbtblhdr {
85 	uint8_t		type;
86 	uint8_t		size;
87 	uint16_t	handle;
88 } __packed;
89 
90 struct smbtable {
91 	struct smbtblhdr *hdr;
92 	void		 *tblhdr;
93 	uint32_t	 cookie;
94 };
95 
96 #define	SMBIOS_TYPE_BIOS		0
97 #define	SMBIOS_TYPE_SYSTEM		1
98 #define	SMBIOS_TYPE_BASEBOARD		2
99 #define	SMBIOS_TYPE_ENCLOSURE		3
100 #define	SMBIOS_TYPE_PROCESSOR		4
101 #define	SMBIOS_TYPE_MEMCTRL		5
102 #define	SMBIOS_TYPE_MEMMOD		6
103 #define	SMBIOS_TYPE_CACHE		7
104 #define	SMBIOS_TYPE_PORT		8
105 #define	SMBIOS_TYPE_SLOTS		9
106 #define	SMBIOS_TYPE_OBD			10
107 #define	SMBIOS_TYPE_OEM			11
108 #define	SMBIOS_TYPE_SYSCONFOPT		12
109 #define	SMBIOS_TYPE_BIOSLANG		13
110 #define	SMBIOS_TYPE_GROUPASSOC		14
111 #define	SMBIOS_TYPE_SYSEVENTLOG		15
112 #define	SMBIOS_TYPE_PHYMEM		16
113 #define	SMBIOS_TYPE_MEMDEV		17
114 #define	SMBIOS_TYPE_ECCINFO32		18
115 #define	SMBIOS_TYPE_MEMMAPARRAYADDR	19
116 #define	SMBIOS_TYPE_MEMMAPDEVADDR	20
117 #define	SMBIOS_TYPE_INBUILTPOINT	21
118 #define	SMBIOS_TYPE_PORTBATT		22
119 #define	SMBIOS_TYPE_SYSRESET		23
120 #define	SMBIOS_TYPE_HWSECUIRTY		24
121 #define	SMBIOS_TYPE_PWRCTRL		25
122 #define	SMBIOS_TYPE_VOLTPROBE		26
123 #define	SMBIOS_TYPE_COOLING		27
124 #define	SMBIOS_TYPE_TEMPPROBE		28
125 #define	SMBIOS_TYPE_CURRENTPROBE	29
126 #define	SMBIOS_TYPE_OOB_REMOTEACCESS	30
127 #define	SMBIOS_TYPE_BIS			31
128 #define	SMBIOS_TYPE_SBI			32
129 #define	SMBIOS_TYPE_ECCINFO64		33
130 #define	SMBIOS_TYPE_MGMTDEV		34
131 #define	SMBIOS_TYPE_MGTDEVCOMP		35
132 #define	SMBIOS_TYPE_MGTDEVTHRESH	36
133 #define	SMBIOS_TYPE_MEMCHANNEL		37
134 #define	SMBIOS_TYPE_IPMIDEV		38
135 #define	SMBIOS_TYPE_SPS			39
136 #define	SMBIOS_TYPE_INACTIVE		126
137 #define	SMBIOS_TYPE_EOT			127
138 
139 /*
140  * SMBIOS Structure Type 0 "BIOS Information"
141  * DMTF Specification DSP0134 Section: 3.3.1 p.g. 34
142  */
143 struct smbios_struct_bios {
144 	uint8_t		vendor;		/* string */
145 	uint8_t		version;	/* string */
146 	uint16_t	startaddr;
147 	uint8_t		release;	/* string */
148 	uint8_t		romsize;
149 	uint64_t	characteristics;
150 	uint32_t	charext;
151 	uint8_t		major_rel;
152 	uint8_t		minor_rel;
153 	uint8_t		ecf_mjr_rel;	/* embedded controller firmware */
154 	uint8_t		ecf_min_rel;	/* embedded controller firmware */
155 } __packed;
156 
157 /*
158  * SMBIOS Structure Type 1 "System Information"
159  * DMTF Specification DSP0134 Section 3.3.2 p.g. 35
160  */
161 
162 struct smbios_sys {
163 /* SMBIOS spec 2.0+ */
164 	uint8_t		vendor;		/* string */
165 	uint8_t		product;	/* string */
166 	uint8_t		version;	/* string */
167 	uint8_t		serial;		/* string */
168 /* SMBIOS spec 2.1+ */
169 	uint8_t		uuid[16];
170 	uint8_t		wakeup;
171 /* SMBIOS spec 2.4+ */
172 	uint8_t		sku;		/* string */
173 	uint8_t		family;		/* string */
174 } __packed;
175 
176 /*
177  * SMBIOS Structure Type 2 "Base Board (Module) Information"
178  * DMTF Specification DSP0134 Section 3.3.3 p.g. 37
179  */
180 struct smbios_board {
181 	uint8_t		vendor;		/* string */
182 	uint8_t		product;	/* string */
183 	uint8_t		version;	/* string */
184 	uint8_t		serial;		/* string */
185 	uint8_t		asset;		/* string */
186 	uint8_t		feature;	/* feature flags */
187 	uint8_t		location;	/* location in chassis */
188 	uint16_t	handle;		/* chassis handle */
189 	uint8_t		type;		/* board type */
190 	uint8_t		noc;		/* number of contained objects */
191 } __packed;
192 
193 /*
194  * SMBIOS Structure Type 3 "System Wnclosure or Chassis"
195  * DMTF Specification DSP0134
196  */
197 struct smbios_enclosure {
198 	/* SMBIOS spec  2.0+ */
199 	uint8_t		vendor;		/* string */
200 	uint8_t		type;
201 	uint8_t		version;	/* string */
202 	uint8_t		serial;		/* string */
203 	uint8_t		asset_tag;	/* string */
204 	/* SMBIOS spec  2.1+ */
205 	uint8_t		boot_state;
206 	uint8_t		psu_state;
207 	uint8_t		thermal_state;
208 	uint8_t		security_status;
209 	/* SMBIOS spec 2.3+ */
210 	uint16_t	oem_defined;
211 	uint8_t		height;
212 	uint8_t		no_power_cords;
213 	uint8_t		no_contained_element;
214 	uint8_t		reclen_contained_element;
215 	uint8_t		contained_elements;
216 	/* SMBIOS spec 2.7+ */
217 	uint8_t		sku;		/* string */
218 } __packed;
219 
220 /*
221  * SMBIOS Structure Type 4 "processor Information"
222  * DMTF Specification DSP0134 v2.5 Section 3.3.5 p.g. 24
223  */
224 struct smbios_cpu {
225 	uint8_t		cpu_socket_designation;	/* string */
226 	uint8_t		cpu_type;
227 	uint8_t		cpu_family;
228 	uint8_t		cpu_mfg;		/* string */
229 	uint32_t	cpu_id_eax;
230 	uint32_t	cpu_id_edx;
231 	uint8_t		cpu_version;		/* string */
232 	uint8_t		cpu_voltage;
233 	uint16_t	cpu_clock;
234 	uint16_t	cpu_max_speed;
235 	uint16_t	cpu_current_speed;
236 	uint8_t		cpu_status;
237 #define SMBIOS_CPUST_POPULATED			(1<<6)
238 #define SMBIOS_CPUST_STATUSMASK			(0x07)
239 	uint8_t		cpu_upgrade;
240 	uint16_t	cpu_l1_handle;
241 	uint16_t	cpu_l2_handle;
242 	uint16_t	cpu_l3_handle;
243 	uint8_t		cpu_serial;		/* string */
244 	uint8_t		cpu_asset_tag;		/* string */
245 	uint8_t		cpu_part_nr;		/* string */
246 	/* following fields were added in smbios 2.5 */
247 	uint8_t		cpu_core_count;
248 	uint8_t		cpu_core_enabled;
249 	uint8_t		cpu_thread_count;
250 	uint16_t	cpu_characteristics;
251 } __packed;
252 
253 /*
254  * SMBIOS Structure Type 38 "IPMI Information"
255  * DMTF Specification DSP0134 Section 3.3.39 p.g. 91
256  */
257 struct smbios_ipmi {
258 	uint8_t		smipmi_if_type;		/* IPMI Interface Type */
259 	uint8_t		smipmi_if_rev;		/* BCD IPMI Revision */
260 	uint8_t		smipmi_i2c_address;	/* I2C address of BMC */
261 	uint8_t		smipmi_nvram_address;	/* I2C address of NVRAM
262 						 * storage */
263 	uint64_t	smipmi_base_address;	/* Base address of BMC (BAR
264 						 * format */
265 	uint8_t		smipmi_base_flags;	/* Flags field:
266 						 * bit 7:6 : register spacing
267 						 *   00 = byte
268 						 *   01 = dword
269 						 *   02 = word
270 						 * bit 4 : Lower bit BAR
271 						 * bit 3 : IRQ valid
272 						 * bit 2 : N/A
273 						 * bit 1 : Interrupt polarity
274 						 * bit 0 : Interrupt trigger */
275 	uint8_t		smipmi_irq;		/* IRQ if applicable */
276 } __packed;
277 
278 int smbios_find_table(uint8_t, struct smbtable *);
279 char *smbios_get_string(struct smbtable *, uint8_t, char *, size_t);
280 
281 #endif
282