1 /* $OpenBSD: specialreg.h,v 1.90 2021/05/14 16:44:38 cheloha Exp $ */ 2 /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */ 3 /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */ 4 5 /*- 6 * Copyright (c) 1991 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the University nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 34 */ 35 36 /* 37 * Bits in 386 special registers: 38 */ 39 #define CR0_PE 0x00000001 /* Protected mode Enable */ 40 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 41 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 43 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 44 #define CR0_PG 0x80000000 /* PaGing enable */ 45 46 /* 47 * Bits in 486 special registers: 48 */ 49 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 50 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 52 #define CR0_NW 0x20000000 /* Not Write-through */ 53 #define CR0_CD 0x40000000 /* Cache Disable */ 54 55 /* 56 * Cyrix 486 DLC special registers, accessible as IO ports. 57 */ 58 #define CCR0 0xc0 /* configuration control register 0 */ 59 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 60 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 61 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 62 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 63 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 64 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 65 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 66 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 67 68 #define CCR1 0xc1 /* configuration control register 1 */ 69 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 70 /* the remaining 7 bits of this register are reserved */ 71 72 /* 73 * bits in CR3 74 */ 75 #define CR3_PCID 0xfffULL 76 #define CR3_PWT (1ULL << 3) 77 #define CR3_PCD (1ULL << 4) 78 #define CR3_REUSE_PCID (1ULL << 63) 79 #define CR3_PADDR 0x7ffffffffffff000ULL 80 81 /* 82 * bits in the pentiums %cr4 register: 83 */ 84 85 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 86 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 87 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */ 88 #define CR4_DE 0x00000008 /* debugging extension */ 89 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 90 #define CR4_PAE 0x00000020 /* physical address extension enable */ 91 #define CR4_MCE 0x00000040 /* machine check enable */ 92 #define CR4_PGE 0x00000080 /* page global enable */ 93 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 94 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 95 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 96 #define CR4_UMIP 0x00000800 /* user mode instruction prevention */ 97 #define CR4_VMXE 0x00002000 /* enable virtual machine operation */ 98 #define CR4_SMXE 0x00004000 /* enable safe mode operation */ 99 #define CR4_FSGSBASE 0x00010000 /* enable {RD,WR}{FS,GS}BASE ops */ 100 #define CR4_PCIDE 0x00020000 /* enable process-context IDs */ 101 #define CR4_OSXSAVE 0x00040000 /* enable XSAVE and extended states */ 102 #define CR4_SMEP 0x00100000 /* supervisor mode exec protection */ 103 #define CR4_SMAP 0x00200000 /* supervisor mode access prevention */ 104 #define CR4_PKE 0x00400000 /* protection key enable */ 105 106 /* 107 * Extended Control Register XCR0 108 */ 109 #define XCR0_X87 0x00000001 /* x87 FPU/MMX state */ 110 #define XCR0_SSE 0x00000002 /* SSE state */ 111 #define XCR0_AVX 0x00000004 /* AVX state */ 112 113 /* 114 * CPUID "features" bits (CPUID function 0x1): 115 * EDX bits, then ECX bits 116 */ 117 118 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 119 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 120 #define CPUID_DE 0x00000004 /* has debugging extension */ 121 #define CPUID_PSE 0x00000008 /* has 4MB page size extension */ 122 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 123 #define CPUID_MSR 0x00000020 /* has model specific registers */ 124 #define CPUID_PAE 0x00000040 /* has phys address extension */ 125 #define CPUID_MCE 0x00000080 /* has machine check exception */ 126 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 127 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 128 #define CPUID_SYS1 0x00000400 /* has SYSCALL/SYSRET inst. (Cyrix) */ 129 #define CPUID_SEP 0x00000800 /* has SYSCALL/SYSRET inst. (AMD/Intel) */ 130 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 131 #define CPUID_PGE 0x00002000 /* has page global extension */ 132 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 133 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 134 #define CPUID_PAT 0x00010000 /* has page attribute table */ 135 #define CPUID_PSE36 0x00020000 /* has 36bit page size extension */ 136 #define CPUID_PSN 0x00040000 /* has processor serial number */ 137 #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */ 138 #define CPUID_B20 0x00100000 /* reserved */ 139 #define CPUID_DS 0x00200000 /* Debug Store */ 140 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 141 #define CPUID_MMX 0x00800000 /* has MMX instructions */ 142 #define CPUID_FXSR 0x01000000 /* has FXRSTOR instruction */ 143 #define CPUID_SSE 0x02000000 /* has streaming SIMD extensions */ 144 #define CPUID_SSE2 0x04000000 /* has streaming SIMD extensions #2 */ 145 #define CPUID_SS 0x08000000 /* self-snoop */ 146 #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */ 147 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 148 #define CPUID_B30 0x40000000 /* reserved */ 149 #define CPUID_PBE 0x80000000 /* Pending Break Enabled restarts clock */ 150 151 #define CPUIDECX_SSE3 0x00000001 /* streaming SIMD extensions #3 */ 152 #define CPUIDECX_PCLMUL 0x00000002 /* Carryless Multiplication */ 153 #define CPUIDECX_DTES64 0x00000004 /* 64bit debug store */ 154 #define CPUIDECX_MWAIT 0x00000008 /* Monitor/Mwait */ 155 #define CPUIDECX_DSCPL 0x00000010 /* CPL Qualified Debug Store */ 156 #define CPUIDECX_VMX 0x00000020 /* Virtual Machine Extensions */ 157 #define CPUIDECX_SMX 0x00000040 /* Safer Mode Extensions */ 158 #define CPUIDECX_EST 0x00000080 /* enhanced SpeedStep */ 159 #define CPUIDECX_TM2 0x00000100 /* thermal monitor 2 */ 160 #define CPUIDECX_SSSE3 0x00000200 /* Supplemental Streaming SIMD Ext. 3 */ 161 #define CPUIDECX_CNXTID 0x00000400 /* Context ID */ 162 #define CPUIDECX_SDBG 0x00000800 /* Silicon debug capability */ 163 #define CPUIDECX_FMA3 0x00001000 /* Fused Multiply Add */ 164 #define CPUIDECX_CX16 0x00002000 /* has CMPXCHG16B instruction */ 165 #define CPUIDECX_XTPR 0x00004000 /* xTPR Update Control */ 166 #define CPUIDECX_PDCM 0x00008000 /* Perfmon and Debug Capability */ 167 #define CPUIDECX_PCID 0x00020000 /* Process-context ID Capability */ 168 #define CPUIDECX_DCA 0x00040000 /* Direct Cache Access */ 169 #define CPUIDECX_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */ 170 #define CPUIDECX_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */ 171 #define CPUIDECX_X2APIC 0x00200000 /* Extended xAPIC Support */ 172 #define CPUIDECX_MOVBE 0x00400000 /* MOVBE Instruction */ 173 #define CPUIDECX_POPCNT 0x00800000 /* POPCNT Instruction */ 174 #define CPUIDECX_DEADLINE 0x01000000 /* APIC one-shot via deadline */ 175 #define CPUIDECX_AES 0x02000000 /* AES Instruction */ 176 #define CPUIDECX_XSAVE 0x04000000 /* XSAVE/XSTOR States */ 177 #define CPUIDECX_OSXSAVE 0x08000000 /* OSXSAVE */ 178 #define CPUIDECX_AVX 0x10000000 /* Advanced Vector Extensions */ 179 #define CPUIDECX_F16C 0x20000000 /* 16bit fp conversion */ 180 #define CPUIDECX_RDRAND 0x40000000 /* RDRAND instruction */ 181 #define CPUIDECX_HV 0x80000000 /* Running on hypervisor */ 182 183 /* 184 * "Structured Extended Feature Flags Parameters" (CPUID function 0x7, leaf 0) 185 * EBX bits 186 */ 187 #define SEFF0EBX_FSGSBASE 0x00000001 /* {RD,WR}[FG]SBASE instructions */ 188 #define SEFF0EBX_TSC_ADJUST 0x00000002 /* Has IA32_TSC_ADJUST MSR */ 189 #define SEFF0EBX_SGX 0x00000004 /* Software Guard Extensions */ 190 #define SEFF0EBX_BMI1 0x00000008 /* advanced bit manipulation */ 191 #define SEFF0EBX_HLE 0x00000010 /* Hardware Lock Elision */ 192 #define SEFF0EBX_AVX2 0x00000020 /* Advanced Vector Extensions 2 */ 193 #define SEFF0EBX_SMEP 0x00000080 /* Supervisor mode exec protection */ 194 #define SEFF0EBX_BMI2 0x00000100 /* advanced bit manipulation */ 195 #define SEFF0EBX_ERMS 0x00000200 /* Enhanced REP MOVSB/STOSB */ 196 #define SEFF0EBX_INVPCID 0x00000400 /* INVPCID instruction */ 197 #define SEFF0EBX_RTM 0x00000800 /* Restricted Transactional Memory */ 198 #define SEFF0EBX_PQM 0x00001000 /* Quality of Service Monitoring */ 199 #define SEFF0EBX_MPX 0x00004000 /* Memory Protection Extensions */ 200 #define SEFF0EBX_AVX512F 0x00010000 /* AVX-512 foundation inst */ 201 #define SEFF0EBX_AVX512DQ 0x00020000 /* AVX-512 double/quadword */ 202 #define SEFF0EBX_RDSEED 0x00040000 /* RDSEED instruction */ 203 #define SEFF0EBX_ADX 0x00080000 /* ADCX/ADOX instructions */ 204 #define SEFF0EBX_SMAP 0x00100000 /* Supervisor mode access prevent */ 205 #define SEFF0EBX_AVX512IFMA 0x00200000 /* AVX-512 integer mult-add */ 206 #define SEFF0EBX_PCOMMIT 0x00400000 /* Persistent commit inst */ 207 #define SEFF0EBX_CLFLUSHOPT 0x00800000 /* cache line flush */ 208 #define SEFF0EBX_CLWB 0x01000000 /* cache line write back */ 209 #define SEFF0EBX_PT 0x02000000 /* Processor Trace */ 210 #define SEFF0EBX_AVX512PF 0x04000000 /* AVX-512 prefetch */ 211 #define SEFF0EBX_AVX512ER 0x08000000 /* AVX-512 exp/reciprocal */ 212 #define SEFF0EBX_AVX512CD 0x10000000 /* AVX-512 conflict detection */ 213 #define SEFF0EBX_SHA 0x20000000 /* SHA Extensions */ 214 #define SEFF0EBX_AVX512BW 0x40000000 /* AVX-512 byte/word inst */ 215 #define SEFF0EBX_AVX512VL 0x80000000 /* AVX-512 vector len inst */ 216 /* SEFF ECX bits */ 217 #define SEFF0ECX_PREFETCHWT1 0x00000001 /* PREFETCHWT1 instruction */ 218 #define SEFF0ECX_AVX512VBMI 0x00000002 /* AVX-512 vector bit inst */ 219 #define SEFF0ECX_UMIP 0x00000004 /* UMIP support */ 220 #define SEFF0ECX_PKU 0x00000008 /* Page prot keys for user mode */ 221 /* SEFF EDX bits */ 222 #define SEFF0EDX_AVX512_4FNNIW 0x00000004 /* AVX-512 neural network insns */ 223 #define SEFF0EDX_AVX512_4FMAPS 0x00000008 /* AVX-512 mult accum single prec */ 224 #define SEFF0EDX_SRBDS_CTRL 0x00000200 /* MCU_OPT_CTRL MSR */ 225 #define SEFF0EDX_MD_CLEAR 0x00000400 /* Microarch Data Clear */ 226 #define SEFF0EDX_TSXFA 0x00002000 /* TSX Forced Abort */ 227 #define SEFF0EDX_IBRS 0x04000000 /* IBRS / IBPB Speculation Control */ 228 #define SEFF0EDX_STIBP 0x08000000 /* STIBP Speculation Control */ 229 #define SEFF0EDX_L1DF 0x10000000 /* L1D_FLUSH */ 230 #define SEFF0EDX_ARCH_CAP 0x20000000 /* Has IA32_ARCH_CAPABILITIES MSR */ 231 #define SEFF0EDX_SSBD 0x80000000 /* Spec Store Bypass Disable */ 232 233 /* 234 * Thermal and Power Management (CPUID function 0x6) EAX bits 235 */ 236 #define TPM_SENSOR 0x00000001 /* Digital temp sensor */ 237 #define TPM_ARAT 0x00000004 /* APIC Timer Always Running */ 238 239 /* 240 * "Architectural Performance Monitoring" bits (CPUID function 0x0a): 241 * EAX bits, EBX bits, EDX bits. 242 */ 243 244 #define CPUIDEAX_VERID 0x000000ff /* Version ID */ 245 #define CPUIDEAX_NUM_GC(cpuid) (((cpuid) >> 8) & 0x000000ff) 246 #define CPUIDEAX_BIT_GC(cpuid) (((cpuid) >> 16) & 0x000000ff) 247 #define CPUIDEAX_LEN_EBX(cpuid) (((cpuid) >> 24) & 0x000000ff) 248 249 #define CPUIDEBX_EVT_CORE (1 << 0) /* Core cycle */ 250 #define CPUIDEBX_EVT_INST (1 << 1) /* Instruction retired */ 251 #define CPUIDEBX_EVT_REFR (1 << 2) /* Reference cycles */ 252 #define CPUIDEBX_EVT_CACHE_REF (1 << 3) /* Last-level cache ref. */ 253 #define CPUIDEBX_EVT_CACHE_MIS (1 << 4) /* Last-level cache miss. */ 254 #define CPUIDEBX_EVT_BRANCH_INST (1 << 5) /* Branch instruction ret. */ 255 #define CPUIDEBX_EVT_BRANCH_MISP (1 << 6) /* Branch mispredict ret. */ 256 257 #define CPUIDEDX_NUM_FC(cpuid) (((cpuid) >> 0) & 0x0000001f) 258 #define CPUIDEDX_BIT_FC(cpuid) (((cpuid) >> 5) & 0x000000ff) 259 260 /* 261 * CPUID "extended features" bits (CPUID function 0x80000001): 262 * EDX bits, then ECX bits 263 */ 264 265 #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */ 266 #define CPUID_NXE 0x00100000 /* No-Execute Extension */ 267 #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */ 268 #define CPUID_FFXSR 0x02000000 /* fast FP/MMX save/restore */ 269 #define CPUID_PAGE1GB 0x04000000 /* 1-GByte pages */ 270 #define CPUID_RDTSCP 0x08000000 /* RDTSCP / IA32_TSC_AUX available */ 271 #define CPUID_LONG 0x20000000 /* long mode */ 272 #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */ 273 #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */ 274 275 #define CPUIDECX_LAHF 0x00000001 /* LAHF and SAHF instructions */ 276 #define CPUIDECX_CMPLEG 0x00000002 /* Core MP legacy mode */ 277 #define CPUIDECX_SVM 0x00000004 /* Secure Virtual Machine */ 278 #define CPUIDECX_EAPICSP 0x00000008 /* Extended APIC space */ 279 #define CPUIDECX_AMCR8 0x00000010 /* LOCK MOV CR0 means MOV CR8 */ 280 #define CPUIDECX_ABM 0x00000020 /* LZCNT instruction */ 281 #define CPUIDECX_SSE4A 0x00000040 /* SSE4-A instruction set */ 282 #define CPUIDECX_MASSE 0x00000080 /* Misaligned SSE mode */ 283 #define CPUIDECX_3DNOWP 0x00000100 /* 3DNowPrefetch */ 284 #define CPUIDECX_OSVW 0x00000200 /* OS visible workaround */ 285 #define CPUIDECX_IBS 0x00000400 /* Instruction based sampling */ 286 #define CPUIDECX_XOP 0x00000800 /* Extended operating support */ 287 #define CPUIDECX_SKINIT 0x00001000 /* SKINIT and STGI are supported */ 288 #define CPUIDECX_WDT 0x00002000 /* Watchdog timer */ 289 /* Reserved 0x00004000 */ 290 #define CPUIDECX_LWP 0x00008000 /* Lightweight profiling support */ 291 #define CPUIDECX_FMA4 0x00010000 /* 4-operand FMA instructions */ 292 #define CPUIDECX_TCE 0x00020000 /* Translation Cache Extension */ 293 /* Reserved 0x00040000 */ 294 #define CPUIDECX_NODEID 0x00080000 /* Support for MSRC001C */ 295 /* Reserved 0x00100000 */ 296 #define CPUIDECX_TBM 0x00200000 /* Trailing bit manipulation instruction */ 297 #define CPUIDECX_TOPEXT 0x00400000 /* Topology extensions support */ 298 #define CPUIDECX_CPCTR 0x00800000 /* core performance counter ext */ 299 #define CPUIDECX_DBKP 0x04000000 /* DataBreakpointExtension */ 300 #define CPUIDECX_PERFTSC 0x08000000 /* performance time-stamp counter */ 301 #define CPUIDECX_PCTRL3 0x10000000 /* L3 performance counter ext */ 302 #define CPUIDECX_MWAITX 0x20000000 /* MWAITX/MONITORX */ 303 304 /* 305 * "Advanced Power Management Information" bits (CPUID function 0x80000007): 306 * EDX bits. 307 */ 308 #define CPUIDEDX_ITSC (1 << 8) /* Invariant TSC */ 309 310 /* 311 * AMD CPUID function 0x80000008 EBX bits 312 */ 313 #define CPUIDEBX_IBPB (1ULL << 12) /* Speculation Control IBPB */ 314 #define CPUIDEBX_IBRS (1ULL << 14) /* Speculation Control IBRS */ 315 #define CPUIDEBX_STIBP (1ULL << 15) /* Speculation Control STIBP */ 316 #define CPUIDEBX_IBRS_ALWAYSON (1ULL << 16) /* IBRS always on mode */ 317 #define CPUIDEBX_STIBP_ALWAYSON (1ULL << 17) /* STIBP always on mode */ 318 #define CPUIDEBX_IBRS_PREF (1ULL << 18) /* IBRS preferred */ 319 #define CPUIDEBX_SSBD (1ULL << 24) /* Speculation Control SSBD */ 320 #define CPUIDEBX_VIRT_SSBD (1ULL << 25) /* Virt Spec Control SSBD */ 321 #define CPUIDEBX_SSBD_NOTREQ (1ULL << 26) /* SSBD not required */ 322 323 #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 15) 324 #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 15) 325 #define CPUID2STEPPING(cpuid) ((cpuid) & 15) 326 327 #define CPUID(code, eax, ebx, ecx, edx) \ 328 __asm volatile("cpuid" \ 329 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \ 330 : "a" (code)); 331 #define CPUID_LEAF(code, leaf, eax, ebx, ecx, edx) \ 332 __asm volatile("cpuid" \ 333 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \ 334 : "a" (code), "c" (leaf)); 335 336 337 /* 338 * Model-specific registers for the i386 family 339 */ 340 #define MSR_P5_MC_ADDR 0x000 /* P5 only */ 341 #define MSR_P5_MC_TYPE 0x001 /* P5 only */ 342 #define MSR_TSC 0x010 343 #define MSR_CESR 0x011 /* P5 only (trap on P6) */ 344 #define MSR_CTR0 0x012 /* P5 only (trap on P6) */ 345 #define MSR_CTR1 0x013 /* P5 only (trap on P6) */ 346 #define MSR_PLATFORM_ID 0x017 /* Platform ID for microcode */ 347 #define MSR_APICBASE 0x01b 348 #define APICBASE_BSP 0x100 349 #define APICBASE_ENABLE_X2APIC 0x400 350 #define APICBASE_GLOBAL_ENABLE 0x800 351 #define MSR_EBL_CR_POWERON 0x02a 352 #define MSR_EBC_FREQUENCY_ID 0x02c /* Pentium 4 only */ 353 #define MSR_TEST_CTL 0x033 354 #define MSR_IA32_FEATURE_CONTROL 0x03a 355 #define MSR_TSC_ADJUST 0x03b 356 #define MSR_SPEC_CTRL 0x048 /* Speculation Control IBRS / STIBP */ 357 #define SPEC_CTRL_IBRS (1ULL << 0) 358 #define SPEC_CTRL_STIBP (1ULL << 1) 359 #define SPEC_CTRL_SSBD (1ULL << 2) 360 #define MSR_PRED_CMD 0x049 /* Speculation Control IBPB */ 361 #define PRED_CMD_IBPB (1ULL << 0) 362 #define MSR_BIOS_UPDT_TRIG 0x079 363 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ 364 #define MSR_BBL_CR_D1 0x089 /* PII+ only */ 365 #define MSR_BBL_CR_D2 0x08a /* PII+ only */ 366 #define MSR_BIOS_SIGN 0x08b 367 #define MSR_SMM_MONITOR_CTL 0x09b 368 #define MSR_SMBASE 0x09e 369 #define MSR_PERFCTR0 0x0c1 370 #define MSR_PERFCTR1 0x0c2 371 #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */ 372 #define MSR_MTRRcap 0x0fe 373 #define MTRRcap_FIXED 0x100 /* bit 8 - fixed MTRRs supported */ 374 #define MTRRcap_WC 0x400 /* bit 10 - WC type supported */ 375 #define MTRRcap_SMRR 0x800 /* bit 11 - SMM range reg supported */ 376 #define MSR_ARCH_CAPABILITIES 0x10a 377 #define ARCH_CAPABILITIES_RDCL_NO (1 << 0) /* Meltdown safe */ 378 #define ARCH_CAPABILITIES_IBRS_ALL (1 << 1) /* enhanced IBRS */ 379 #define ARCH_CAPABILITIES_RSBA (1 << 2) /* RSB Alternate */ 380 #define ARCH_CAPABILITIES_SKIP_L1DFL_VMENTRY (1 << 3) 381 #define ARCH_CAPABILITIES_SSB_NO (1 << 4) /* Spec St Byp safe */ 382 #define ARCH_CAPABILITIES_MDS_NO (1 << 5) /* microarch data-sampling */ 383 #define ARCH_CAPABILITIES_IF_PSCHANGE_MC_NO (1 << 6) /* PS MCE safe */ 384 #define ARCH_CAPABILITIES_TSX_CTRL (1 << 7) /* has TSX_CTRL MSR */ 385 #define ARCH_CAPABILITIES_TAA_NO (1 << 8) /* TSX AA safe */ 386 #define MSR_FLUSH_CMD 0x10b 387 #define FLUSH_CMD_L1D_FLUSH 0x1 /* (1ULL << 0) */ 388 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ 389 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ 390 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ 391 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ 392 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ 393 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ 394 #define MSR_TSX_CTRL 0x122 395 #define TSX_CTRL_RTM_DISABLE (1ULL << 0) 396 #define TSX_CTRL_TSX_CPUID_CLEAR (1ULL << 1) 397 #define MSR_MCU_OPT_CTRL 0x123 398 #define RNGDS_MITG_DIS (1ULL << 0) 399 #define MSR_SYSENTER_CS 0x174 /* PII+ only */ 400 #define MSR_SYSENTER_ESP 0x175 /* PII+ only */ 401 #define MSR_SYSENTER_EIP 0x176 /* PII+ only */ 402 #define MSR_MCG_CAP 0x179 403 #define MSR_MCG_STATUS 0x17a 404 #define MSR_MCG_CTL 0x17b 405 #define MSR_EVNTSEL0 0x186 406 #define MSR_EVNTSEL1 0x187 407 #define MSR_PERF_STATUS 0x198 /* Pentium M */ 408 #define MSR_PERF_CTL 0x199 /* Pentium M */ 409 #define PERF_CTL_TURBO 0x100000000ULL /* bit 32 - turbo mode */ 410 #define MSR_THERM_CONTROL 0x19a 411 #define MSR_THERM_INTERRUPT 0x19b 412 #define MSR_THERM_STATUS 0x19c 413 #define MSR_THERM_STATUS_VALID_BIT 0x80000000 414 #define MSR_THERM_STATUS_TEMP(msr) ((msr >> 16) & 0x7f) 415 #define MSR_THERM2_CTL 0x19d /* Pentium M */ 416 #define MSR_MISC_ENABLE 0x1a0 417 /* 418 * MSR_MISC_ENABLE (0x1a0) 419 * 420 * Enable Fast Strings: enables fast REP MOVS/REP STORS (R/W) 421 * Enable TCC: Enable automatic thermal control circuit (R/W) 422 * Performance monitoring available: 1 if enabled (R/O) 423 * Branch trace storage unavailable: 1 if unsupported (R/O) 424 * Processor event based sampling unavailable: 1 if unsupported (R/O) 425 * Enhanced Intel SpeedStep technology enable: 1 to enable (R/W) 426 * Enable monitor FSM: 1 to enable MONITOR/MWAIT (R/W) 427 * Limit CPUID maxval: 1 to limit CPUID leaf nodes to 0x2 and lower (R/W) 428 * Enable xTPR message disable: 1 to disable xTPR messages 429 * XD bit disable: 1 to disable NX capability (bit 34, or bit 2 of %edx/%rdx) 430 */ 431 #define MISC_ENABLE_FAST_STRINGS (1 << 0) 432 #define MISC_ENABLE_TCC (1 << 3) 433 #define MISC_ENABLE_PERF_MON_AVAILABLE (1 << 7) 434 #define MISC_ENABLE_BTS_UNAVAILABLE (1 << 11) 435 #define MISC_ENABLE_PEBS_UNAVAILABLE (1 << 12) 436 #define MISC_ENABLE_EIST_ENABLED (1 << 16) 437 #define MISC_ENABLE_ENABLE_MONITOR_FSM (1 << 18) 438 #define MISC_ENABLE_LIMIT_CPUID_MAXVAL (1 << 22) 439 #define MISC_ENABLE_xTPR_MESSAGE_DISABLE (1 << 23) 440 #define MISC_ENABLE_XD_BIT_DISABLE (1 << 2) 441 442 /* 443 * for Core i Series and newer Xeons, see 444 * http://www.intel.com/content/dam/www/public/us/en/ 445 * documents/white-papers/cpu-monitoring-dts-peci-paper.pdf 446 */ 447 #define MSR_TEMPERATURE_TARGET 0x1a2 /* Core i Series, Newer Xeons */ 448 #define MSR_TEMPERATURE_TARGET_TJMAX(msr) (((msr) >> 16) & 0xff) 449 /* 450 * not documented anywhere, see intelcore_update_sensor() 451 * only available Core Duo and Core Solo Processors 452 */ 453 #define MSR_TEMPERATURE_TARGET_UNDOCUMENTED 0x0ee 454 #define MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED 0x40000000 455 #define MSR_DEBUGCTLMSR 0x1d9 456 #define MSR_LASTBRANCHFROMIP 0x1db 457 #define MSR_LASTBRANCHTOIP 0x1dc 458 #define MSR_LASTINTFROMIP 0x1dd 459 #define MSR_LASTINTTOIP 0x1de 460 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 461 #define MSR_MTRRvarBase 0x200 462 #define MSR_MTRRfix64K_00000 0x250 463 #define MSR_MTRRfix16K_80000 0x258 464 #define MSR_MTRRfix4K_C0000 0x268 465 #define MSR_CR_PAT 0x277 466 #define MSR_MTRRdefType 0x2ff 467 #define MTRRdefType_FIXED_ENABLE 0x400 /* bit 10 - fixed MTRR enabled */ 468 #define MTRRdefType_ENABLE 0x800 /* bit 11 - MTRRs enabled */ 469 #define MSR_PERF_FIXED_CTR1 0x30a /* CPU_CLK_Unhalted.Core */ 470 #define MSR_PERF_FIXED_CTR2 0x30b /* CPU_CLK.Unhalted.Ref */ 471 #define MSR_PERF_FIXED_CTR_CTRL 0x38d 472 #define MSR_PERF_FIXED_CTR_FC_DIS 0x0 /* disable counter */ 473 #define MSR_PERF_FIXED_CTR_FC_1 0x1 /* count ring 1 */ 474 #define MSR_PERF_FIXED_CTR_FC_123 0x2 /* count rings 1,2,3 */ 475 #define MSR_PERF_FIXED_CTR_FC_ANY 0x3 /* count everything */ 476 #define MSR_PERF_FIXED_CTR_FC_MASK 0x3 477 #define MSR_PERF_FIXED_CTR_FC(_i, _v) ((_v) << (4 * (_i))) 478 #define MSR_PERF_FIXED_CTR_ANYTHR(_i) (0x4 << (4 * (_i))) 479 #define MSR_PERF_FIXED_CTR_INT(_i) (0x8 << (4 * (_i))) 480 #define MSR_PERF_GLOBAL_CTRL 0x38f 481 #define MSR_PERF_GLOBAL_CTR1_EN (1ULL << 33) 482 #define MSR_PERF_GLOBAL_CTR2_EN (1ULL << 34) 483 #define MSR_MC0_CTL 0x400 484 #define MSR_MC0_STATUS 0x401 485 #define MSR_MC0_ADDR 0x402 486 #define MSR_MC0_MISC 0x403 487 #define MSR_MC1_CTL 0x404 488 #define MSR_MC1_STATUS 0x405 489 #define MSR_MC1_ADDR 0x406 490 #define MSR_MC1_MISC 0x407 491 #define MSR_MC2_CTL 0x408 492 #define MSR_MC2_STATUS 0x409 493 #define MSR_MC2_ADDR 0x40a 494 #define MSR_MC2_MISC 0x40b 495 #define MSR_MC4_CTL 0x40c 496 #define MSR_MC4_STATUS 0x40d 497 #define MSR_MC4_ADDR 0x40e 498 #define MSR_MC4_MISC 0x40f 499 #define MSR_MC3_CTL 0x410 500 #define MSR_MC3_STATUS 0x411 501 #define MSR_MC3_ADDR 0x412 502 #define MSR_MC3_MISC 0x413 503 504 /* VIA MSR */ 505 #define MSR_CENT_TMTEMPERATURE 0x1423 /* Thermal monitor temperature */ 506 507 /* 508 * AMD K6/K7 MSRs. 509 */ 510 #define MSR_K6_UWCCR 0xc0000085 511 #define MSR_K7_EVNTSEL0 0xc0010000 512 #define MSR_K7_EVNTSEL1 0xc0010001 513 #define MSR_K7_EVNTSEL2 0xc0010002 514 #define MSR_K7_EVNTSEL3 0xc0010003 515 #define MSR_K7_PERFCTR0 0xc0010004 516 #define MSR_K7_PERFCTR1 0xc0010005 517 #define MSR_K7_PERFCTR2 0xc0010006 518 #define MSR_K7_PERFCTR3 0xc0010007 519 520 /* 521 * AMD K8 (Opteron) MSRs. 522 */ 523 #define MSR_PATCH_LEVEL 0x0000008b 524 #define MSR_SYSCFG 0xc0000010 525 526 #define MSR_EFER 0xc0000080 /* Extended feature enable */ 527 #define EFER_SCE 0x00000001 /* SYSCALL extension */ 528 #define EFER_LME 0x00000100 /* Long Mode Enabled */ 529 #define EFER_LMA 0x00000400 /* Long Mode Active */ 530 #define EFER_NXE 0x00000800 /* No-Execute Enabled */ 531 #define EFER_SVME 0x00001000 /* SVM Enabled */ 532 533 #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */ 534 #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */ 535 #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */ 536 #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */ 537 538 #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */ 539 #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */ 540 #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */ 541 #define MSR_PATCH_LOADER 0xc0010020 542 #define MSR_INT_PEN_MSG 0xc0010055 /* Interrupt pending message */ 543 544 #define MSR_DE_CFG 0xc0011029 /* Decode Configuration */ 545 #define DE_CFG_721 0x00000001 /* errata 721 */ 546 #define DE_CFG_SERIALIZE_LFENCE (1 << 1) /* Enable serializing lfence */ 547 548 #define IPM_C1E_CMP_HLT 0x10000000 549 #define IPM_SMI_CMP_HLT 0x08000000 550 551 /* 552 * These require a 'passcode' for access. See cpufunc.h. 553 */ 554 #define MSR_HWCR 0xc0010015 555 #define HWCR_FFDIS 0x00000040 556 557 #define MSR_NB_CFG 0xc001001f 558 #define NB_CFG_DISIOREQLOCK 0x0000000000000004ULL 559 #define NB_CFG_DISDATMSK 0x0000001000000000ULL 560 561 #define MSR_LS_CFG 0xc0011020 562 #define LS_CFG_DIS_LS2_SQUISH 0x02000000 563 564 #define MSR_IC_CFG 0xc0011021 565 #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800 566 567 #define MSR_DC_CFG 0xc0011022 568 #define DC_CFG_DIS_CNV_WC_SSO 0x00000004 569 #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400 570 571 #define MSR_BU_CFG 0xc0011023 572 #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL 573 #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL 574 #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL 575 576 /* 577 * Constants related to MTRRs 578 */ 579 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 580 #define MTRR_N16K 16 581 #define MTRR_N4K 64 582 583 /* 584 * the following four 3-byte registers control the non-cacheable regions. 585 * These registers must be written as three separate bytes. 586 * 587 * NCRx+0: A31-A24 of starting address 588 * NCRx+1: A23-A16 of starting address 589 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 590 * 591 * The non-cacheable region's starting address must be aligned to the 592 * size indicated by the NCR_SIZE_xx field. 593 */ 594 #define NCR1 0xc4 595 #define NCR2 0xc7 596 #define NCR3 0xca 597 #define NCR4 0xcd 598 599 #define NCR_SIZE_0K 0 600 #define NCR_SIZE_4K 1 601 #define NCR_SIZE_8K 2 602 #define NCR_SIZE_16K 3 603 #define NCR_SIZE_32K 4 604 #define NCR_SIZE_64K 5 605 #define NCR_SIZE_128K 6 606 #define NCR_SIZE_256K 7 607 #define NCR_SIZE_512K 8 608 #define NCR_SIZE_1M 9 609 #define NCR_SIZE_2M 10 610 #define NCR_SIZE_4M 11 611 #define NCR_SIZE_8M 12 612 #define NCR_SIZE_16M 13 613 #define NCR_SIZE_32M 14 614 #define NCR_SIZE_4G 15 615 616 /* 617 * Performance monitor events. 618 * 619 * Note that 586-class and 686-class CPUs have different performance 620 * monitors available, and they are accessed differently: 621 * 622 * 686-class: `rdpmc' instruction 623 * 586-class: `rdmsr' instruction, CESR MSR 624 * 625 * The descriptions of these events are too lengthy to include here. 626 * See Appendix A of "Intel Architecture Software Developer's 627 * Manual, Volume 3: System Programming" for more information. 628 */ 629 630 /* 631 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 632 * is CTR1. 633 */ 634 635 #define PMC5_CESR_EVENT 0x003f 636 #define PMC5_CESR_OS 0x0040 637 #define PMC5_CESR_USR 0x0080 638 #define PMC5_CESR_E 0x0100 639 #define PMC5_CESR_P 0x0200 640 641 #define PMC5_DATA_READ 0x00 642 #define PMC5_DATA_WRITE 0x01 643 #define PMC5_DATA_TLB_MISS 0x02 644 #define PMC5_DATA_READ_MISS 0x03 645 #define PMC5_DATA_WRITE_MISS 0x04 646 #define PMC5_WRITE_M_E 0x05 647 #define PMC5_DATA_LINES_WBACK 0x06 648 #define PMC5_DATA_CACHE_SNOOP 0x07 649 #define PMC5_DATA_CACHE_SNOOP_HIT 0x08 650 #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09 651 #define PMC5_BANK_CONFLICTS 0x0a 652 #define PMC5_MISALIGNED_DATA 0x0b 653 #define PMC5_INST_READ 0x0c 654 #define PMC5_INST_TLB_MISS 0x0d 655 #define PMC5_INST_CACHE_MISS 0x0e 656 #define PMC5_SEGMENT_REG_LOAD 0x0f 657 #define PMC5_BRANCHES 0x12 658 #define PMC5_BTB_HITS 0x13 659 #define PMC5_BRANCH_TAKEN 0x14 660 #define PMC5_PIPELINE_FLUSH 0x15 661 #define PMC5_INST_EXECUTED 0x16 662 #define PMC5_INST_EXECUTED_V_PIPE 0x17 663 #define PMC5_BUS_UTILIZATION 0x18 664 #define PMC5_WRITE_BACKUP_STALL 0x19 665 #define PMC5_DATA_READ_STALL 0x1a 666 #define PMC5_WRITE_E_M_STALL 0x1b 667 #define PMC5_LOCKED_BUS 0x1c 668 #define PMC5_IO_CYCLE 0x1d 669 #define PMC5_NONCACHE_MEM_READ 0x1e 670 #define PMC5_AGI_STALL 0x1f 671 #define PMC5_FLOPS 0x22 672 #define PMC5_BP0_MATCH 0x23 673 #define PMC5_BP1_MATCH 0x24 674 #define PMC5_BP2_MATCH 0x25 675 #define PMC5_BP3_MATCH 0x26 676 #define PMC5_HARDWARE_INTR 0x27 677 #define PMC5_DATA_RW 0x28 678 #define PMC5_DATA_RW_MISS 0x29 679 680 /* 681 * 686-class Event Selector MSR format. 682 */ 683 684 #define PMC6_EVTSEL_EVENT 0x000000ff 685 #define PMC6_EVTSEL_UNIT 0x0000ff00 686 #define PMC6_EVTSEL_UNIT_SHIFT 8 687 #define PMC6_EVTSEL_USR (1 << 16) 688 #define PMC6_EVTSEL_OS (1 << 17) 689 #define PMC6_EVTSEL_E (1 << 18) 690 #define PMC6_EVTSEL_PC (1 << 19) 691 #define PMC6_EVTSEL_INT (1 << 20) 692 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 693 #define PMC6_EVTSEL_INV (1 << 23) 694 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 695 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 696 697 /* Data Cache Unit */ 698 #define PMC6_DATA_MEM_REFS 0x43 699 #define PMC6_DCU_LINES_IN 0x45 700 #define PMC6_DCU_M_LINES_IN 0x46 701 #define PMC6_DCU_M_LINES_OUT 0x47 702 #define PMC6_DCU_MISS_OUTSTANDING 0x48 703 704 /* Instruction Fetch Unit */ 705 #define PMC6_IFU_IFETCH 0x80 706 #define PMC6_IFU_IFETCH_MISS 0x81 707 #define PMC6_ITLB_MISS 0x85 708 #define PMC6_IFU_MEM_STALL 0x86 709 #define PMC6_ILD_STALL 0x87 710 711 /* L2 Cache */ 712 #define PMC6_L2_IFETCH 0x28 713 #define PMC6_L2_LD 0x29 714 #define PMC6_L2_ST 0x2a 715 #define PMC6_L2_LINES_IN 0x24 716 #define PMC6_L2_LINES_OUT 0x26 717 #define PMC6_L2_M_LINES_INM 0x25 718 #define PMC6_L2_M_LINES_OUTM 0x27 719 #define PMC6_L2_RQSTS 0x2e 720 #define PMC6_L2_ADS 0x21 721 #define PMC6_L2_DBUS_BUSY 0x22 722 #define PMC6_L2_DBUS_BUSY_RD 0x23 723 724 /* External Bus Logic */ 725 #define PMC6_BUS_DRDY_CLOCKS 0x62 726 #define PMC6_BUS_LOCK_CLOCKS 0x63 727 #define PMC6_BUS_REQ_OUTSTANDING 0x60 728 #define PMC6_BUS_TRAN_BRD 0x65 729 #define PMC6_BUS_TRAN_RFO 0x66 730 #define PMC6_BUS_TRANS_WB 0x67 731 #define PMC6_BUS_TRAN_IFETCH 0x68 732 #define PMC6_BUS_TRAN_INVAL 0x69 733 #define PMC6_BUS_TRAN_PWR 0x6a 734 #define PMC6_BUS_TRANS_P 0x6b 735 #define PMC6_BUS_TRANS_IO 0x6c 736 #define PMC6_BUS_TRAN_DEF 0x6d 737 #define PMC6_BUS_TRAN_BURST 0x6e 738 #define PMC6_BUS_TRAN_ANY 0x70 739 #define PMC6_BUS_TRAN_MEM 0x6f 740 #define PMC6_BUS_DATA_RCV 0x64 741 #define PMC6_BUS_BNR_DRV 0x61 742 #define PMC6_BUS_HIT_DRV 0x7a 743 #define PMC6_BUS_HITM_DRDV 0x7b 744 #define PMC6_BUS_SNOOP_STALL 0x7e 745 746 /* Floating Point Unit */ 747 #define PMC6_FLOPS 0xc1 748 #define PMC6_FP_COMP_OPS_EXE 0x10 749 #define PMC6_FP_ASSIST 0x11 750 #define PMC6_MUL 0x12 751 #define PMC6_DIV 0x12 752 #define PMC6_CYCLES_DIV_BUSY 0x14 753 754 /* Memory Ordering */ 755 #define PMC6_LD_BLOCKS 0x03 756 #define PMC6_SB_DRAINS 0x04 757 #define PMC6_MISALIGN_MEM_REF 0x05 758 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 759 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 760 761 /* Instruction Decoding and Retirement */ 762 #define PMC6_INST_RETIRED 0xc0 763 #define PMC6_UOPS_RETIRED 0xc2 764 #define PMC6_INST_DECODED 0xd0 765 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 766 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 767 768 /* Interrupts */ 769 #define PMC6_HW_INT_RX 0xc8 770 #define PMC6_CYCLES_INT_MASKED 0xc6 771 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 772 773 /* Branches */ 774 #define PMC6_BR_INST_RETIRED 0xc4 775 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 776 #define PMC6_BR_TAKEN_RETIRED 0xc9 777 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 778 #define PMC6_BR_INST_DECODED 0xe0 779 #define PMC6_BTB_MISSES 0xe2 780 #define PMC6_BR_BOGUS 0xe4 781 #define PMC6_BACLEARS 0xe6 782 783 /* Stalls */ 784 #define PMC6_RESOURCE_STALLS 0xa2 785 #define PMC6_PARTIAL_RAT_STALLS 0xd2 786 787 /* Segment Register Loads */ 788 #define PMC6_SEGMENT_REG_LOADS 0x06 789 790 /* Clocks */ 791 #define PMC6_CPU_CLK_UNHALTED 0x79 792 793 /* MMX Unit */ 794 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 795 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 796 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 797 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 798 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 799 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 800 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 801 802 /* Segment Register Renaming */ 803 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 804 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 805 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 806 807 /* 808 * AMD K7 Event Selector MSR format. 809 */ 810 811 #define K7_EVTSEL_EVENT 0x000000ff 812 #define K7_EVTSEL_UNIT 0x0000ff00 813 #define K7_EVTSEL_UNIT_SHIFT 8 814 #define K7_EVTSEL_USR (1 << 16) 815 #define K7_EVTSEL_OS (1 << 17) 816 #define K7_EVTSEL_E (1 << 18) 817 #define K7_EVTSEL_PC (1 << 19) 818 #define K7_EVTSEL_INT (1 << 20) 819 #define K7_EVTSEL_EN (1 << 22) 820 #define K7_EVTSEL_INV (1 << 23) 821 #define K7_EVTSEL_COUNTER_MASK 0xff000000 822 #define K7_EVTSEL_COUNTER_MASK_SHIFT 24 823 824 /* Segment Register Loads */ 825 #define K7_SEGMENT_REG_LOADS 0x20 826 827 #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21 828 829 /* Data Cache Unit */ 830 #define K7_DATA_CACHE_ACCESS 0x40 831 #define K7_DATA_CACHE_MISS 0x41 832 #define K7_DATA_CACHE_REFILL 0x42 833 #define K7_DATA_CACHE_REFILL_SYSTEM 0x43 834 #define K7_DATA_CACHE_WBACK 0x44 835 #define K7_L2_DTLB_HIT 0x45 836 #define K7_L2_DTLB_MISS 0x46 837 #define K7_MISALIGNED_DATA_REF 0x47 838 #define K7_SYSTEM_REQUEST 0x64 839 #define K7_SYSTEM_REQUEST_TYPE 0x65 840 841 #define K7_SNOOP_HIT 0x73 842 #define K7_SINGLE_BIT_ECC_ERROR 0x74 843 #define K7_CACHE_LINE_INVAL 0x75 844 #define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76 845 #define K7_L2_REQUEST 0x79 846 #define K7_L2_REQUEST_BUSY 0x7a 847 848 /* Instruction Fetch Unit */ 849 #define K7_IFU_IFETCH 0x80 850 #define K7_IFU_IFETCH_MISS 0x81 851 #define K7_IFU_REFILL_FROM_L2 0x82 852 #define K7_IFU_REFILL_FROM_SYSTEM 0x83 853 #define K7_ITLB_L1_MISS 0x84 854 #define K7_ITLB_L2_MISS 0x85 855 #define K7_SNOOP_RESYNC 0x86 856 #define K7_IFU_STALL 0x87 857 858 #define K7_RETURN_STACK_HITS 0x88 859 #define K7_RETURN_STACK_OVERFLOW 0x89 860 861 /* Retired */ 862 #define K7_RETIRED_INST 0xc0 863 #define K7_RETIRED_OPS 0xc1 864 #define K7_RETIRED_BRANCHES 0xc2 865 #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3 866 #define K7_RETIRED_TAKEN_BRANCH 0xc4 867 #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5 868 #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6 869 #define K7_RETIRED_RESYNC_BRANCH 0xc7 870 #define K7_RETIRED_NEAR_RETURNS 0xc8 871 #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9 872 #define K7_RETIRED_INDIRECT_MISPREDICTED 0xca 873 874 /* Interrupts */ 875 #define K7_CYCLES_INT_MASKED 0xcd 876 #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce 877 #define K7_HW_INTR_RECV 0xcf 878 879 #define K7_INSTRUCTION_DECODER_EMPTY 0xd0 880 #define K7_DISPATCH_STALLS 0xd1 881 #define K7_BRANCH_ABORTS_TO_RETIRE 0xd2 882 #define K7_SERIALIZE 0xd3 883 #define K7_SEGMENT_LOAD_STALL 0xd4 884 #define K7_ICU_FULL 0xd5 885 #define K7_RESERVATION_STATIONS_FULL 0xd6 886 #define K7_FPU_FULL 0xd7 887 #define K7_LS_FULL 0xd8 888 #define K7_ALL_QUIET_STALL 0xd9 889 #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda 890 891 #define K7_BP0_MATCH 0xdc 892 #define K7_BP1_MATCH 0xdd 893 #define K7_BP2_MATCH 0xde 894 #define K7_BP3_MATCH 0xdf 895 896 /* VIA C3 crypto featureset: for amd64_has_xcrypt */ 897 #define C3_HAS_AES 1 /* cpu has AES */ 898 #define C3_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 899 #define C3_HAS_MM 4 /* cpu has RSA instructions */ 900 #define C3_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 901 902 /* Centaur Extended Feature flags */ 903 #define C3_CPUID_HAS_RNG 0x000004 904 #define C3_CPUID_DO_RNG 0x000008 905 #define C3_CPUID_HAS_ACE 0x000040 906 #define C3_CPUID_DO_ACE 0x000080 907 #define C3_CPUID_HAS_ACE2 0x000100 908 #define C3_CPUID_DO_ACE2 0x000200 909 #define C3_CPUID_HAS_PHE 0x000400 910 #define C3_CPUID_DO_PHE 0x000800 911 #define C3_CPUID_HAS_PMM 0x001000 912 #define C3_CPUID_DO_PMM 0x002000 913 914 /* VIA C3 xcrypt-* instruction context control options */ 915 #define C3_CRYPT_CWLO_ROUND_M 0x0000000f 916 #define C3_CRYPT_CWLO_ALG_M 0x00000070 917 #define C3_CRYPT_CWLO_ALG_AES 0x00000000 918 #define C3_CRYPT_CWLO_KEYGEN_M 0x00000080 919 #define C3_CRYPT_CWLO_KEYGEN_HW 0x00000000 920 #define C3_CRYPT_CWLO_KEYGEN_SW 0x00000080 921 #define C3_CRYPT_CWLO_NORMAL 0x00000000 922 #define C3_CRYPT_CWLO_INTERMEDIATE 0x00000100 923 #define C3_CRYPT_CWLO_ENCRYPT 0x00000000 924 #define C3_CRYPT_CWLO_DECRYPT 0x00000200 925 #define C3_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 926 #define C3_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 927 #define C3_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 928 929 /* Intel Silicon Debug */ 930 #define IA32_DEBUG_INTERFACE 0xc80 931 #define IA32_DEBUG_INTERFACE_ENABLE 0x00000001 932 #define IA32_DEBUG_INTERFACE_LOCK 0x40000000 933 #define IA32_DEBUG_INTERFACE_MASK 0x80000000 934 935 /* 936 * VMX 937 */ 938 #define IA32_FEATURE_CONTROL_LOCK 0x01 939 #define IA32_FEATURE_CONTROL_SMX_EN 0x02 940 #define IA32_FEATURE_CONTROL_VMX_EN 0x04 941 #define IA32_FEATURE_CONTROL_SENTER_EN (1ULL << 15) 942 #define IA32_FEATURE_CONTROL_SENTER_PARAM_MASK 0x7f00 943 #define IA32_VMX_BASIC 0x480 944 #define IA32_VMX_PINBASED_CTLS 0x481 945 #define IA32_VMX_PROCBASED_CTLS 0x482 946 #define IA32_VMX_EXIT_CTLS 0x483 947 #define IA32_VMX_ENTRY_CTLS 0x484 948 #define IA32_VMX_MISC 0x485 949 #define IA32_VMX_CR0_FIXED0 0x486 950 #define IA32_VMX_CR0_FIXED1 0x487 951 #define IA32_VMX_CR4_FIXED0 0x488 952 #define IA32_VMX_CR4_FIXED1 0x489 953 #define IA32_VMX_PROCBASED2_CTLS 0x48B 954 #define IA32_VMX_EPT_VPID_CAP 0x48C 955 #define IA32_VMX_TRUE_PINBASED_CTLS 0x48D 956 #define IA32_VMX_TRUE_PROCBASED_CTLS 0x48E 957 #define IA32_VMX_TRUE_EXIT_CTLS 0x48F 958 #define IA32_VMX_TRUE_ENTRY_CTLS 0x490 959 #define IA32_VMX_VMFUNC 0x491 960 961 #define IA32_EPT_VPID_CAP_XO_TRANSLATIONS (1ULL << 0) 962 #define IA32_EPT_VPID_CAP_PAGE_WALK_4 (1ULL << 6) 963 #define IA32_EPT_VPID_CAP_WB (1ULL << 14) 964 #define IA32_EPT_VPID_CAP_AD_BITS (1ULL << 21) 965 966 #define IA32_EPT_PAGING_CACHE_TYPE_UC 0x0 967 #define IA32_EPT_PAGING_CACHE_TYPE_WB 0x6 968 #define IA32_EPT_AD_BITS_ENABLE (1ULL << 6) 969 #define IA32_EPT_PAGE_WALK_LENGTH 0x4 970 971 /* VMX : IA32_VMX_BASIC bits */ 972 #define IA32_VMX_TRUE_CTLS_AVAIL (1ULL << 55) 973 974 /* VMX : IA32_VMX_PINBASED_CTLS bits */ 975 #define IA32_VMX_EXTERNAL_INT_EXITING (1ULL << 0) 976 #define IA32_VMX_NMI_EXITING (1ULL << 3) 977 #define IA32_VMX_VIRTUAL_NMIS (1ULL << 5) 978 #define IA32_VMX_ACTIVATE_VMX_PREEMPTION_TIMER (1ULL << 6) 979 #define IA32_VMX_PROCESS_POSTED_INTERRUPTS (1ULL << 7) 980 981 /* VMX : IA32_VMX_PROCBASED_CTLS bits */ 982 #define IA32_VMX_INTERRUPT_WINDOW_EXITING (1ULL << 2) 983 #define IA32_VMX_USE_TSC_OFFSETTING (1ULL << 3) 984 #define IA32_VMX_HLT_EXITING (1ULL << 7) 985 #define IA32_VMX_INVLPG_EXITING (1ULL << 9) 986 #define IA32_VMX_MWAIT_EXITING (1ULL << 10) 987 #define IA32_VMX_RDPMC_EXITING (1ULL << 11) 988 #define IA32_VMX_RDTSC_EXITING (1ULL << 12) 989 #define IA32_VMX_CR3_LOAD_EXITING (1ULL << 15) 990 #define IA32_VMX_CR3_STORE_EXITING (1ULL << 16) 991 #define IA32_VMX_CR8_LOAD_EXITING (1ULL << 19) 992 #define IA32_VMX_CR8_STORE_EXITING (1ULL << 20) 993 #define IA32_VMX_USE_TPR_SHADOW (1ULL << 21) 994 #define IA32_VMX_NMI_WINDOW_EXITING (1ULL << 22) 995 #define IA32_VMX_MOV_DR_EXITING (1ULL << 23) 996 #define IA32_VMX_UNCONDITIONAL_IO_EXITING (1ULL << 24) 997 #define IA32_VMX_USE_IO_BITMAPS (1ULL << 25) 998 #define IA32_VMX_MONITOR_TRAP_FLAG (1ULL << 27) 999 #define IA32_VMX_USE_MSR_BITMAPS (1ULL << 28) 1000 #define IA32_VMX_MONITOR_EXITING (1ULL << 29) 1001 #define IA32_VMX_PAUSE_EXITING (1ULL << 30) 1002 #define IA32_VMX_ACTIVATE_SECONDARY_CONTROLS (1ULL << 31) 1003 1004 /* VMX : IA32_VMX_PROCBASED2_CTLS bits */ 1005 #define IA32_VMX_VIRTUALIZE_APIC (1ULL << 0) 1006 #define IA32_VMX_ENABLE_EPT (1ULL << 1) 1007 #define IA32_VMX_DESCRIPTOR_TABLE_EXITING (1ULL << 2) 1008 #define IA32_VMX_ENABLE_RDTSCP (1ULL << 3) 1009 #define IA32_VMX_VIRTUALIZE_X2APIC_MODE (1ULL << 4) 1010 #define IA32_VMX_ENABLE_VPID (1ULL << 5) 1011 #define IA32_VMX_WBINVD_EXITING (1ULL << 6) 1012 #define IA32_VMX_UNRESTRICTED_GUEST (1ULL << 7) 1013 #define IA32_VMX_APIC_REGISTER_VIRTUALIZATION (1ULL << 8) 1014 #define IA32_VMX_VIRTUAL_INTERRUPT_DELIVERY (1ULL << 9) 1015 #define IA32_VMX_PAUSE_LOOP_EXITING (1ULL << 10) 1016 #define IA32_VMX_RDRAND_EXITING (1ULL << 11) 1017 #define IA32_VMX_ENABLE_INVPCID (1ULL << 12) 1018 #define IA32_VMX_ENABLE_VM_FUNCTIONS (1ULL << 13) 1019 #define IA32_VMX_VMCS_SHADOWING (1ULL << 14) 1020 #define IA32_VMX_ENABLE_ENCLS_EXITING (1ULL << 15) 1021 #define IA32_VMX_RDSEED_EXITING (1ULL << 16) 1022 #define IA32_VMX_ENABLE_PML (1ULL << 17) 1023 #define IA32_VMX_EPT_VIOLATION_VE (1ULL << 18) 1024 #define IA32_VMX_CONCEAL_VMX_FROM_PT (1ULL << 19) 1025 #define IA32_VMX_ENABLE_XSAVES_XRSTORS (1ULL << 20) 1026 #define IA32_VMX_ENABLE_TSC_SCALING (1ULL << 25) 1027 1028 /* VMX : IA32_VMX_EXIT_CTLS bits */ 1029 #define IA32_VMX_SAVE_DEBUG_CONTROLS (1ULL << 2) 1030 #define IA32_VMX_HOST_SPACE_ADDRESS_SIZE (1ULL << 9) 1031 #define IA32_VMX_LOAD_IA32_PERF_GLOBAL_CTRL_ON_EXIT (1ULL << 12) 1032 #define IA32_VMX_ACKNOWLEDGE_INTERRUPT_ON_EXIT (1ULL << 15) 1033 #define IA32_VMX_SAVE_IA32_PAT_ON_EXIT (1ULL << 18) 1034 #define IA32_VMX_LOAD_IA32_PAT_ON_EXIT (1ULL << 19) 1035 #define IA32_VMX_SAVE_IA32_EFER_ON_EXIT (1ULL << 20) 1036 #define IA32_VMX_LOAD_IA32_EFER_ON_EXIT (1ULL << 21) 1037 #define IA32_VMX_SAVE_VMX_PREEMPTION_TIMER (1ULL << 22) 1038 #define IA32_VMX_CLEAR_IA32_BNDCFGS_ON_EXIT (1ULL << 23) 1039 #define IA32_VMX_CONCEAL_VM_EXITS_FROM_PT (1ULL << 24) 1040 1041 /* VMX: IA32_VMX_ENTRY_CTLS bits */ 1042 #define IA32_VMX_LOAD_DEBUG_CONTROLS (1ULL << 2) 1043 #define IA32_VMX_IA32E_MODE_GUEST (1ULL << 9) 1044 #define IA32_VMX_ENTRY_TO_SMM (1ULL << 10) 1045 #define IA32_VMX_DEACTIVATE_DUAL_MONITOR_TREATMENT (1ULL << 11) 1046 #define IA32_VMX_LOAD_IA32_PERF_GLOBAL_CTRL_ON_ENTRY (1ULL << 13) 1047 #define IA32_VMX_LOAD_IA32_PAT_ON_ENTRY (1ULL << 14) 1048 #define IA32_VMX_LOAD_IA32_EFER_ON_ENTRY (1ULL << 15) 1049 #define IA32_VMX_LOAD_IA32_BNDCFGS_ON_ENTRY (1ULL << 16) 1050 #define IA32_VMX_CONCEAL_VM_ENTRIES_FROM_PT (1ULL << 17) 1051 1052 /* 1053 * VMX : VMCS Fields 1054 */ 1055 1056 /* 16-bit control fields */ 1057 #define VMCS_GUEST_VPID 0x0000 1058 #define VMCS_POSTED_INT_NOTIF_VECTOR 0x0002 1059 #define VMCS_EPTP_INDEX 0x0004 1060 1061 /* 16-bit guest state fields */ 1062 #define VMCS_GUEST_IA32_ES_SEL 0x0800 1063 #define VMCS_GUEST_IA32_CS_SEL 0x0802 1064 #define VMCS_GUEST_IA32_SS_SEL 0x0804 1065 #define VMCS_GUEST_IA32_DS_SEL 0x0806 1066 #define VMCS_GUEST_IA32_FS_SEL 0x0808 1067 #define VMCS_GUEST_IA32_GS_SEL 0x080A 1068 #define VMCS_GUEST_IA32_LDTR_SEL 0x080C 1069 #define VMCS_GUEST_IA32_TR_SEL 0x080E 1070 #define VMCS_GUEST_INTERRUPT_STATUS 0x0810 1071 #define VMCS_GUEST_PML_INDEX 0x0812 1072 1073 /* 16-bit host state fields */ 1074 #define VMCS_HOST_IA32_ES_SEL 0x0C00 1075 #define VMCS_HOST_IA32_CS_SEL 0x0C02 1076 #define VMCS_HOST_IA32_SS_SEL 0x0C04 1077 #define VMCS_HOST_IA32_DS_SEL 0x0C06 1078 #define VMCS_HOST_IA32_FS_SEL 0x0C08 1079 #define VMCS_HOST_IA32_GS_SEL 0x0C0A 1080 #define VMCS_HOST_IA32_TR_SEL 0x0C0C 1081 1082 /* 64-bit control fields */ 1083 #define VMCS_IO_BITMAP_A 0x2000 1084 #define VMCS_IO_BITMAP_B 0x2002 1085 #define VMCS_MSR_BITMAP_ADDRESS 0x2004 1086 #define VMCS_EXIT_STORE_MSR_ADDRESS 0x2006 1087 #define VMCS_EXIT_LOAD_MSR_ADDRESS 0x2008 1088 #define VMCS_ENTRY_LOAD_MSR_ADDRESS 0x200A 1089 #define VMCS_EXECUTIVE_VMCS_POINTER 0x200C 1090 #define VMCS_PML_ADDRESS 0x200E 1091 #define VMCS_TSC_OFFSET 0x2010 1092 #define VMCS_VIRTUAL_APIC_ADDRESS 0x2012 1093 #define VMCS_APIC_ACCESS_ADDRESS 0x2014 1094 #define VMCS_POSTED_INTERRUPT_DESC 0x2016 1095 #define VMCS_VM_FUNCTION_CONTROLS 0x2018 1096 #define VMCS_GUEST_IA32_EPTP 0x201A 1097 #define VMCS_EOI_EXIT_BITMAP_0 0x201C 1098 #define VMCS_EOI_EXIT_BITMAP_1 0x201E 1099 #define VMCS_EOI_EXIT_BITMAP_2 0x2020 1100 #define VMCS_EOI_EXIT_BITMAP_3 0x2022 1101 #define VMCS_EPTP_LIST_ADDRESS 0x2024 1102 #define VMCS_VMREAD_BITMAP_ADDRESS 0x2026 1103 #define VMCS_VMWRITE_BITMAP_ADDRESS 0x2028 1104 #define VMCS_VIRTUALIZATION_EXC_ADDRESS 0x202A 1105 #define VMCS_XSS_EXITING_BITMAP 0x202C 1106 #define VMCS_ENCLS_EXITING_BITMAP 0x202E 1107 #define VMCS_TSC_MULTIPLIER 0x2032 1108 1109 /* 64-bit RO data field */ 1110 #define VMCS_GUEST_PHYSICAL_ADDRESS 0x2400 1111 1112 /* 64-bit guest state fields */ 1113 #define VMCS_LINK_POINTER 0x2800 1114 #define VMCS_GUEST_IA32_DEBUGCTL 0x2802 1115 #define VMCS_GUEST_IA32_PAT 0x2804 1116 #define VMCS_GUEST_IA32_EFER 0x2806 1117 #define VMCS_GUEST_IA32_PERF_GBL_CTRL 0x2808 1118 #define VMCS_GUEST_PDPTE0 0x280A 1119 #define VMCS_GUEST_PDPTE1 0x280C 1120 #define VMCS_GUEST_PDPTE2 0x280E 1121 #define VMCS_GUEST_PDPTE3 0x2810 1122 #define VMCS_GUEST_IA32_BNDCFGS 0x2812 1123 1124 /* 64-bit host state fields */ 1125 #define VMCS_HOST_IA32_PAT 0x2C00 1126 #define VMCS_HOST_IA32_EFER 0x2C02 1127 #define VMCS_HOST_IA32_PERF_GBL_CTRL 0x2C04 1128 1129 /* 32-bit control fields */ 1130 #define VMCS_PINBASED_CTLS 0x4000 1131 #define VMCS_PROCBASED_CTLS 0x4002 1132 #define VMCS_EXCEPTION_BITMAP 0x4004 1133 #define VMCS_PF_ERROR_CODE_MASK 0x4006 1134 #define VMCS_PF_ERROR_CODE_MATCH 0x4008 1135 #define VMCS_CR3_TARGET_COUNT 0x400A 1136 #define VMCS_EXIT_CTLS 0x400C 1137 #define VMCS_EXIT_MSR_STORE_COUNT 0x400E 1138 #define VMCS_EXIT_MSR_LOAD_COUNT 0x4010 1139 #define VMCS_ENTRY_CTLS 0x4012 1140 #define VMCS_ENTRY_MSR_LOAD_COUNT 0x4014 1141 #define VMCS_ENTRY_INTERRUPTION_INFO 0x4016 1142 #define VMCS_ENTRY_EXCEPTION_ERROR_CODE 0x4018 1143 #define VMCS_ENTRY_INSTRUCTION_LENGTH 0x401A 1144 #define VMCS_TPR_THRESHOLD 0x401C 1145 #define VMCS_PROCBASED2_CTLS 0x401E 1146 #define VMCS_PLE_GAP 0x4020 1147 #define VMCS_PLE_WINDOW 0x4022 1148 1149 /* 32-bit RO data fields */ 1150 #define VMCS_INSTRUCTION_ERROR 0x4400 1151 #define VMCS_EXIT_REASON 0x4402 1152 #define VMCS_EXIT_INTERRUPTION_INFO 0x4404 1153 #define VMCS_EXIT_INTERRUPTION_ERR_CODE 0x4406 1154 #define VMCS_IDT_VECTORING_INFO 0x4408 1155 #define VMCS_IDT_VECTORING_ERROR_CODE 0x440A 1156 #define VMCS_INSTRUCTION_LENGTH 0x440C 1157 #define VMCS_EXIT_INSTRUCTION_INFO 0x440E 1158 1159 /* 32-bit guest state fields */ 1160 #define VMCS_GUEST_IA32_ES_LIMIT 0x4800 1161 #define VMCS_GUEST_IA32_CS_LIMIT 0x4802 1162 #define VMCS_GUEST_IA32_SS_LIMIT 0x4804 1163 #define VMCS_GUEST_IA32_DS_LIMIT 0x4806 1164 #define VMCS_GUEST_IA32_FS_LIMIT 0x4808 1165 #define VMCS_GUEST_IA32_GS_LIMIT 0x480A 1166 #define VMCS_GUEST_IA32_LDTR_LIMIT 0x480C 1167 #define VMCS_GUEST_IA32_TR_LIMIT 0x480E 1168 #define VMCS_GUEST_IA32_GDTR_LIMIT 0x4810 1169 #define VMCS_GUEST_IA32_IDTR_LIMIT 0x4812 1170 #define VMCS_GUEST_IA32_ES_AR 0x4814 1171 #define VMCS_GUEST_IA32_CS_AR 0x4816 1172 #define VMCS_GUEST_IA32_SS_AR 0x4818 1173 #define VMCS_GUEST_IA32_DS_AR 0x481A 1174 #define VMCS_GUEST_IA32_FS_AR 0x481C 1175 #define VMCS_GUEST_IA32_GS_AR 0x481E 1176 #define VMCS_GUEST_IA32_LDTR_AR 0x4820 1177 #define VMCS_GUEST_IA32_TR_AR 0x4822 1178 #define VMCS_GUEST_INTERRUPTIBILITY_ST 0x4824 1179 #define VMCS_GUEST_ACTIVITY_STATE 0x4826 1180 #define VMCS_GUEST_SMBASE 0x4828 1181 #define VMCS_GUEST_IA32_SYSENTER_CS 0x482A 1182 #define VMCS_VMX_PREEMPTION_TIMER_VAL 0x482E 1183 1184 /* 32-bit host state field */ 1185 #define VMCS_HOST_IA32_SYSENTER_CS 0x4C00 1186 1187 /* Natural-width control fields */ 1188 #define VMCS_CR0_MASK 0x6000 1189 #define VMCS_CR4_MASK 0x6002 1190 #define VMCS_CR0_READ_SHADOW 0x6004 1191 #define VMCS_CR4_READ_SHADOW 0x6006 1192 #define VMCS_CR3_TARGET_0 0x6008 1193 #define VMCS_CR3_TARGET_1 0x600A 1194 #define VMCS_CR3_TARGET_2 0x600C 1195 #define VMCS_CR3_TARGET_3 0x600E 1196 1197 /* Natural-width RO fields */ 1198 #define VMCS_GUEST_EXIT_QUALIFICATION 0x6400 1199 #define VMCS_IO_RCX 0x6402 1200 #define VMCS_IO_RSI 0x6404 1201 #define VMCS_IO_RDI 0x6406 1202 #define VMCS_IO_RIP 0x6408 1203 #define VMCS_GUEST_LINEAR_ADDRESS 0x640A 1204 1205 /* Natural-width guest state fields */ 1206 #define VMCS_GUEST_IA32_CR0 0x6800 1207 #define VMCS_GUEST_IA32_CR3 0x6802 1208 #define VMCS_GUEST_IA32_CR4 0x6804 1209 #define VMCS_GUEST_IA32_ES_BASE 0x6806 1210 #define VMCS_GUEST_IA32_CS_BASE 0x6808 1211 #define VMCS_GUEST_IA32_SS_BASE 0x680A 1212 #define VMCS_GUEST_IA32_DS_BASE 0x680C 1213 #define VMCS_GUEST_IA32_FS_BASE 0x680E 1214 #define VMCS_GUEST_IA32_GS_BASE 0x6810 1215 #define VMCS_GUEST_IA32_LDTR_BASE 0x6812 1216 #define VMCS_GUEST_IA32_TR_BASE 0x6814 1217 #define VMCS_GUEST_IA32_GDTR_BASE 0x6816 1218 #define VMCS_GUEST_IA32_IDTR_BASE 0x6818 1219 #define VMCS_GUEST_IA32_DR7 0x681A 1220 #define VMCS_GUEST_IA32_RSP 0x681C 1221 #define VMCS_GUEST_IA32_RIP 0x681E 1222 #define VMCS_GUEST_IA32_RFLAGS 0x6820 1223 #define VMCS_GUEST_PENDING_DBG_EXC 0x6822 1224 #define VMCS_GUEST_IA32_SYSENTER_ESP 0x6824 1225 #define VMCS_GUEST_IA32_SYSENTER_EIP 0x6826 1226 1227 /* Natural-width host state fields */ 1228 #define VMCS_HOST_IA32_CR0 0x6C00 1229 #define VMCS_HOST_IA32_CR3 0x6C02 1230 #define VMCS_HOST_IA32_CR4 0x6C04 1231 #define VMCS_HOST_IA32_FS_BASE 0x6C06 1232 #define VMCS_HOST_IA32_GS_BASE 0x6C08 1233 #define VMCS_HOST_IA32_TR_BASE 0x6C0A 1234 #define VMCS_HOST_IA32_GDTR_BASE 0x6C0C 1235 #define VMCS_HOST_IA32_IDTR_BASE 0x6C0E 1236 #define VMCS_HOST_IA32_SYSENTER_ESP 0x6C10 1237 #define VMCS_HOST_IA32_SYSENTER_EIP 0x6C12 1238 #define VMCS_HOST_IA32_RSP 0x6C14 1239 #define VMCS_HOST_IA32_RIP 0x6C16 1240 1241 #define IA32_VMX_INVVPID_INDIV_ADDR_CTX 0x0 1242 #define IA32_VMX_INVVPID_SINGLE_CTX 0x1 1243 #define IA32_VMX_INVVPID_ALL_CTX 0x2 1244 #define IA32_VMX_INVVPID_SINGLE_CTX_GLB 0x3 1245 1246 #define IA32_VMX_INVEPT_SINGLE_CTX 0x1 1247 #define IA32_VMX_INVEPT_GLOBAL_CTX 0x2 1248 1249 #define IA32_VMX_EPT_FAULT_READ (1ULL << 0) 1250 #define IA32_VMX_EPT_FAULT_WRITE (1ULL << 1) 1251 #define IA32_VMX_EPT_FAULT_EXEC (1ULL << 2) 1252 1253 #define IA32_VMX_EPT_FAULT_WAS_READABLE (1ULL << 3) 1254 #define IA32_VMX_EPT_FAULT_WAS_WRITABLE (1ULL << 4) 1255 #define IA32_VMX_EPT_FAULT_WAS_EXECABLE (1ULL << 5) 1256 1257 #define IA32_VMX_MSR_LIST_SIZE_MASK (7ULL << 25) 1258 #define IA32_VMX_CR3_TGT_SIZE_MASK (0x1FFULL << 16) 1259 1260 #define VMX_SKIP_L1D_FLUSH 2 1261 #define VMX_L1D_FLUSH_SIZE (64 * 1024) 1262 1263 /* 1264 * SVM 1265 */ 1266 #define MSR_AMD_VM_CR 0xc0010114 1267 #define MSR_AMD_VM_HSAVE_PA 0xc0010117 1268 #define CPUID_AMD_SVM_CAP 0x8000000A 1269 #define AMD_SVM_NESTED_PAGING_CAP (1 << 0) 1270 #define AMD_SVM_VMCB_CLEAN_CAP (1 << 5) 1271 #define AMD_SVM_FLUSH_BY_ASID_CAP (1 << 6) 1272 #define AMD_SVMDIS 0x10 1273 1274 #define SVM_TLB_CONTROL_FLUSH_NONE 0 1275 #define SVM_TLB_CONTROL_FLUSH_ALL 1 1276 #define SVM_TLB_CONTROL_FLUSH_ASID 3 1277 #define SVM_TLB_CONTROL_FLUSH_ASID_GLB 7 1278 1279 #define SVM_CLEANBITS_I (1 << 0) 1280 #define SVM_CLEANBITS_IOPM (1 << 1) 1281 #define SVM_CLEANBITS_ASID (1 << 2) 1282 #define SVM_CLEANBITS_TPR (1 << 3) 1283 #define SVM_CLEANBITS_NP (1 << 4) 1284 #define SVM_CLEANBITS_CR (1 << 5) 1285 #define SVM_CLEANBITS_DR (1 << 6) 1286 #define SVM_CLEANBITS_DT (1 << 7) 1287 #define SVM_CLEANBITS_SEG (1 << 8) 1288 #define SVM_CLEANBITS_CR2 (1 << 9) 1289 #define SVM_CLEANBITS_LBR (1 << 10) 1290 #define SVM_CLEANBITS_AVIC (1 << 11) 1291 1292 #define SVM_CLEANBITS_ALL \ 1293 (SVM_CLEANBITS_I | SVM_CLEANBITS_IOPM | SVM_CLEANBITS_ASID | \ 1294 SVM_CLEANBITS_TPR | SVM_CLEANBITS_NP | SVM_CLEANBITS_CR | \ 1295 SVM_CLEANBITS_DR | SVM_CLEANBITS_DT | SVM_CLEANBITS_SEG | \ 1296 SVM_CLEANBITS_CR2 | SVM_CLEANBITS_LBR | SVM_CLEANBITS_AVIC ) 1297 1298 #define SVM_INTR_MISC_V_IGN_TPR 0x10 1299 1300 /* 1301 * SVM : VMCB intercepts 1302 */ 1303 #define SVM_INTERCEPT_CR0_READ (1UL << 0) 1304 #define SVM_INTERCEPT_CR1_READ (1UL << 1) 1305 #define SVM_INTERCEPT_CR2_READ (1UL << 2) 1306 #define SVM_INTERCEPT_CR3_READ (1UL << 2) 1307 #define SVM_INTERCEPT_CR4_READ (1UL << 4) 1308 #define SVM_INTERCEPT_CR5_READ (1UL << 5) 1309 #define SVM_INTERCEPT_CR6_READ (1UL << 6) 1310 #define SVM_INTERCEPT_CR7_READ (1UL << 7) 1311 #define SVM_INTERCEPT_CR8_READ (1UL << 8) 1312 #define SVM_INTERCEPT_CR9_READ (1UL << 9) 1313 #define SVM_INTERCEPT_CR10_READ (1UL << 10) 1314 #define SVM_INTERCEPT_CR11_READ (1UL << 11) 1315 #define SVM_INTERCEPT_CR12_READ (1UL << 12) 1316 #define SVM_INTERCEPT_CR13_READ (1UL << 13) 1317 #define SVM_INTERCEPT_CR14_READ (1UL << 14) 1318 #define SVM_INTERCEPT_CR15_READ (1UL << 15) 1319 #define SVM_INTERCEPT_CR0_WRITE (1UL << 16) 1320 #define SVM_INTERCEPT_CR1_WRITE (1UL << 17) 1321 #define SVM_INTERCEPT_CR2_WRITE (1UL << 18) 1322 #define SVM_INTERCEPT_CR3_WRITE (1UL << 19) 1323 #define SVM_INTERCEPT_CR4_WRITE (1UL << 20) 1324 #define SVM_INTERCEPT_CR5_WRITE (1UL << 21) 1325 #define SVM_INTERCEPT_CR6_WRITE (1UL << 22) 1326 #define SVM_INTERCEPT_CR7_WRITE (1UL << 23) 1327 #define SVM_INTERCEPT_CR8_WRITE (1UL << 24) 1328 #define SVM_INTERCEPT_CR9_WRITE (1UL << 25) 1329 #define SVM_INTERCEPT_CR10_WRITE (1UL << 26) 1330 #define SVM_INTERCEPT_CR11_WRITE (1UL << 27) 1331 #define SVM_INTERCEPT_CR12_WRITE (1UL << 28) 1332 #define SVM_INTERCEPT_CR13_WRITE (1UL << 29) 1333 #define SVM_INTERCEPT_CR14_WRITE (1UL << 30) 1334 #define SVM_INTERCEPT_CR15_WRITE (1UL << 31) 1335 #define SVM_INTERCEPT_DR0_READ (1UL << 0) 1336 #define SVM_INTERCEPT_DR1_READ (1UL << 1) 1337 #define SVM_INTERCEPT_DR2_READ (1UL << 2) 1338 #define SVM_INTERCEPT_DR3_READ (1UL << 2) 1339 #define SVM_INTERCEPT_DR4_READ (1UL << 4) 1340 #define SVM_INTERCEPT_DR5_READ (1UL << 5) 1341 #define SVM_INTERCEPT_DR6_READ (1UL << 6) 1342 #define SVM_INTERCEPT_DR7_READ (1UL << 7) 1343 #define SVM_INTERCEPT_DR8_READ (1UL << 8) 1344 #define SVM_INTERCEPT_DR9_READ (1UL << 9) 1345 #define SVM_INTERCEPT_DR10_READ (1UL << 10) 1346 #define SVM_INTERCEPT_DR11_READ (1UL << 11) 1347 #define SVM_INTERCEPT_DR12_READ (1UL << 12) 1348 #define SVM_INTERCEPT_DR13_READ (1UL << 13) 1349 #define SVM_INTERCEPT_DR14_READ (1UL << 14) 1350 #define SVM_INTERCEPT_DR15_READ (1UL << 15) 1351 #define SVM_INTERCEPT_DR0_WRITE (1UL << 16) 1352 #define SVM_INTERCEPT_DR1_WRITE (1UL << 17) 1353 #define SVM_INTERCEPT_DR2_WRITE (1UL << 18) 1354 #define SVM_INTERCEPT_DR3_WRITE (1UL << 19) 1355 #define SVM_INTERCEPT_DR4_WRITE (1UL << 20) 1356 #define SVM_INTERCEPT_DR5_WRITE (1UL << 21) 1357 #define SVM_INTERCEPT_DR6_WRITE (1UL << 22) 1358 #define SVM_INTERCEPT_DR7_WRITE (1UL << 23) 1359 #define SVM_INTERCEPT_DR8_WRITE (1UL << 24) 1360 #define SVM_INTERCEPT_DR9_WRITE (1UL << 25) 1361 #define SVM_INTERCEPT_DR10_WRITE (1UL << 26) 1362 #define SVM_INTERCEPT_DR11_WRITE (1UL << 27) 1363 #define SVM_INTERCEPT_DR12_WRITE (1UL << 28) 1364 #define SVM_INTERCEPT_DR13_WRITE (1UL << 29) 1365 #define SVM_INTERCEPT_DR14_WRITE (1UL << 30) 1366 #define SVM_INTERCEPT_DR15_WRITE (1UL << 31) 1367 #define SVM_INTERCEPT_INTR (1UL << 0) 1368 #define SVM_INTERCEPT_NMI (1UL << 1) 1369 #define SVM_INTERCEPT_SMI (1UL << 2) 1370 #define SVM_INTERCEPT_INIT (1UL << 3) 1371 #define SVM_INTERCEPT_VINTR (1UL << 4) 1372 #define SVM_INTERCEPT_CR0_SEL_WRITE (1UL << 5) 1373 #define SVM_INTERCEPT_IDTR_READ (1UL << 6) 1374 #define SVM_INTERCEPT_GDTR_READ (1UL << 7) 1375 #define SVM_INTERCEPT_LDTR_READ (1UL << 8) 1376 #define SVM_INTERCEPT_TR_READ (1UL << 9) 1377 #define SVM_INTERCEPT_IDTR_WRITE (1UL << 10) 1378 #define SVM_INTERCEPT_GDTR_WRITE (1UL << 11) 1379 #define SVM_INTERCEPT_LDTR_WRITE (1UL << 12) 1380 #define SVM_INTERCEPT_TR_WRITE (1UL << 13) 1381 #define SVM_INTERCEPT_RDTSC (1UL << 14) 1382 #define SVM_INTERCEPT_RDPMC (1UL << 15) 1383 #define SVM_INTERCEPT_PUSHF (1UL << 16) 1384 #define SVM_INTERCEPT_POPF (1UL << 17) 1385 #define SVM_INTERCEPT_CPUID (1UL << 18) 1386 #define SVM_INTERCEPT_RSM (1UL << 19) 1387 #define SVM_INTERCEPT_IRET (1UL << 20) 1388 #define SVM_INTERCEPT_INTN (1UL << 21) 1389 #define SVM_INTERCEPT_INVD (1UL << 22) 1390 #define SVM_INTERCEPT_PAUSE (1UL << 23) 1391 #define SVM_INTERCEPT_HLT (1UL << 24) 1392 #define SVM_INTERCEPT_INVLPG (1UL << 25) 1393 #define SVM_INTERCEPT_INVLPGA (1UL << 26) 1394 #define SVM_INTERCEPT_INOUT (1UL << 27) 1395 #define SVM_INTERCEPT_MSR (1UL << 28) 1396 #define SVM_INTERCEPT_TASK_SWITCH (1UL << 29) 1397 #define SVM_INTERCEPT_FERR_FREEZE (1UL << 30) 1398 #define SVM_INTERCEPT_SHUTDOWN (1UL << 31) 1399 #define SVM_INTERCEPT_VMRUN (1UL << 0) 1400 #define SVM_INTERCEPT_VMMCALL (1UL << 1) 1401 #define SVM_INTERCEPT_VMLOAD (1UL << 2) 1402 #define SVM_INTERCEPT_VMSAVE (1UL << 3) 1403 #define SVM_INTERCEPT_STGI (1UL << 4) 1404 #define SVM_INTERCEPT_CLGI (1UL << 5) 1405 #define SVM_INTERCEPT_SKINIT (1UL << 6) 1406 #define SVM_INTERCEPT_RDTSCP (1UL << 7) 1407 #define SVM_INTERCEPT_ICEBP (1UL << 8) 1408 #define SVM_INTERCEPT_WBINVD (1UL << 9) 1409 #define SVM_INTERCEPT_MONITOR (1UL << 10) 1410 #define SVM_INTERCEPT_MWAIT_UNCOND (1UL << 11) 1411 #define SVM_INTERCEPT_MWAIT_COND (1UL << 12) 1412 #define SVM_INTERCEPT_XSETBV (1UL << 13) 1413 #define SVM_INTERCEPT_EFER_WRITE (1UL << 15) 1414 #define SVM_INTERCEPT_CR0_WRITE_POST (1UL << 16) 1415 #define SVM_INTERCEPT_CR1_WRITE_POST (1UL << 17) 1416 #define SVM_INTERCEPT_CR2_WRITE_POST (1UL << 18) 1417 #define SVM_INTERCEPT_CR3_WRITE_POST (1UL << 19) 1418 #define SVM_INTERCEPT_CR4_WRITE_POST (1UL << 20) 1419 #define SVM_INTERCEPT_CR5_WRITE_POST (1UL << 21) 1420 #define SVM_INTERCEPT_CR6_WRITE_POST (1UL << 22) 1421 #define SVM_INTERCEPT_CR7_WRITE_POST (1UL << 23) 1422 #define SVM_INTERCEPT_CR8_WRITE_POST (1UL << 24) 1423 #define SVM_INTERCEPT_CR9_WRITE_POST (1UL << 25) 1424 #define SVM_INTERCEPT_CR10_WRITE_POST (1UL << 26) 1425 #define SVM_INTERCEPT_CR11_WRITE_POST (1UL << 27) 1426 #define SVM_INTERCEPT_CR12_WRITE_POST (1UL << 28) 1427 #define SVM_INTERCEPT_CR13_WRITE_POST (1UL << 29) 1428 #define SVM_INTERCEPT_CR14_WRITE_POST (1UL << 30) 1429 #define SVM_INTERCEPT_CR15_WRITE_POST (1UL << 31) 1430 1431 /* 1432 * PAT 1433 */ 1434 #define PATENTRY(n, type) (type << ((n) * 8)) 1435 #define PAT_UC 0x0UL 1436 #define PAT_WC 0x1UL 1437 #define PAT_WT 0x4UL 1438 #define PAT_WP 0x5UL 1439 #define PAT_WB 0x6UL 1440 #define PAT_UCMINUS 0x7UL 1441 1442 /* 1443 * XSAVE subfeatures (cpuid 0xd, leaf 1) 1444 */ 1445 #define XSAVE_XSAVEOPT 0x1UL 1446 #define XSAVE_XSAVEC 0x2UL 1447 #define XSAVE_XGETBV1 0x4UL 1448 #define XSAVE_XSAVES 0x8UL 1449 1450 /* 1451 * Default cr0 and cr4 flags. 1452 */ 1453 #define CR0_DEFAULT (CR0_PE|CR0_PG|CR0_NE|CR0_WP) 1454 #define CR4_DEFAULT (CR4_PAE|CR4_PGE|CR4_PSE|CR4_OSFXSR|CR4_OSXMMEXCPT) 1455