1 /* $OpenBSD: agp_machdep.c,v 1.4 2009/06/06 06:02:44 oga Exp $ */ 2 3 /* 4 * Copyright (c) 2008 - 2009 Owain G. Ainsworth <oga@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 /* 19 * Copyright (c) 2002 Michael Shalayeff 20 * All rights reserved. 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 1. Redistributions of source code must retain the above copyright 26 * notice, this list of conditions and the following disclaimer. 27 * 2. Redistributions in binary form must reproduce the above copyright 28 * notice, this list of conditions and the following disclaimer in the 29 * documentation and/or other materials provided with the distribution. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 32 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 33 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 34 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 35 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 36 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 37 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 41 * THE POSSIBILITY OF SUCH DAMAGE. 42 */ 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcidevs.h> 52 #include <dev/pci/agpvar.h> 53 54 #include <machine/cpufunc.h> 55 #include <machine/bus.h> 56 57 #include "intagp.h" 58 59 /* bus_dma functions */ 60 61 #if NINTAGP > 0 62 void intagp_dma_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 63 bus_size_t, int); 64 #endif 65 66 void 67 agp_flush_cache(void) 68 { 69 wbinvd(); 70 } 71 72 /* 73 * functions for bus_dma used by drm for GEM 74 * 75 * We use the sg_dma backend (also used by iommu) to provide the actual 76 * implementation, so all we need provide is the magic to create the tag, and 77 * the appropriate callbacks. 78 * 79 * We give the backend drivers a chance to honour the bus_dma flags, some of 80 * these may be used, for example to provide snooped mappings (intagp). 81 * For intagp at least, we honour the BUS_DMA_COHERENT flag, though it is not 82 * used often, and is * technically to be used for dmamem_map, we use it for 83 * dmamap_load since adding coherency involes flags to the gtt pagetables. 84 * We only use it for very special circumstances since when a GTT mapping is 85 * set to coherent, the cpu can't read or write through the gtt aperture. 86 * 87 * Currently, since the userland agp driver still needs to access the gart, we 88 * only do bus_dma for a section that we've been told is ours, hence the need 89 * for the init function at present. 90 */ 91 92 int 93 agp_bus_dma_init(struct agp_softc *sc, bus_addr_t start, bus_addr_t end, 94 bus_dma_tag_t *dmat) 95 { 96 struct bus_dma_tag *tag; 97 struct sg_cookie *cookie; 98 99 /* 100 * XXX add agp map into the main queue that takes up our chunk of 101 * GTT space to prevent the userland api stealing any of it. 102 */ 103 if ((tag = malloc(sizeof(*tag), M_DEVBUF, 104 M_WAITOK | M_CANFAIL)) == NULL) 105 return (ENOMEM); 106 107 if ((cookie = sg_dmatag_init("agpgtt", sc->sc_chipc, start, end - start, 108 sc->sc_methods->bind_page, sc->sc_methods->unbind_page, 109 sc->sc_methods->flush_tlb)) == NULL) { 110 free(tag, M_DEVBUF); 111 return (ENOMEM); 112 } 113 114 tag->_cookie = cookie; 115 tag->_dmamap_create = sg_dmamap_create; 116 tag->_dmamap_destroy = sg_dmamap_destroy; 117 tag->_dmamap_load = sg_dmamap_load; 118 tag->_dmamap_load_mbuf = sg_dmamap_load_mbuf; 119 tag->_dmamap_load_uio = sg_dmamap_load_uio; 120 tag->_dmamap_load_raw = sg_dmamap_load_raw; 121 tag->_dmamap_unload = sg_dmamap_unload; 122 tag->_dmamem_alloc = sg_dmamem_alloc; 123 tag->_dmamem_free = _bus_dmamem_free; 124 tag->_dmamem_map = _bus_dmamem_map; 125 tag->_dmamem_unmap = _bus_dmamem_unmap; 126 tag->_dmamem_mmap = _bus_dmamem_mmap; 127 128 /* Driver may need special sync handling */ 129 if (sc->sc_methods->dma_sync != NULL) { 130 tag->_dmamap_sync = sc->sc_methods->dma_sync; 131 } else { 132 tag->_dmamap_sync = _bus_dmamap_sync; 133 } 134 135 *dmat = tag; 136 return (0); 137 } 138 139 void 140 agp_bus_dma_destroy(struct agp_softc *sc, bus_dma_tag_t dmat) 141 { 142 struct sg_cookie *cookie = dmat->_cookie; 143 144 145 /* 146 * XXX clear up blocker queue 147 */ 148 149 sg_dmatag_destroy(cookie); 150 free(dmat, M_DEVBUF); 151 } 152 153 void 154 agp_bus_dma_set_alignment(bus_dma_tag_t tag, bus_dmamap_t dmam, 155 u_long alignment) 156 { 157 sg_dmamap_set_alignment(tag, dmam, alignment); 158 } 159 160 161 /* 162 * ick ick ick. However, the rest of this driver is supposedly MI (though 163 * they only exist on x86), so this can't be in dev/pci. 164 */ 165 166 #if NINTAGP > 0 167 168 /* 169 * bus_dmamap_sync routine for intagp. 170 * 171 * This is tailored to the usage that drm with the GEM memory manager 172 * will be using, since intagp is for intel IGD, and thus shouldn't be 173 * used for anything other than gpu-based work. Essentially for the intel GEM 174 * driver we use bus_dma as an abstraction to convert our memory into a gtt 175 * address and deal with any cache incoherencies that we create. 176 * 177 * We use the cflush instruction to deal with clearing the caches, since our 178 * cache is physically indexed, we can even map then clear the page and it'll 179 * work. on i386 we need to check for the presence of cflush() in cpuid, 180 * however, all cpus that have a new enough intel GMCH should be suitable. 181 */ 182 void 183 intagp_dma_sync(bus_dma_tag_t tag, bus_dmamap_t dmam, 184 bus_addr_t offset, bus_size_t size, int ops) 185 { 186 #ifdef DIAGNOSTIC 187 if ((ops & (BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)) != 0 && 188 (ops & (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)) != 0) 189 panic("agp_dmamap_sync: mix PRE and POST"); 190 if (offset >= dmam->dm_mapsize) 191 panic("_intagp_dma_sync: bad offset %lu (size = %lu)", 192 offset, dmam->dm_mapsize); 193 if (size == 0 || (offset + size) > dmam->dm_mapsize) 194 panic("intagp_dma_sync: bad length"); 195 #endif /* DIAGNOSTIC */ 196 197 /* Coherent mappings need no sync. */ 198 if (dmam->_dm_flags & BUS_DMA_COHERENT) 199 return; 200 201 /* 202 * We need to clflush the object cache in all cases but postwrite. 203 * 204 * - Due to gpu incoherency, postread we need to flush speculative 205 * reads (which are not written back on intel cpus). 206 * 207 * - preread we need to flush data which will very soon be stale from 208 * the caches 209 * 210 * - prewrite we need to make sure our data hits the memory before the 211 * gpu hoovers it up. 212 * 213 * The chipset also may need flushing, but that fits badly into 214 * bus_dma and it done in the driver. 215 */ 216 if (ops & BUS_DMASYNC_POSTREAD || ops & BUS_DMASYNC_PREREAD || 217 ops & BUS_DMASYNC_PREWRITE) { 218 /* XXX use clflush */ 219 wbinvd(); 220 } 221 } 222 #endif 223